International Journal of Circuit Theory and Applications

Cover image for Vol. 39 Issue 2

February 2011

Volume 39, Issue 2

Pages 91–209

  1. Research Articles

    1. Top of page
    2. Research Articles
    3. Letter to the editor
    1. Using modal series to analyze the transient response of oscillators (pages 127–134)

      Mahmood Khatibi and Hasan Modir Shanechi

      Version of Record online: 3 AUG 2009 | DOI: 10.1002/cta.621

    2. A 14b 150 MS/s 140 mW 2.0 mm2 0.13µm CMOS A/D converter for software-defined radio systems (pages 135–147)

      Hee-Cheol Choi, Pil-Seon Yoo, Gil-Cho Ahn and Seung-Hoon Lee

      Version of Record online: 18 JAN 2010 | DOI: 10.1002/cta.622

      Thumbnail image of graphical abstract

      This work proposes a 14 b 150 MS/s CMOS A/D converters (ADC) for software-defined radio systems requiring simultaneously high-resolution, low-power, and small chip area at high speed. The proposed calibration-free ADC employs a wide-band low-noise input sample-and-hold amplifier (SHA) along with a four-stage pipelined architecture optimizing scaling-down factors for the sampling capacitance and the input trans-conductance of amplifiers in each stage to minimize thermal noise effect and power consumption. Copyright © 2010 John Wiley & Sons, Ltd.

    3. On IIR-based bit-stream multipliers (pages 149–158)

      Chiu-Wa Ng, Ngai Wong, Hayden Kwok-Hay So and Tung-Sang Ng

      Version of Record online: 18 JAN 2010 | DOI: 10.1002/cta.623

      Thumbnail image of graphical abstract

      We analyze the existing IIR-based bi-level bit-stream multiplier and propose a design guideline for the key design parameter. We then generalize the IIR-based design to tri- and quad-level architectures which achieve better signal-to-noise performance. The hardware complexity in terms of FPGA resources and noise performance of these designs are contrasted with each other and also with previously proposed FIR-based bit-stream multipliers. Copyright © 2010 John Wiley & Sons, Ltd.

    4. Non-invasive chaos control of DC–DC converter and its optimization (pages 159–174)

      Lu Wei-Guo, Zhou Luo-Wei, Luo Quan-Ming and Wu Jun-Ke

      Version of Record online: 22 MAR 2010 | DOI: 10.1002/cta.626

      Thumbnail image of graphical abstract

      A novel non-invasive chaos control based on its frequency-domain form is presented and a new Jacobian-matrix stability analysis method for PWM-controlled DC-DC converter system is proposed as well. The experiment results show a good dynamic control effect with the optimal control parameters. Copyright © 2010 John Wiley & Sons, Ltd.

    5. Modeling of switching frequency instabilities in buck-based DC–AC H-bridge inverters (pages 175–193)

      Abdelali El Aroudi, Enric Rodriguez, Mohamed Orabi and Eduard Alarcón

      Version of Record online: 18 JAN 2010 | DOI: 10.1002/cta.627

      Thumbnail image of graphical abstract

      In this paper, the dynamical behavior of a full bridge DC-AC buck inverter controlled by fixed frequency and PWM is studied. After showing that the system can undergo both period-doubling and Neimark-Sacker bifurcation at the fast scale (switching period) by using the exact switching model, an exact solution discrete-time model able to predict both instability phenomena is derived. The model is obtained without making the quasi-static approximation and it can be used to obtain the useful operation region in the multidimensional design parameter space from time domain simulations in a very fast and accurate manner. Based on the study of the system, some design guidelines are provided. Copyright © 2010 John Wiley & Sons, Ltd.

    6. An analog cell and its applications in analog signal processing (pages 195–201)

      Hamed Sajjadi-Kia

      Version of Record online: 22 MAR 2010 | DOI: 10.1002/cta.628

      Thumbnail image of graphical abstract

      Transistor-level implementation of the proposed squarer circuit. This paper presents a straightforward current-mode CMOS squarer circuit. The proposed circuit exploits the square-law characteristic of MOS transistor in saturation region. The squarer circuit is then used to implement multiplier and exponential functions. To demonstrate the method, circuits are designed in 0:35 µm CMOS process, using single 3:3 V supply. HSPICE simulations, with level 49 model parameters, confirm the operation of the proposed CMOS circuits. Copyright © 2010 John Wiley & Sons, Ltd.

  2. Letter to the editor

    1. Top of page
    2. Research Articles
    3. Letter to the editor
    1. You have free access to this content
      Improved control-to-output characteristics of a PWM buck-boost converter (pages 203–209)

      Yu-Kang Lo, Jun-Ting Chen, Chung-Yi Lin and Sheng-Yuan Ou

      Version of Record online: 22 MAR 2010 | DOI: 10.1002/cta.624

      Thumbnail image of graphical abstract

      An indirect control variable for improving the control-to-output characteristics of a PWM buck-boost converter is introduced. The resulting voltage gain function appears proportional to this indirect control command. In addition the dependence of the DC gain of the control-to-output transfer function on the duty cycle is eliminated. The implementation of the presented controller requires additional analog ICs. Nevertheless, the proposed control method can be fulfilled via digital approach as well, and applied to any buck-boost derived converter topologies. Copyright © 2010 John Wiley & Sons, Ltd.

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