A new power aware multiplier design based onWallace tree is presented using high order counters. Multipliers of widths of 8, 16, and 32-bits are designed based on the proposed algorithm. Simulations showed that the design achieves an average of 18.6% power reduction compared to the original Wallace tree. The design performs even better as the multipliers size increases, achieving a 5% gate count reduction, a 26.5% power reduction, and a 23.9% better power-delay product in 32-bit multipliers.. Copyright © 2010 John Wiley & Sons, Ltd.