International Journal of Circuit Theory and Applications

Cover image for Vol. 40 Issue 11

November 2012

Volume 40, Issue 11

Pages 1085–1185

  1. Research Articles

    1. Top of page
    2. Research Articles
    1. A novel variable frequency modulation technique to improve light-load efficiency for multiphase synchronous rectified VRM (pages 1085–1105)

      Sheng-Yuan Ou, Ho-Pu Hsiao and Huei-Fa Su

      Article first published online: 23 MAR 2011 | DOI: 10.1002/cta.773

      Thumbnail image of graphical abstract

      A novel variable frequency modulation technique for multiphase synchronous rectified VRM is proposed in this paper. The proposed technique provides ZVS for power switches under both light and heavy load conditions and thereby increasing the efficiency. The frequency increases for light load condition in order to retain ZVS and decrease the conduction loss. The efficiency can be increased up to 17% and 5% for single-phase VRM and 8% and 4% for eight-phase VRM under various load conditions. Even an off-the shelf controller with additional simple and cheap control circuit comprising one switch, a very low cost and small circuitry is attached to gain the significant benefits. Copyright © 2011 John Wiley & Sons, Ltd.

    2. VLSI implementation of a configurable IP Core for quantized discrete cosine and integer transforms (pages 1107–1126)

      Chi-Chia Sun, Philipp Donner and Jürgen Götze

      Article first published online: 29 MAR 2011 | DOI: 10.1002/cta.774

      Thumbnail image of graphical abstract

      Circuit design of an IP core for supporting both QDCT and quantized integer transform is presented, which is based on iterative CORIDC architecture. The result of configurable transformations and arbitrary scaling procedures is very suitable for lowcomplexityand highperformance Codecs for the next generation UHD resolution devices. Copyright © 2011 John Wiley & Sons, Ltd.

    3. Pulse current generator for driving tubular field emission lamp based on DCM flyback converter (pages 1127–1141)

      Chang-Hua Lin, Chien-Ming Wang, Min-Hsuan Hung and Ying Lu

      Article first published online: 1 APR 2011 | DOI: 10.1002/cta.775

      Thumbnail image of graphical abstract

      This paper implements a pulse current generator operated in discontinuous conduction mode for driving a tubular field emission lamp. The proposed system based on flyback topology can provide pulse-type power driving to eliminate the temperature rise and arcing phenomenon caused by the traditional constant voltage driving. Therefore, both the lighting efficiency and lamp lifespan are improved. Copyright © 2010 John Wiley & Sons, Ltd.

    4. Power-efficient analog design based on the class AB super source follower (pages 1143–1163)

      Antonio J. Lopez-Martin, Lucia Acosta, Coro Garcia-Alberdi, Ramon G. Carvajal and Jaime Ramirez-Angulo

      Article first published online: 19 APR 2011 | DOI: 10.1002/cta.776

      Thumbnail image of graphical abstract

      A new technique for low-voltage power-efficient analog design is presented, based on a class AB version of the Super Source Follower as basic building block. Measurement results of various applications (buffers, current mirrors and transconductors) confirm the advantages of the proposed technique. Copyright © 2011 John Wiley & Sons, Ltd.

    5. On global asymptotic stability for a class of delayed neural networks (pages 1165–1174)

      James Lam, Shengyuan Xu, Daniel W. C. Ho and Yun Zou

      Article first published online: 29 MAR 2011 | DOI: 10.1002/cta.777

      This paper deals with the stability analysis for a class of delayed neural networks described by nonlinear delay differential equations of the neutral type. A new and simple sufficient condition guaranteeing the existence, uniqueness and global asymptotic stability of an equilibrium point of such a kind of delayed neural networks is developed. When the stability condition is applied to the more commonly encountered delayed neural networks, it is shown that our result can be less conservative. Copyright © 2011 John Wiley & Sons, Ltd.

    6. Low power Wallace multiplier design based on wide counters (pages 1175–1185)

      Sa'ed Abed, Bassam Jamil Mohd, Zaid Al-bayati and Sahel Alouneh

      Article first published online: 23 MAY 2011 | DOI: 10.1002/cta.779

      Thumbnail image of graphical abstract

      A new power aware multiplier design based onWallace tree is presented using high order counters. Multipliers of widths of 8, 16, and 32-bits are designed based on the proposed algorithm. Simulations showed that the design achieves an average of 18.6% power reduction compared to the original Wallace tree. The design performs even better as the multipliers size increases, achieving a 5% gate count reduction, a 26.5% power reduction, and a 23.9% better power-delay product in 32-bit multipliers.. Copyright © 2010 John Wiley & Sons, Ltd.

SEARCH

SEARCH BY CITATION