Hardware decoder for turbo trellis-coded modulations with higher-order modulation schemes
Article first published online: 13 DEC 2006
DOI: 10.1002/ecjc.20252
Copyright © 2006 Wiley Periodicals, Inc.
Issue
1520-6440/asset/cover.gif?v=1&s=5dcbd8b5581795810e209e1f34ba941dd2b64c08)
Electronics and Communications in Japan (Part III: Fundamental Electronic Science)
Volume 90, Issue 4, pages 27–38, April 2007
Additional Information
How to Cite
Shohon, T., Koshi, K., Tamura, M. and Ogiwara, H. (2007), Hardware decoder for turbo trellis-coded modulations with higher-order modulation schemes. Electron. Comm. Jpn. Pt. III, 90: 27–38. doi: 10.1002/ecjc.20252
Publication History
- Issue published online: 13 DEC 2006
- Article first published online: 13 DEC 2006
Funded by
- JSPS Science Research Grant, Basic Research (C) 15560321.
- Abstract
- References
- Cited By
Keywords:
- turbo code;
- trellis-coded modulation;
- hardware;
- decoder
Abstract
This paper discusses the realization of a hardware decoder for turbo trellis-coded modulation with high-order modulation levels. In order to avoid an increase of decoding processing with the increase of modulation levels, a simplified decoding algorithm based on Max-log MAP is considered, and a method for fast execution is proposed. When the proposed decoding procedure is used, the amount of computation can be reduced to approximately 1/25 of that by Max-log MAP without degrading the performance (when the number of states in the element encoder is 8 and the number of input bits is 7). In order to realize the hardware decoder, the number of bits needed for each variable is analyzed. Then an efficient design procedure for the path metric module is presented. As an example of the design of a hardware decoder based on these investigations, the design of a turbo TCM decoder for 256QAM is presented. © 2006 Wiley Periodicals, Inc. Electron Comm Jpn Pt 3, 90(4): 27 – 38, 2007; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/ecjc.20252
