Employing reduced surface field technique by a P-type region in 4H-SiC metal semiconductor field effect transistors for increasing breakdown voltage
Article first published online: 21 MAR 2012
Copyright © 2012 John Wiley & Sons, Ltd.
International Journal of Numerical Modelling: Electronic Networks, Devices and Fields
Volume 26, Issue 2, pages 103–111, March/April 2013
How to Cite
Moghadam, H. A., Orouji, A. A. and Jamali Mahabadi, S. E. (2013), Employing reduced surface field technique by a P-type region in 4H-SiC metal semiconductor field effect transistors for increasing breakdown voltage. Int. J. Numer. Model., 26: 103–111. doi: 10.1002/jnm.1836
- Issue published online: 12 FEB 2013
- Article first published online: 21 MAR 2012
- Manuscript Accepted: 13 FEB 2012
- Manuscript Revised: 31 OCT 2011
- Manuscript Received: 7 SEP 2011
- metal semiconductor field effect transistor;
- breakdown voltage;
- two-dimensional (2D) simulation
In this paper, we employ the Reduced Surface Field technique in metal semiconductor field effect transistors (MESFETs) by a P-type region above the active layer near gate (PR-MESFET). Electric field distribution can be made more uniform by a new depletion region in the active layer of the proposed structure that is created by a P-type region. Therefore, the electric field peak at the gate edge decreases, and the breakdown voltage increases. On the basis of our simulation results, the breakdown voltage increases as compared with the conventional bulk 4H-SiC MESFET (CB-MESFET) and the spacer bulk 4H-SiC MESFET (SB-MESFET). Detailed numerical simulations demonstrate that for proposed structure due to decrease in parasitic gate-to-drain capacitor, maximum oscillation frequency increases with respect to SB-MESFET. Our simulation results show that output current slightly decreases in comparison with CB-MESFET. Copyright © 2012 John Wiley & Sons, Ltd.