Electrical–thermal modeling of through-silicon via (TSV) arrays in interposer

Authors

  • Jianyong Xie,

    Corresponding author
    1. Interconnect and Packaging Center (IPC), School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA
    • Correspondence to: Jianyong Xie, Interconnect and Packaging Center (IPC), School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA 30332, USA.

      E-mail: jianyong.xie@gatech.edu

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  • Biancun Xie,

    1. Interconnect and Packaging Center (IPC), School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA
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  • Madhavan Swaminathan

    1. Interconnect and Packaging Center (IPC), School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA
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SUMMARY

In this paper, electrical–thermal modeling of through-silicon via (TSV) arrays is presented. In order to address the thermal effect on TSVs, TSV array design and modeling need to take into account the effect of realistic system thermal profile to meet design budget. To obtain temperature estimation for a 3D system, cascadic multigrid method is employed using an initial guess obtained by simulation using equivalent thermal conductivity to represent critical regions. By considering the thermal effect on electrical conductivities of TSV conductor and silicon substrate, the electrical–thermal modeling of TSV array in the interposer is carried out using cylindrical modal basis functions. The temperature effect on TSV insertion loss, crosstalk, and RLCG parameters are discussed with examples along with correlation with measurements. Copyright © 2012 John Wiley & Sons, Ltd.

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