Implementation of the symmetric doped double-gate MOSFET model in Verilog-A for circuit simulation

Authors

  • Joaquín Alvarado,

    Corresponding author
    1. Microelectronics Laboratory, Université catholique de Louvain, Place du Levant 3, B-1348, Louvain-la-Neuve, Belgium
    • Microelectronics Laboratory, Université catholique de Louvain, Place du Levant 3, B-1348, Louvain-la-Neuve, Belgium
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  • Benjamin Iñiguez,

    1. Department of Electronic Engineering, Universitat Rovira i Virgili, Avinguda dels Paisos Catalans 26, 43007, Tarragona, Spain
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  • Magali Estrada,

    1. Centro de Investigación y de Estudios Avanzados del I.P.N., Av. I.P.N. No. 2508, Col. San Pedro Zacatenco, C.P. 07360, México, D.F.
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  • Denis Flandre,

    1. Microelectronics Laboratory, Université catholique de Louvain, Place du Levant 3, B-1348, Louvain-la-Neuve, Belgium
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  • Antonio Cerdeira

    1. Centro de Investigación y de Estudios Avanzados del I.P.N., Av. I.P.N. No. 2508, Col. San Pedro Zacatenco, C.P. 07360, México, D.F.
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Abstract

Recently we developed a model for symmetric double-gate MOSFETs (SDDGM) that, for the first time, considers the doping concentration in the Si film in the complete range from 1×1014 to 3×1018 cm−3. The model covers a wide range of technological parameters and includes short channel effects. It was validated for different devices using data from simulations, as well as measured in real devices. In this paper, we present the implementation in Verilog-A code of this model, which allows its introduction in commercial simulators. The Verilog-A implementation was optimized to achieve reduction in computational time, as well as good accuracy. Results are compared with data from 2D simulations, showing a very good agreement in all transistor operation regions. Copyright © 2009 John Wiley & Sons, Ltd.

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