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Fast estimation of RL-loaded microelectronic interconnections delay for the signal integrity prediction


Blaise Ravelo, IRSEEM (Research Institute in Electronic and Embedded Systems), EA 4353, Graduate School of Engineering ESIGELEC, Technopole du Madrillet, Avenue Galilée, BP 10024, 76801 Saint Etienne du Rouvray Cedex, France.



This article presents a modelling method of the signal delays induced by microelectronic interconnections regarding RL impedance load. The method proposed is based on the RLC model of the transmission lines (TL) extracted from the equivalent S parameters. Formulation for estimating the interconnection propagation delay is established according to the behaviour of the TL unit step responses. The second order model is validated with a microstrip interconnect prototype with simulations and measurements in frequency and time domains. The developed propagation delay model was validated with SPICE computations. For that, a transient simulation was performed by considering input signals corresponding to high-speed data of some Gbits/s. Then, accurate results were found for interconnections with different lengths in order of millimetre and also by varying the load values. It was shown that the computed 50% propagation delays present of relative errors about 5%. Copyright © 2011 John Wiley & Sons, Ltd.