Research Article

Design of a 4.2–5.4 GHz differential LC VCO using 0.35 μm SiGe BiCMOS technology for IEEE 802.11a applications

  1. Onur Esame,
  2. Ibrahim Tekin,
  3. Ayhan Bozkurt,
  4. Yasar Gurbuz*

Article first published online: 1 MAR 2007

DOI: 10.1002/mmce.20218

Issue

International Journal of RF and Microwave Computer‐Aided Engineering

International Journal of RF and Microwave Computer-Aided Engineering

Volume 17, Issue 2, pages 243–251, March 2007

Additional Information

How to Cite

Esame, O., Tekin, I., Bozkurt, A. and Gurbuz, Y. (2007), Design of a 4.2–5.4 GHz differential LC VCO using 0.35 μm SiGe BiCMOS technology for IEEE 802.11a applications. Int J RF and Microwave Comp Aid Eng, 17: 243–251. doi: 10.1002/mmce.20218

Author Information

  1. Sabanci University, Faculty of Engineering and Natural Sciences, Orhanli, Tuzla, 34956 Istanbul, Turkey

*Sabanci University, Faculty of Engineering and Natural Sciences, Orhanli, Tuzla, 34956 Istanbul, Turkey

Publication History

  1. Issue published online: 14 MAR 2007
  2. Article first published online: 1 MAR 2007
  3. Manuscript Accepted: 21 APR 2006
  4. Manuscript Received: 30 JAN 2006

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Keywords:

  • VCO;
  • SiGe;
  • BiCMOS;
  • WLAN;
  • differential tuning;
  • accumulation MOS varactors;
  • RFIC

Abstract

In this paper, a 4.2–5.4 GHz, −Gm LC voltage controlled oscillator (VCO) for IEEE 802.11a standard is presented. The circuit is designed with AMS 0.35 μm SiGe BiCMOS process that includes high-speed SiGe Heterojunction Bipolar Transistors (HBTs). According to post-layout simulation results, phase noise is −110.7 dBc/Hz at 1 MHz offset from 5.4 GHz carrier frequency and −113.4 dBc/Hz from 4.2 GHz carrier frequency. A linear, 1200 MHz tuning range is obtained from the simulations, utilizing accumulation-mode varactors. Phase noise was also found to be relatively low because of taking advantage of differential tuning concept. Output power of the fundamental frequency changes between 4.8 dBm and 5.5 dBm depending on the tuning voltage. Based on the simulation results, the circuit draws 2 mA without buffers and 14.5 mA from 2.5 V supply including buffer circuits leading to a total power dissipation of 36.25 mW. The circuit layout occupies an area of 0.6 mm2 on Si substrate, including DC and RF pads. © 2007 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2007.

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