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Effect of lattice mismatch on gate lag in high quality InAlN/AlN/GaN HFET structures

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Abstract

Grown lattice matched to GaN, InAlN-based heterojunction field effect transistors (HFETs) are promising due to the relatively large band discontinuity at the interface and lack of misfit strain. Despite the recent progress in the growth, there still exists some questions as to the true lattice matching condition of InAlN to GaN due to discrepancies in the value of the lattice parameters of the InN binary, as well as the literature value of the InAlN bowing parameters. In order to address this, we used the gate lag as a supplementary measurement to verify lattice matching to the underlying GaN, as strain-free layers would not have piezoelectric charge at the surface, which would be one source of lag. We observe very low lag for a nearly lattice matched barrier, and a marked increase as the composition deviates from the lattice matched condition. Additionally, FETs fabricated on a nearly matched layer boast a maximum drain current of over 1.5 and ∼2.0 A/mm and transconductances of ∼275 and ∼300 mS/mm at DC and in pulsed modes, respectively, and a cutoff frequency of 15.9 GHz (an fT*LG product of 10.3) for a gate length of 0.65 µm.

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