Pre-patterned silicon substrates for the growth of III–V nanostructures

Authors


Abstract

This paper reviews the recent progresses obtained by direct growth of III–V semiconductor quantum dots (QDs) on pre-patterned and flat silicon substrates. This combination allows us to study in detail the growth mechanisms of III–V materials on silicon substrates. For the flat surfaces, we concentrate on basic growth studies addressing mainly morphological properties of QD-like structures with a main emphasis on surface preparation and growth parameters. For the pre-patterned substrates, we report the optimization of electron beam lithography and dry etching processes to fabricate sub-100 nm holes in pre-patterned Si (100) substrates with controlled size, shape, and periodicity. The pre-patterned silicon substrates underwent thorough ex situ chemical and in situ cleaning processes before the molecular beam epitaxy (MBE) growth. Finally, the MBE growth sequence of QDs on patterned silicon surface has shown highly selective formation of localized dome like nanostructures in patterned holes with 1 µm period.

original image

A 3D AFM image of a single nanohole in silicon substrate with diameter and depth of about 70 nm.

1 Introduction

Silicon is the main material for various semiconductor devices with approximately 90% of the semiconductor industry. However, indirect nature of the silicon band structure prevents the realization of efficient light emitting devices. On the other hand, III–V materials, due to their excellent optical properties and optoelectronic capabilities, are widely utilized in conventional photonic devices such as lasers and LEDs. Integration of III–V semiconductor compound light sources with silicon 1–9 is highly sought for the realization of photonic integrated circuits using the well-established complementary metal-oxide-semiconductor (CMOS) fabrication technologies. In particular, optical interconnect systems 10, 11 provide a promising approach for the realization of the next generation high-speed communication and computing technologies.

In the last three decades, different approaches have been utilized such as SiGe/Si short period superlattices 12, or defect atoms (e.g. rare earth atoms) 13 to allow optical transitions in silicon matrix. Recently, several approaches are under exploration based on a hybrid combination of III–V and silicon material, e.g. by nanowire growth 14, wafer fusion techniques 15, using thick relaxation layers 16, or applying lattice matched material compositions 17. However, the growth of these buffer layers increases the process complexity and material cost. For III–V/Si hybrid integration, direct epitaxial growth of III–V compounds on silicon substrates would be the most desirable approach, because only silicon processing is required as is already used in passive silicon photonics. Nevertheless, heteroepitaxial growth typically introduces a substantial crystalline defect density 18–21. As a result, the presence of high-density threading dislocations due to the lattice mismatch and the formation of antiphase boundaries due to the polar non-polar nature of the III–V/IV semiconductor system propagating through the active material will become a non-radiative recombination centre, which will destroy the light emission 22–24. Growth on pre-patterned substrates could result in reducing or eliminating such defects due to size effect and effective lateral stress relaxation related to the presence of facet edges and sidewalls 25–28.

In contrast to the III–V/IV systems, tremendous progress in the growth of In(Ga)As quantum dots (QDs) on pre-patterned GaAs substrates has been made 29–31. Site-controlled In(Ga)As QDs with very narrow linewidth photoluminescence signal have been achieved both in inverted pyramidal 32–35 and round-shaped nanoholes 36, 37. A detail of specific lithographic process for the pre-patterning of silicon surface with sub-100 nm holes for the MBE overgrowth has not been reported explicitly in the literature as the site-controlled growth of QDs on silicon is a relatively new field. Therefore, we have carried out considerable work in order to develop and optimize an etching process suitable for the purpose of over-growth on pre-patterned silicon. In recent years, some research efforts have also been made to realize the growth of III/V QDs on pre-patterned silicon substrates using SiO2 as a mask which show encouraging results 24, 38. For such fabrications, several lithographic techniques are in use for pre-patterning silicon substrates, such as focused ion beam (FIB), scanning probe techniques and electron beam lithography (EBL). However, the EBL is the most widely used technique to fabricate features even in sub-10 nm range 39.

This article is organized as follows: Section 2 provides experimental details on sample growth and processing. Section 3 presents basic growth studies addressing mainly morphological properties of QD-like structures grown directly on silicon surfaces with the main emphasis on growth parameters. In Section 4, we show the results of optimized EBL and dry etching processes for the patterning of silicon substrates with sub-100 nm holes and the MBE growth of III–V nanostructures on pre-patterned silicon surfaces. Section 5 provides preliminary results towards the full nucleation control of III–V material in the nanoholes using an optimized in situ cleaning.

2 Sample growth and processing

All samples discussed here were grown on exactly oriented n-type (100) silicon substrates. The growth was performed by a GEN II Varian molecular beam epitaxy (MBE) system. This III–V MBE system was modified by installing an additional silicon e-beam evaporator and high silicon substrate heater to allow silicon homo-epitaxy within an III–V environment. In contrast to the earlier work, where the maximum substrate temperatures were limited by a standard III–V substrate heater to about 800 °C, which restricts, for example an optimum surface preparation. The high temperature manipulator in the modified MBE system permits substrate heating up to 1200 °C and the e-beam evaporator cell allows growth rates in the range of 200–300 nm h−1. There are two different growth types of QDs studied in the following sections. The first type consists of direct growth on silicon surfaces. The substrates were ex situ cleaned using buffered HF (NH4/HF:H2O) (1:1) for 4 min as a pre-removal step of the surface native oxide followed by an in situ thermal atomic hydrogen (AH) assisted surface cleaning process at 500 °C (45 min with PH = 3.7 × 10−7 Torr) in the buffer chamber. The final thermal oxide desorption was done in the growth chamber within the temperature range of 700–915 °C. The surface quality and the dots formation process are monitored in situ by reflection high-energy diffraction (RHEED). Additional improvement for the cleaning and growth was achieved by exposing the silicon surface with Ga at low fluxes (0.1 ML s−1). The influences of different growth parameters, such as growth temperature, V/III ratio and In-growth rate, on the structural properties of InAs QDs are investigated. For the second type, the silicon substrates are pre-patterned using EBL and dry etching. The substrate was cleaned for 2 min each in acetone and isopropyl alcohol (IPA) and spin coated with positive tone electron beam resist PMMA to achieve a thickness of about 200 nm. The resist was then exposed to define sub-100 nm holes by Raith e-LINE EBL system using single pixel dot exposure. After the exposure the resist was developed with standard MIBK:IPA (1:3) solution. The nanoholes pattern was then transferred to the Si substrate by an optimized dry etch process using Plasmalab System100 machine. The resist was then removed by soaking the substrate in acetone for 5 min. The substrate was further cleaned in IPA at 80 °C for 10 min and in oxygen plasma asher for 30 min to remove any residual resist particles and carbon contamination left after the lithographic processing. Finally the substrate was cleaned with HF/H2O (1:2) solution for 2 min to remove the native oxide. The substrates were then loaded into the MBE system within 10 min of ex situ chemical cleaning.

3 Direct quantum dot growth on silicon surfaces

In this section, the influence of the growth parameters on the structural properties (size, density and shape) of InAs QDs such as: V/III ratio and growth temperature are investigated. For more details see Ref. 21. Surface cleaning is a first step to be examined to establish high quality silicon surfaces for III/V overgrowth by removing impurities and contaminations. The silicon substrate surfaces were prepared ex situ using buffered HF (NH4/HF:H2O) (1:1) for 4 min as a pre-removal step of the surface native oxide followed by an in situ thermal oxide desorption at 910 °C for 15 min as inferred from single crystalline surface according to RHEED patterns depicted in Fig. 1b. RHEED streak patterns with hemispherical shapes were observed after AH cleaning followed by thermal oxide desorption at 700 °C as shown in Fig. 1c. This is an indication of a clean 2D crystalline surface compared to a diffused RHEED pattern (amorphous surface) obtained before the cleaning treatment as displayed in Fig. 1a. Thermal desorption accompanied with hydrogen treatment is an efficient method to prepare a clean 2D crystalline surface, which is in agreement with literature that the hydrogen cleaning is effective in removing the oxides and carbon contaminations from the silicon surfaces 40, 41.

Figure 1.

(online colour at: www.pss-a.com) Top row: RHEED streak patterns: (a) Before the in situ cleaning, the diffused scattering indicates an amorphous surface, (b) with thermal oxide desorption at 900 °C, (c) with AH cleaning followed by thermal oxide desorption at 700 °C. RHEED streak patterns with hemispherical shapes in (b) and (c) indicate a clean 2D crystalline surface. Middle row: AFM images (1 × 1 µm2) of 2 MLs InAs QDs grown using SK mode with different V/III ratios: (d) 15, (e) 25, and (f) 35, QD density increases strongly with increasing V/III ratio. Bottom row: AFM images (1 × 1 µm2) of 2 MLs InAs QDs grown using SK mode at different growth temperatures (g) 400 °C, (h) 450 °C, and (i) 500 °C. No QDs formation at 500 °C is observed due to indium desorption.

After the surface preparation, the QDs were directly grown on silicon. Different growth parameters were examined. It was found that by increasing the V/III ratio from 15 to 35, the density of InAs QDs is strongly modified and increased from approximately 108 cm−2 (Fig. 1d) to approximately 1011 cm−2 (Fig. 1f). This is a clear indication that the arsenic flux is an important parameter to control the QD density. Atomic force microscopy (AFM) images in Fig. 1g–h show that the InAs QD density is slightly increased with increasing the growth temperature in the range of 400–450 °C, which is opposite to the growth on III–V substrates. The QD lateral dimensions and average heights (Hav) decreased from L = 33–55 nm and Hav = 6.62 nm at 400 °C (Fig. 1g) to values of L = 15–40 nm and Hav = 4.5 nm at 450 °C (Fig. 1h). The main reason of these changes is related to the indium desorption which starts to be significant at 450 °C (Fig. 1b). This causes a reduction of the dot sizes at 450 °C and do not allow any InAs nucleation at 500 °C (Fig. 1c), which is in agreement with literature where no nanoislands formation are observed at temperatures higher than 450 °C 42. It should be noted that the shape and size of InAs QDs (data not shown) are significantly changed by increasing the indium growth rate from 108 nm h−1 (0.1 ML s−1) to 324 nm h−1 (0.3 ML s−1). It seems that a reduction of the formation time can switch the InAs QD from circular to dash shape; this dash structures is preferentially oriented on [110] crystal direction. This is due to the preferential migration of indium atoms along [110] crystal direction which results from the anisotropic migration lengths and stress relaxation along different crystal directions.

To conclude this section, we have successfully grown QDs directly on silicon substrate. The QDs show different structural properties with varying the growth parameters. Despite the great efforts, the direct III–V structures growth on silicon show no light emission. However, recent TEM characterizations illustrate a completely relaxed and defect-free small QDs embedded in a defect-free silicon matrix (under investigation 43). These are in fact encouraging results, which through further growth optimization, e.g. by introducing a thin GaP layer on mis-oriented silicon substrate; the light emission could be feasible. An alternative approach which will be discussed in the following sections is to nucleate the InAs in sub-100 nm holes on pre-patterned silicon substrates. It is expected to reduce or eliminate the anti-phase domains which are one of the main causes in destroying the light emission.

4 MBE growth on patterned silicon substrates

4.1 Etching process of nanoholes

The e-beam resist used for lithographic process was PMMA 2% dissolved in cholorobenzol or anisole. Two dry etching processes based on mixed fluorine plasma have been optimized in an Oxford Plasmalab 100 ICP180 machine. The first dry etching process involves SF6 + O2 plasma which results in a high etching rate of about 600 nm min−1 and negligible mask erosion at room temperature. This process has been used to etch, e.g. mesas and alignment marks up to 1 µm depth. In the second dry etching process, the CHF3 is used instead of O2. Due to high resist erosion rate of SF6 + CHF3 dry etching, a thick 200 nm layer of PMMA was coated on the substrate using a spin coater. The sample was then heated for 2 min at 180 °C on a hot plate to evaporate the solvent. After the e-beam exposure the resist was developed for 90 s in MIBK/IPA (1:3), 15 s in IPA and blown dry with nitrogen. After the development of the PMMA, the sample was etched. The SF6 + CHF3 recipe results in a low etching rate of about 120 nm min−1. This allows us to achieve highly anisotropic etching of silicon with vertical sidewalls. The anisotropic etching helps prevent significant modifications of the dimensions of the etched features. This is particularly crucial for the fabrication of nanoholes with diameters lying in sub-100 nm range. The selectivity of Si/PMMA = 2:1 is low but sufficient to etch nanoholes with a depth of few tens of nm for the pre-patterned substrates. As a final step the resist was removed and the sample was cleaned.

4.2 Nanoholes fabrication

Before nanoholes fabrication, a design with alignment marks, identification characters and 100 × 100 µm2 boxes were patterned on silicon surface using EBL and the fast dry etching recipe followed by patterning of 80 × 80 µm2 arrays of holes with different periodicities in 100 × 100 µm2 boxes using the slow etching process described above. The etching rate of silicon can also be controlled by changing the ICP power of the etching machine without affecting the sidewall profiles as shown in Fig. 2a.

Figure 2.

(online colour at: www.pss-a.com) (a) Silicon etching rate as a function of ICP power. The etch rate increases linearly with increasing ICP power due to the enhancement of the density of the F* etching species. The corresponding SEM images of 2 µm wide trenches with vertical sidewalls for different ICP powers. (b) Variation of DC bias of the plasma and PMMA erosion rate versus ICP power.

An important parameter to be carefully controlled for the SF6 + CHF3 recipe is the erosion rate of the e-beam resist, which acts as a mask during the etching of nanoholes. The mask erosion has to be kept low for etching of nanoholes. The dependence of plasma DC bias together with PMMA erosion rate on ICP power is shown in Fig. 2b. By changing ICP power from 600 to 800 W, there is a considerable jump in DC bias from 135 to 161 V. However, a further increase in ICP power to 1200 W results in a little increase in the DC bias to value of a 172 V. On the other hand, the dependence of e-beam resist (PMMA) erosion rate on ICP power is rather different which increases only slightly with increasing the ICP power from 600 to 800 W then significantly increases for high ICP powers of 1000 and 1200 W. The ICP power determines the ion density whereas the DC bias determines their energy. At ICP power of 800 W, one can get an appreciable silicon etch rate (Fig. 2a) with a reduced e-beam resist erosion rate. Moreover, perfectly vertical sidewalls are obtained using this ICP power as shown in the inset of Fig. 2a. Therefore, for the fabrication of nanoholes, the ICP power of 800 W was used during the SF6 + CHF3 etching process.

For the optimization of e-beam exposure for the fabrication of nanoholes, a narrow aperture size of 10 µm was selected and the clearance dose dependence of beam acceleration voltages was studied for single pixel dot exposure. The result shown in Fig. 3a indicates that the optimal acceleration voltage for the used resist thickness of 200 nm is around 10 kV for which the smallest clearance dose is needed. For acceleration voltages below 10 kV the penetration depth of electrons is too low to expose the whole resist with practical doses. It is worth to note that in contrary to the work of Duan et al. 44, where a higher sensitivity was obtained by lowering the acceleration energy. In this present work, the higher sensitivity was observed at 10 kV which is due to use of thicker resists (200 nm). Furthermore, we used a narrow aperture size of 10 µm for the electron beam, which results in a reduced beam current and beam spot size for all acceleration voltages. For such a narrow aperture of 10 µm the electron beam with an acceleration voltage below 10 kV does not cause the scission of PMMA long chain molecules through the whole thickness of the resist at lower doses resulting in lower sensitivity. On the other hand, Duan et al., have used thin PMMA resists of about 40 nm with a larger aperture size of 20 µm. Both exposure conditions and PMMA thickness that have been used by Duan et al., are completely different to those used in this work, therefore, one cannot expect comparable results.

Figure 3.

(online colour at: www.pss-a.com) (a) Minimum clearance dose and hole diameter versus electron beam acceleration voltage. (b) Hole diameter as function of exposure dose for a fixed beam acceleration voltage. The inset shows SEM profile of 60 nm hole diameter with an exposure dose of 10 fC per single pixel dot (top left) and with 100 fC per single pixel dot (bottom right) with diameter around 120 nm. The red circle indicates the traces of carbon contaminations.

For a given beam acceleration voltage the diameter of the patterned hole increases linearly with the exposure dose due to beam spreading caused by increased generation of secondary electrons and their scattering through the resist (Fig. 3b). The holes patterned with smaller exposure dose (10 fC) have around 60 nm diameter in size and well defined round shapes whereas those with high exposure dose (100 fC) have traces of carbon contamination (indicated by a red circle in the inset of Fig. 3b) due to the carbonization of PMMA resist 44. Low exposure dose (10 fC) was thus selected for the patterning of nanoholes on silicon.

The control over the hole diameter was achieved by increasing the dose for a single pixel exposure. Figure 3a shows the impact of increasing the exposure dose over the hole diameter for a given e-beam acceleration voltage. The hole diameter increases almost linearly with increasing exposure dose. This can be explained in terms of enhanced forward scattering with increasing exposure dose which results in an enlargement of the hole diameter. The inset of Fig. 3b at a dose of 100 fC shows the emergence of traces of carbon contamination in the fabricated holes for enormously high exposure doses indicated by the red circle. Such a situation occurs when hydrogen and oxygen bonds with carbon are broken and subsequent evaporation of hydrogen and oxygen takes place leaving carbon behind. Hence very high exposure doses have to be avoided for single pixel dot exposure.

Using the optimal e-beam acceleration voltage of 10 kV and an aperture of 10 µm we have successfully fabricated very large arrays of nearly identical nanoholes without defects (e.g. missing holes) as shown in Fig. 4 with periodicities of 1 µm (Fig. 4a), 750 nm (Fig. 4b), 500 nm (Fig. 4c) and 200 nm (Fig. 4d), respectively. It should be noted that similar hole diameters are found for periodicities of 1 µm, 750 nm and 500 nm whereas a slight increase in the diameter is observed for a period of 200 nm. This is possibly arising from the proximity effect. The depth of the holes and the surface roughness of the samples were determined by AFM measurements. As an example, AFM images of patterned holes with 1 µm period are shown in Fig. 4a top view and 3D view. The AFM images showed very low surface roughness values of about 0.1–0.2 nm which is equivalent to the roughness for unpatterned silicon substrates. This shows that the chemical cleaning sequence described above thoroughly removes the contamination associated with the lithographic and etching processes from the silicon surfaces. The diameter and the depth of the patterned holes both ranged between 60 and 70 nm giving an aspect ratio equal to unity.

Figure 4.

(online colour at: www.pss-a.com) (a) SEM image of the fabricated nanoholes with 1 µm period and the corresponding AFM image (3 × 3 µm2) of the patterned silicon surface with a very low surface roughness value of about 0.1–0.2 nm which is equivalent to the roughness for unpatterned silicon substrates. SEM images of nanoholes with periodicities of 750 nm (b), 500 nm (c), and 200 nm (d).

4.3 MBE growth

Before the III–V growth, an in situ surface cleaning process was carried out in the MBE growth chamber using thermal desorption and AH cleaning similar to the above mentioned in situ cleaning process for flat surfaces. It is known that for oxide desorption, high desorption temperatures are necessary. The AH cleaning has been used to remove organic contaminants 17, 18.

Following this approach, the pre-patterned sample was exposed to an AH flux of 3 × 10−7 Torr at 500 °C for 45 min then the sample was annealed at 850 °C for 10 min to desorb the native oxide from the surface and the holes. The removal of oxide was confirmed by hemi-circular streaky RHEED pattern (Fig. 5a) indicating a 2D smooth surface. However, the annealing at 850 °C severely damaged the pattern as evident from the AFM image of the surface (Fig. 5a). Involving the AH cleaning and reducing the annealing temperature to 750 °C then the sample was annealed till emergence of a 2D hemi-circular RHEED pattern (Fig. 5b). The annealing time was 30 min. The AFM image shows that the pattern was preserved after this cleaning sequence (Fig. 5b). No detectable differences in the diameter, depth, and vertical profile of the holes before and after the optimized in situ cleaning are observed. It should be noted that the appearance of 2D hemi-circular RHEED patterns for such pre-patterned sample could mean that the oxide is most probably removed from the silicon surface but no evidence that the oxide is removed from the nanoholes. Intensive investigations are ongoing to prove this hypothesis and obtain a suitable cleaning recipe for nanoholes, preliminary results are discussed below and the full investigation of such study will be presented elsewhere. However, the studied samples in Section 4.2, the in situ cleaning sequence involving AH cleaning and 30 min thermal annealing at 750 °C before the growth were used.

Figure 5.

(online colour at: www.pss-a.com) (a) RHEED pattern of a silicon surface after thermal oxide desorption at 850 °C and the corresponding 5 × 5 µm2 AFM image. (b) RHEED pattern for a cleaned silicon substrate using AH cleaning followed by a 30 min thermal oxide desorption step at 750 °C. The bottom picture is a 3 × 3 µm2 AFM image.

A schematic sequence of the growth on patterned samples is shown in Fig. 6a. The grown samples consist of 2 nm nominal thickness of a GaAs buffer at 600 °C, 2 MLs nominal thickness of an In0.15Ga0.85As QDs layer at 500 °C and 2 nm nominal thickness of a GaAs capping layer at 500 °C. The growth of a GaAs capping layer at a temperature of 500 °C, same as that for QDs growth, was intended to avoid high indium desorption that takes place above 500 °C 31. In the first growth step, we optimized the nucleation of the GaAs buffer layer as nanoislands in the nanoholes. Furthermore, the formation of these nanoislands has taken place highly selectively in the patterned holes spaced by 1 µm as compared to other periods. The next steps are the deposition of 2 MLs for the QD layer at 500 °C and a GaAs cap layer.

Figure 6.

(online colour at: www.pss-a.com) (a) Schematic sequence of the growth on patterned sample. (b) Two-dimensional AFM image (5 × 5 µm2) showing the surfaces morphology after the growth of a complete structure. (c) A 36° tilted SEM image showing the cross-section of the GaAs/In0.15Ga0.85As/GaAs nanostructures localized in the patterned holes.

The AFM profile of the grown sample surface morphology (Fig. 6b) confirms the nucleation of III–V nanostructures in the nanoholes. After the growth of the GaAs capping layer additional nanocrystallites are formed between the holes causing high surface roughness of about 2–3 nm which is obtained from the AFM image. We believe that these additional nanocrystallites are formed during the deposition of the GaAs capping layer at 500 °C due to the smaller migration length of gallium ad-atoms at such low growth temperatures. It should be noted that the growth of the QDs was not uniform. This could be related to the slight variation in the diameter of the nanoholes, which causes the variation of the size of the nucleated nanostructures during the MBE growth. Furthermore, the fluctuation in beam fluxes during the growth could also contribute to the non-uniformity of the QDs. Moreover, about 60% of the holes are filled, this could be explained by the surface degradation after the processing steps, and the local surface inhomogeneities would affect the diffusion of ad-atoms to certain crystal directions which would result in non-uniform distribution of nucleation sites during the growth.

Focused ion beam (FIB) was used to verify the nucleation of III–V materials in the nanoholes. Figure 6c displays a 36° tilted SEM image showing the cross-section of the GaAs/In0.15Ga0.85As/GaAs nanostructures localized in the patterned holes. The cross-sectional view exhibits a good interface between QDs and silicon in the nanohole. We propose that the selective nucleation of the III–V nanostructures inside the holes with 1 µm spacing after different growth steps is due to the lower chemical potential inside the etched holes than for the plane surface 45. This gradient of chemical potential provides the driving force for the group III–V ad-atoms to diffuse to the holes and preferentially nucleate there 45, 46. Growth of GaAs/InAs/GaAs nanostructures on pre-patterned silicon masked with SiO2 has already been demonstrated in ref. 26 with thick nominal depositions. However, in our work we have demonstrated for the first time 47 the site controlled growth of GaAs/InGaAs/GaAs nanostructures with very low nominal deposition thicknesses directly on pre-patterned silicon without the use of a SiO2 mask.

5 Optimized growth: Towards full control of III–V nucleation in pre-patterned nanoholes

The hemicircular streaky RHEED patterns obtained using the standard pre-growth cleaning procedure discussed above indicate clean silicon surfaces. However, as clearly seen from Fig. 6b, there are considerably amount of the nanoholes not filled by the III–V material. This could be due to the presence of residual oxide in the holes. It was found in early studies by Sun et al. 48 that thermal oxide desorption takes place through void formation on surfaces. Therefore, if these voids are large enough or merged to each other, the streaky RHEED patterns will always appear because the biggest area is oxide free. The native oxide in the holes and growth temperature play a crucial role in selective area growth. In order to obtain a full control over the nucleation in the nanoholes it is important to obtain a suitable in situ cleaning method in the MBE chamber for full desorption of native oxide from the hole surfaces.

Oxygen and carbon are unavoidable contaminations after wet chemical treatment and therefore in this section, we briefly present preliminary results towards the full nucleation control of III–V materials in the nanoholes using in situ cleaning.

Before loading the silicon substrates into the MBE chamber, the samples were rinsed using a 5% HF solution for 20 s to remove the native oxide from the silicon surface. Subsequently, the samples are loaded into the buffer chamber for 10 min for degassing and afterwards loaded into the growth chamber. The patterned substrate temperature was then increased gradually to 800 °C with a ramping rate of 30 °C min−1. At 800 °C the sample was annealed without AH cleaning for 5 min to desorb the native oxides. After this step the pre-patterned samples were immediately covered with arsenic flux and cooled down to the growth temperature of the III–V material with a ramp of 30 °C min−1. It should be noted that the nanoholes are preserved after this process (the AFM images are not shown here). A nominal 4 MLs thick GaAs layer was deposited at a substrate temperature of 600 °C. AFM images in Fig. 7 show that the nucleation of the GaAs takes place in all nanoholes with approximately 100% of the holes are filled. This is a strong indication that the oxide is removed from all nanoholes. No additional III–V nanostructures are formed between the holes which could be related to the low ramping rate for substrate temperature. It should be noted that using high ramping rate of 75 °C min−1 results in III–V material nucleation between the holes.

Figure 7.

(online colour at: www.pss-a.com) AFM images (5 × 5 µm2) of the optimized GaAs grown in pre-patterned silicon substrate on a 1 µm period.

6 Conclusions and outlook

In conclusion, we have briefly reviewed our recent work on direct epitaxial growth on pre-patterned and on flat silicon substrates. The experimental approach is based on the use of a minimum III–V amount to allow a full silicon processing. EBL and dry etching processes were optimized to fabricate sub-100 nm holes with controlled size, shape, and periodicity. The pre-patterned silicon substrates underwent thorough ex situ chemical and in situ cleaning sequences before the growth. The site-controlled MBE growth of GaAs/InGaAs/GaAs QDs in the patterned holes with 1 µm period was achieved. We have also shown an optimized in situ cleaning process that leads to the nucleation of GaAs nanostructures in all patterned nanoholes. Besides the ability to control the III–V material nucleation in the hole, the nanostructures are not homogeneous in shape and size.

The next steps are to grow the full structure with InAs QDs and to optimize the nucleation of the III–V material only in the holes and also control the homogeneity of the grown III–V structures. At the present stage, the achieved results show that more control on in situ cleaning and some growth parameters are required in order to grow an optical active material fully embedded in a silicon matrix.

Acknowledgements

We acknowledge T. Pfau, A. Gushterov for their help in the experiment. F. Schnabel, K Fuchs and T. Kusserow for technical support. This work was supported by BMBF (MONALISA).