Suppression of threshold voltage shifts in organic thin-film transistors with bilayer gate dielectrics

Authors

  • Kenjiro Fukuda,

    Corresponding author
    1. Research Center for Organic Electronics, Yamagata University, Yamagata, Japan
    • Graduate School of Science and Engineering, Yamagata University, Yamagata, Japan
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  • Tatsuya Suzuki,

    1. Graduate School of Science and Engineering, Yamagata University, Yamagata, Japan
    2. Research Center for Organic Electronics, Yamagata University, Yamagata, Japan
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  • Takuma Kobayashi,

    1. Graduate School of Science and Engineering, Yamagata University, Yamagata, Japan
    2. Research Center for Organic Electronics, Yamagata University, Yamagata, Japan
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  • Daisuke Kumaki,

    1. Graduate School of Science and Engineering, Yamagata University, Yamagata, Japan
    2. Research Center for Organic Electronics, Yamagata University, Yamagata, Japan
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  • Shizuo Tokito

    1. Graduate School of Science and Engineering, Yamagata University, Yamagata, Japan
    2. Research Center for Organic Electronics, Yamagata University, Yamagata, Japan
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Abstract

Bias-stress effects in pentacene thin-film transistors (TFT) with parylene-C and amorphous fluoropolymers as bilayer gate dielectric layers are systematically investigated. The threshold voltage shift can be controlled systematically by changing the thicknesses of the two dielectric layers. The shift is proportional to a proportion of a potential drop between parylene-C layer to the total potential drop between gate and source electrodes, and the threshold voltage shift can be fitted to a sum of the exponential functions. Devices with optimized thicknesses of the bilayer gate dielectrics show remarkable stability under continuous gate-bias voltage stress over long periods, demonstrating shifts in threshold voltage of less than 0.5 V after 48 h. pssa201228811-gra-0001

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