### Abstract

- Top of page
- Abstract
- 1 Introduction
- 2 Experimental
- 3 Results and discussion
- 4 Conclusions
- 5 Supporting information
- Acknowledgements
- References

Bias-stress effects in pentacene thin-film transistors (TFT) with parylene-C and amorphous fluoropolymers as bilayer gate dielectric layers are systematically investigated. The threshold voltage shift can be controlled systematically by changing the thicknesses of the two dielectric layers. The shift is proportional to a proportion of a potential drop between parylene-C layer to the total potential drop between gate and source electrodes, and the threshold voltage shift can be fitted to a sum of the exponential functions. Devices with optimized thicknesses of the bilayer gate dielectrics show remarkable stability under continuous gate-bias voltage stress over long periods, demonstrating shifts in threshold voltage of less than 0.5 V after 48 h.