Bias-stress effects in pentacene thin-film transistors (TFT) with parylene-C and amorphous fluoropolymers as bilayer gate dielectric layers are systematically investigated. The threshold voltage shift can be controlled systematically by changing the thicknesses of the two dielectric layers. The shift is proportional to a proportion of a potential drop between parylene-C layer to the total potential drop between gate and source electrodes, and the threshold voltage shift can be fitted to a sum of the exponential functions. Devices with optimized thicknesses of the bilayer gate dielectrics show remarkable stability under continuous gate-bias voltage stress over long periods, demonstrating shifts in threshold voltage of less than 0.5 V after 48 h.
Organic thin-film transistor (TFT) devices have attracted significant attention in research and development because they can be processed on plastic substrates with printable fabrication techniques at low temperature. These features allow for large-area electronic applications such as flexible displays , RFID tags , memory devices [3, 4], and flexible sensors . While recent efforts have achieved significant progress in improving the electrical characteristics of organic TFT devices [6, 7], operational stability remains a major issue to be resolved before organic TFT devices are commercialized for practical applications. In some TFT devices, excess charges induced by the gate electric field are believed to fall into trap states over time with continuous device operation, a behavior known as the bias-stress effect, which is an obstacle to the long-term operational stability for organic TFT devices, as well as those based on a-Si:H, poly-Si, and metal-oxide semiconductor materials [8-12]. Bias-stress effects are largely attributed to the trapping of carriers from a gate bias-induced conduction channel into localized electronic states [13-16]. These trap states may be located within the semiconductor layer, at a semiconductor/dielectric interface, or in the gate dielectric layer. The longer the gate bias is applied, the more carriers are trapped, and hence the larger the shift in threshold voltage that is observed. The trapped carriers generally do not contribute to source/drain current, which decreases over time at a given gate–source voltage. For p-type organic TFT devices, the threshold voltage generally changes in a negative direction for negative gate–source voltages [17, 18].
There are a number of previous studies relating to the suppression of the bias-stress effects. There are two major approaches for suppressing the bias-stress effect. One is to reduce trap sites in the semiconductor layer such as by physically eliminating them with thermal annealing , and the other is to improve the semiconductor/dielectric interface, e.g., by reducing roughness at the interface , forming self-assembled monolayer modification on dielectric surfaces , or using hydroxyl-free amorphous fluoropolymers as gate dielectric layers [22-24].
Recently, we reported on organic TFT devices with polychloro-p-xylylene (parylene-C) gate dielectrics that exhibited positive threshold voltage shifts under a negative continuous gate–source voltage with no hysteresis in transfer characteristics , whereby the crystallinity of parylene-C dielectric layers affected the reverse bias-stress effect. From these results we found that the bias-stress effects can be influenced not only by trap sites within a semiconductor layer or at semiconductor/dielectric interface, but also by those in dielectric layer.
In this study, we succeeded in suppressing threshold voltage shifts under continuously applied bias voltages with bilayer gate dielectrics consisting of parylene-C and an amorphous fluoropolymer. The positive voltage shift caused by the parylene-C dielectrics was able to compensate the negative voltage shift caused by the fluoropolymer dielectrics. We systematically varied the thicknesses of two dielectric layers and evaluated the relationship between their thicknesses and the threshold voltage shift under the continuous negative gate–source voltage, and it was found that changing the thickness ratio of two dielectric layers could control the threshold voltage shift.
2.1 Device fabrication and measurements
Polycrystalline pentacene TFT devices with parylene-C/fluoropolymer as bilayer gate dielectrics were manufactured by employing a vacuum evaporation process. An illustration of the bottom-gate, top-contact TFT device with parylene-C/fluoropolymer as bilayer gate dielectrics is shown in Fig. 1. First, aluminum was evaporated onto a glass substrate to form a 50-nm thick gate electrode. A parylene-C (KISCO, dix-C) layer was then formed by chemical vapor deposition. Dichloro-p-xylylene powders were sublimed at 135 °C in a sublimation chamber and then were converted to monomer gas at 650 °C in a pyrolysis chamber. The monomers were deposited onto the substrates and polymerized to form polymer films of poly-p-xylylene in a deposition chamber with a base pressure of less than 35 mTorr. After deposition of the parylene-C layer, the substrates were annealed at 150 °C for 1 h in a nitrogen atmosphere to change the crystallinity of the parylene-C. Then, a secondary dielectric fluoropolymer layer was formed on the parylene-C layer. Solutions of fluoropolymer (DuPontTM, Teflon® AF 1600) in Fluorinert (3MTM, FC-43) were spin coated onto the parylene-C surface and were dried at 150 °C for 1 h. The thickness of the parylene-C layer (dP) was easily controlled by changing the mass of the dimers, and the thickness of the fluoropolymer layer (dF) was controlled by adjusting solution concentrations and rotation speeds. A pentacene layer was deposited to form a 75-nm thick organic semiconductor channel on the dielectric layers. Finally, gold was deposited to form 50-nm thick source/drain electrodes. The channel width (W) and the channel length (L) of the fabricated TFT devices were 1000 and 65 µm, respectively. After the fabrication process, the devices were postannealed at 100 °C for 1 h, in order to eliminate adsorbed molecules, such as oxygen or water, which cause trap sites in the semiconductor layers [19, 26].
A total capacitance of TFT devices with bilayer dielectrics is described as two capacitances in series:
where CTotal is the total capacitance of bilayer dielectrics, CP is the capacitance of the parylene-C layer, and CF is the capacitance of the fluoropolymer layer. The relative permittivity of the parylene-C layer is 3.1 and that of fluoropolymer layer is 1.9. We prepared several such TFT devices with different thicknesses of parylene-C and fluoropolymer layers (Table 1). The fabricated TFT devices had nearly the same capacitances, within a range of 5.21 to 6.00 nF cm−2, by controlling the thicknesses of the two dielectric layers.
|dP (nm)||dF (nm)||CTotal (nF cm−2)||X = CTotal/CP||µ (cm2 V−1 s−1)||VTH (V)|
In order to systematically estimate how each dielectric layer affects the bias-stress effects, we considered the ratio X of the voltage drop between the parylene-C layer to a total voltage drop between gate and source electrodes:
where VP is the voltage drop between the parylene-C layer and VGS is the gate–source voltage. X was obtained from CTotal and CP. For all devices in this study, the changes of the threshold voltage were observed under the same constant bias voltages (VGS = –40 V, VDS = 0 V). A ratio of X = 1 means the TFT has only parylene-C dielectric layers, and X = 0 means the TFT have only fluoropolymer dielectric layers. A summary of the dielectric layer thicknesses and performance for each of the TFT devices before inducing a bias voltage is shown in Table 1.
3 Results and discussion
3.1 Relationship between the bias-stress effect and bilayer dielectric thicknesses
We estimated the change in threshold voltage (ΔVTH) as the devices were stressed with constant bias voltages (VGS = –40 V, VDS = 0 V) from their transfer characteristics. Figure 2 shows the changes in transfer characteristics before and after stressing the devices for 3600 s, for TFT devices with different X values ranging from 0 to 1. When a continuous VGS of –40 V was applied to the device with X = 0 for 3600 s, the threshold voltage shifted slightly in the negative direction, from –24.1 to –25.1 V (Fig. 2). However, when a DC gate–source bias voltage of –40 V was continuously applied to the device with X = 1 for 3600 s, the threshold voltage shifted in a positive direction from –23.6 to –19.4 V (Fig. 2). Further, when the same bias voltage was applied to a device with X = 0.34 for 3600 s, almost no change was observed in threshold voltage or other key electrical parameters such as on/off ratio and field-effect mobility (Fig. 2).
Figure 3 shows the change in threshold voltage measured over an extended period of time at VGS = –40 V and VDS = 0 V. The measured ΔVTH for the devices with X < 0.34 decreased monotonically as the stress time increased. However, ΔVTH for the devices with X > 0.34 increased monotonically as the stress time increased. Figure 3 shows ΔVTH after 1 h as a function of X. These plots clearly show a linearly proportional change in ΔVTH vs. X, with the following linear curve fit:
This result indicates that the opposite bias-stress tendencies of these two dielectrics cancel each other by stacking the two layers. The bias-stress effect can then be controlled systematically by changing the thicknesses of these two dielectric layers. This proportional relationship between ΔVTH and X was observed not only for the top-contact TFT devices with evaporated gold source/drain electrodes but also for bottom-contact TFT devices with printed silver source/drain electrodes (see Figs. S3–S5 of Supporting Information, online at: www.pss-a.com). As a result, it was concluded that suppression of bias-stress effects is independent of either the device structure or electrode material. Hwang et al.  reported that organic TFT devices with bilayer dielectrics with Al2O3 and CYTOP® show long-term operational stability. However, the study did not look at changes in the dielectric thickness. We systematically investigated the relation between the capacitances of the two dielectrics, and threshold-voltage shift under constant bias voltages, which could be described by Eq. (3).
3.2 Surface observation of dielectrics and semiconducting layers
The surface morphology of each device was evaluated using atomic force microscopy (AFM). Representative AFM images for each dielectric surface and pentacene layer are shown in Fig. 4. The root-mean-square average roughness (Rq) of the dielectric surface increased from 0.25 to 3.72 nm as the X value increased from 0 to 1 (Fig. 4). The fluoropolymer layer reduced the surface roughness of parylene-C layers because they possess a significantly smoother surface than that of parylene-C, whereby surface roughness decreased as the thickness of fluoropolymer layer increased. However, there is almost no variation in pentacene layer grain sizes (Fig. 4). The bias-stress effects are not consistent with either the dielectric layer surface roughness and semiconductor layer grain size. For example, although bilayer dielectrics with ratio X = 0.21 and 0.48 have almost the same surface roughness of about 0.7 nm and same pentacene layer grain sizes, the device with the former dielectric layer structure demonstrated a positive threshold voltage shift while the device with the latter dielectric layer structure demonstrated the negative threshold voltage shift, as shown in Fig. 3. The only difference between those two bilayer dielectric structures was the thicknesses of the parylene-C and the fluoropolymer layers. Although it was not in direct contact with the semiconductor material, the bottom parylene-C dielectric layer also influenced the threshold-voltage shift under continuous bias voltages. These results are consistent with the results reported by Ng et al. .
Additionally, the reverse bias-stress effect did not occur for the TFT devices with parylene-N dielectric layers, which have a similar chemical structure to parylene-C but have no chlorine atom or no dipole in a single repeating unit (see Figs. S6–S8, Supporting Information). These results indirectly indicate that dielectric layer materials could be the cause the bias-stress effects.
3.3 Long-term operational stability
In order to observe a long-term operational stability under the continuous bias voltages on the TFT device with bilayer dielectrics, we observed the threshold voltage shift of the device with bilayer dielectrics of X = 0.34 under continuous voltages of VGS = –40 V, VDS = 0 V for 48 h. Figure 5 shows ΔVTH as a function of stress time. A slight positive threshold voltage shift was observed for the first 30 min, after which a negative threshold shift was seen. The ΔVTH after applying voltage for 48 h was only –0.44 V without any changes in other key electrical parameters such as on/off ratio and field-effect mobility (Fig. 5), which demonstrates the remarkable stability against the bias stress of TFT devices with bilayer dielectrics.
The time dependence of the bias-stress-induced threshold voltage shift under a constant VGS and VDS is typically described by a stretched exponential function ,
where VTH(0) is the threshold voltage in the unbiased state, VTH(∞) is the threshold voltage when equilibrium has been reached at t → ∞, τ is the time constant, and β is the stretching parameter (0 < β ≤ 1). In this study, the two dielectrics cause opposite threshold voltage shifts under continuous bias voltages, whereby we consider a sum of two stretched exponential functions with different parameters to describe the bias-stress effect for the TFT devices with bilayer dielectrics:
where . We have fitted the time dependence of the measured threshold voltage shift to Eq. (5). The fit parameters are summarized in Table 2 and the fitted curve is shown in Fig. 5 as a black solid line. The obtained fitting curve agrees with the experimental result, which indicates the threshold voltage shift under bias voltages of the TFT devices where both positive and negative factors can be properly described by the expanded stretched exponential function.
|A1 (V)||β1||τ1 (s)||A2 (V)||β2||τ2 (s)|
|0.28||0.70||3.6 × 102||–2.65||0.42||2.6 × 106|
It is interesting to compare the two time constants obtained: τ1, which is the time constant for the positive threshold voltage shift and τ2, which is that for the negative threshold voltage shifts. Here, τ1 is 10 000 times smaller than τ2. This large difference reflects the slight negative shift following the initial positive shift for 30 min as shown in Fig. 5. It is known that the TFT devices with fluoropolymer gate dielectrics show stability against the bias-stress effect because the gate dielectric layers have no hydroxyl groups [22, 23]. These TFT devices have large time constants in Eq. (4) . Conversely, positive bias shifts caused by dipoles in a dielectric layer generally have quite small time constants, and thereby a large hysteresis is observed in transfer characteristics [30, 31]. The time constants obtained from the fits in this study were consistent with those results in the previous studies.
Bias-stress effects in pentacene TFT devices with parylene-C/fluoropolymer bilayer gate dielectrics were investigated. It was found that the threshold-voltage shifts bore a proportionate relationship to the voltage drop between parylene-C layers. TFT devices using two dielectric layers with optimized thicknesses showed remarkable stability under continuous bias-stress voltages applied for an extended period of time. Furthermore, the threshold-voltage shift could be fitted to a sum of stretched exponential functions. These results indicate that bilayer dielectrics that have the same time constants and opposite threshold-voltage shift directions can suppress bias-stress effects almost completely and provide long-term operational stability.
5 Supporting information
Supporting information is available online from Wiley Online Library at: www.pss-a.com, or from the author.
The authors thank the Japan Science and Technology Agency (JST) for their support of this work.