The fabrication technology of extra-functionality CMOS devices involves process steps which lead to high damage in the silicon lattice. Amorphizing implants and simultaneous reduction of thermal budgets to gain better control of the formation of ultra-shallow junctions render the presence of extended defects in active regions unavoidable. In particular, dislocation loops (DLs) have proven to be stable under thermal treatment. To better understand the electrical properties of DLs and their impact on the leakage current we developed an analytical tool to extract defect parameters from measured Deep Level Transient Spectroscopy (DLTS) signals and capacitance transients. Commercial process and device simulators are used to test the plausibility of applied defect models and the basic assumptions about the electrical activity of DLs.
Simulation of DLTS peak broadening caused by the broadening of a defect level distribution in the band gap of silicon.