Electrical measurements on copper phthalocyanine (CuPc)-based organic field effect transistors using SiO2 dielectric revealed hysteresis and threshold voltage instability to be due to the combined effect of both hole- and electron-trapping mechanisms, with the electron-trap density being higher than hole-trap density. Hysteresis was found to increase further after modifying the SiO2 surface with octadecyltrichlorosilane (OTS) while it reduced drastically after polystyrene (PS) modification. Individual contribution of holes and electrons to hysteresis and the cause of increased/reduced trapping of the same for interface modified devices were identified. The increase in hysteresis with OTS-modified devices was attributed to increase in hole-trap density arising from a larger grain-boundary density of CuPc films. Minimum grain-boundary density and efficient removal of trap centers at dielectric/semiconductor interface using PS modification resulted in minimum hysteresis. Comparison of hole- and electron-trap densities estimated for measurements under different ambient conditions, like high humidity conditions and oxygen flow, showed that hole-trap density increased with increase in humidity. Under oxygen flow, hysteresis, and hole-trap density were found to reduce considerably, which could be attributed to creation of excess holes that readily fill hole traps, thereby resulting in increased mobile carrier concentrations.