Two-dimensional numerical analysis of nanoscale junctionless and conventional Double Gate MOSFETs including the effect of interfacial traps

Authors


Abstract

This paper deals with the immunity behavior of the junctionless DG MOSFET device against the hot carrier degradation effect. The junctionless device is highly privileged because of its easy fabrication procedure, homogeneity along the channel axe in addition to its promising electrical characteristics compared to the conventional DG MOSFET with PN junction at the source and the drain sides. As a result, we demonstrate that junctionless DG MOSFET can be a viable option to enhance the immunity performances of nanoscale CMOS-based devices technology for nanoelectronics digital applications (© 2012 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

Ancillary