Gate-engineering-based approach to improve the nanoscale DG MOSFET behavior against interfacial trap effects



In this paper, we propose a numerical investigation based framework for the analysis of a new MOSFET device, which is motivated by gate engineering and junctionless channel paradigms. The device immunity against the hot carrier effect is evaluated by comparing the obtained relative degradation in the threshold voltage to its counterparts in the conventional and single junctionless double gate MOSFETs. It is found that our proposed design can efficiently deal with the hot carrier and short channel effects. As a result, the gate-engineering-based design for junctionless channel structures appears to be of potential importance in the development of nanoscale devices dedicated to digital circuit applications. (© 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)