Source/drain induced defects in advanced MOSFETs: what device electrical characterization tells



A wealth of convergent results are indicating that point defects originating from the processing of source/drain (S/D) regions are strongly involved in many parameters that rule the operation mechanisms and ultimately the performance of transistors. One example of such effect is the mobility degradation which is observed at short gate length in most, if not all, technologies. Defects can also been traced by their implication in leakage currents. Their dynamics has been found as well to be involved in the activation/deactivation processes and the final series resistance of S/D regions, enlightening the role of additional interfaces that are being introduced with thin film SOI and nanowire technologies. These complex effects, which are becoming 3D in present technologies, are very difficult to characterize by means of structural characterization. On the other hand, simulation based predictions have strongly improved. However, due to the complex processes involved, they still require the adjustment of a large number of parameters, which can usually be validated in model configurations only. In this paper we will review and complement some of our recent results obtained from electrical characterization, for a variety of advanced MOS transistor architectures, with focus on the analysis of the parameters which can be influenced by the presence of defects. It is shown that in-depth electrical characterization can provide strong experimental indications about point defects lateral distribution, with the advantage of probing the real device. (© 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)