Special Issue Paper
FPGA implementation of AES algorithm for high throughput using folded parallel architecture
Article first published online: 12 OCT 2012
Copyright © 2012 John Wiley & Sons, Ltd.
Security and Communication Networks
How to Cite
Rahimunnisa, K., Karthigaikumar, P., Rasheed, S., Jayakumar, J. and SureshKumar, S. (2012), FPGA implementation of AES algorithm for high throughput using folded parallel architecture. Security Comm. Networks. doi: 10.1002/sec.651
- Article first published online: 12 OCT 2012
- Manuscript Accepted: 25 AUG 2012
- Manuscript Revised: 11 JUL 2012
- Manuscript Received: 23 JAN 2012
- Field Programmable Gate Array (FPGA);
This paper presents high throughput architecture for the hardware implementation of Advanced Encryption Standard algorithm. Advanced Encryption Standard is the industry standard crypto algorithm for encryption and is used for protecting secret information. This work is mainly targeted for low-cost embedded applications. This paper introduces parallel operation in the folded architecture to obtain better throughput. The design is coded in Very High-speed Integrated Circuit Hardware Description Language. Timing simulation is performed to verify the functionality of the designed circuit. The proposed structure is implemented in Virtex-6 XC6VLX75T FPGA device. This work gives a high throughput of 37.1 Gb/s with a maximum frequency of 505.5 MHz, which is 20% higher than the maximum throughput reported in the literature. Copyright © 2012 John Wiley & Sons, Ltd.