Special Issue Paper
FPGA implementation of AES algorithm for high throughput using folded parallel architecture
Article first published online: 12 OCT 2012
Copyright © 2012 John Wiley & Sons, Ltd.
Security and Communication Networks
How to Cite
Rahimunnisa, K., Karthigaikumar, P., Rasheed, S., Jayakumar, J. and SureshKumar, S. (2012), FPGA implementation of AES algorithm for high throughput using folded parallel architecture. Security Comm. Networks. doi: 10.1002/sec.651
- Article first published online: 12 OCT 2012
- Manuscript Accepted: 25 AUG 2012
- Manuscript Revised: 11 JUL 2012
- Manuscript Received: 23 JAN 2012
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