Special Issue Paper
FPGA implementation of AES algorithm for high throughput using folded parallel architecture
Version of Record online: 12 OCT 2012
Copyright © 2012 John Wiley & Sons, Ltd.
Security and Communication Networks
Volume 7, Issue 11, pages 2225–2236, November 2014
How to Cite
2014), FPGA implementation of AES algorithm for high throughput using folded parallel architecture, Security Comm. Networks, 7, 2225–2236, doi: 10.1002/sec.651, , , , and (
- Issue online: 24 OCT 2014
- Version of Record online: 12 OCT 2012
- Manuscript Accepted: 25 AUG 2012
- Manuscript Revised: 11 JUL 2012
- Manuscript Received: 23 JAN 2012
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