V.S. is permanently located at the MPI in Halle but worked as a visiting scientist at the IBM Zurich Research Laboratory, where this work was carried out.
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Communication
Realization of a Silicon Nanowire Vertical Surround-Gate Field-Effect Transistor
Article first published online: 7 NOV 2005
DOI: 10.1002/smll.200500181
Copyright © 2006 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim
Additional Information
How to Cite
Schmidt, V., Riel, H., Senz, S., Karg, S., Riess, W. and Gösele, U. (2006), Realization of a Silicon Nanowire Vertical Surround-Gate Field-Effect Transistor. Small, 2: 85–88. doi: 10.1002/smll.200500181
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V.S. is permanently located at the MPI in Halle but worked as a visiting scientist at the IBM Zurich Research Laboratory, where this work was carried out.
Publication History
- Issue published online: 5 DEC 2005
- Article first published online: 7 NOV 2005
- Manuscript Revised: 1 AUG 2005
- Manuscript Received: 1 JUN 2005
- Abstract
- Article
- References
- Cited By
Keywords:
- chemical vapor deposition;
- field-effect transistors;
- nanowires;
- silicon
A generic process for fabricating vertical surround-gate field-effect transistors (FETs) from epitaxially grown silicon nanowires is presented. The process is demonstrated using n-type Si nanowires grown on a p-type substrate in ultrahigh vacuum using a Au catalyst. The process consists of various deposition and etching steps; no chemical or mechanical polishing is required. Individual as well as arrays of vertical surround-gate FETs can be fabricated.