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Silicon Nanowire Charge-Trap Memory Incorporating Self-Assembled Iron Oxide Quantum Dots

Authors

  • Ruo-Gu Huang,

    1. Division of Chemistry and Chemical Engineering, California Institute of Technology, 1200 E. California Blvd, MC 127-72, Pasadena, CA 91125, USA, FAX: (+1) 626-395-2355
    2. Micron Technology, Inc., 3060 N. First Street, San Jose, CA 95134, USA
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  • James R. Heath

    Corresponding author
    1. Division of Chemistry and Chemical Engineering, California Institute of Technology, 1200 E. California Blvd, MC 127-72, Pasadena, CA 91125, USA, FAX: (+1) 626-395-2355
    • Division of Chemistry and Chemical Engineering, California Institute of Technology, 1200 E. California Blvd, MC 127-72, Pasadena, CA 91125, USA, FAX: (+1) 626-395-2355.
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Abstract

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Charge-trap non-volatile memory devices based upon the precise integration of quantum dot storage elements with silicon nanowire field-effect transistors are described. Template-assisted assembly yields an ordered array of FeO QDs within the trenches that separate highly aligned SiNWs, and injected charges are reversibly stored via Fowler–Nordheim tunneling into the QDs. Stored charges shift the transistor threshold voltages, providing the basis for a memory device. Quantum dot size is found to strongly influence memory performance metrics.

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