A preliminary version of this work appeared in the Proceedings of the IEEE Workshop on Signal Processing Systems (SiPS 2009).
Extended conference paper
Loop scheduling with memory access reduction subject to register constraints for DSP applications†
Version of Record online: 6 FEB 2013
Copyright © 2013 John Wiley & Sons, Ltd.
Software: Practice and Experience
Volume 44, Issue 8, pages 999–1026, August 2014
How to Cite
Wang, Y., Jia, Z., Chen, R., Wang, M., Liu, D. and Shao, Z. (2014), Loop scheduling with memory access reduction subject to register constraints for DSP applications. Softw: Pract. Exper., 44: 999–1026. doi: 10.1002/spe.2186
- Issue online: 9 JUL 2014
- Version of Record online: 6 FEB 2013
- Manuscript Accepted: 10 JAN 2013
- Manuscript Revised: 8 JAN 2013
- Manuscript Received: 14 MAY 2012
- Hong Kong Special Administrative Region, China. Grant Number: ITS/082/10
- Germany/Hong Kong Joint Research Scheme. Grant Number: G_HK021/12
- National Natural Science Foundation of China. Grant Number: 61272103
- Hong Kong Polytechnic University. Grant Numbers: 4-ZZD7, G-YK24, G-YM10
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