A Gate-Current Model for Advanced MOSFET Technologies Implemented into HiSIM2

Authors

  • Ryosuke Inagaki,

    Non-member, Corresponding author
    1. Graduate School of IPS, Waseda University, 2-7 Hibikino Wakamatsu-ku, Kitakyushu-shi, Fukuoka 808-0135 and Semiconductor Technology Academic Research Center, 3-17-2 Shin-Yokohama, Kouhoku-ku, Yokohama-shi, Kanagawa 222-0033, Japan
    • Graduate School of IPS, Waseda University, 2-7 Hibikino Wakamatsu-ku, Kitakyushu-shi, Fukuoka 808-0135 and Semiconductor Technology Academic Research Center, 3-17-2 Shin-Yokohama, Kouhoku-ku, Yokohama-shi, Kanagawa 222-0033, Japan
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  • Norio Sadachika,

    Non-member
    1. Advanced Science of Matter, Hiroshima University, 1-3-1 Kagamiyama, Higashi Hiroshima-shi, Hiroshima 739-8530, Japan
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  • Dondee Navarro,

    Non-member
    1. Silvaco Japan Co., Ltd., 549-2 Shinanou-cho, Totsuka-ku, Yokohama-shi, kanagawa 244-0801, Japan
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  • Mitiko Miura-Mattausch,

    Non-member
    1. Advanced Science of Matter, Hiroshima University, 1-3-1 Kagamiyama, Higashi Hiroshima-shi, Hiroshima 739-8530, Japan
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  • Yasuaki Inoue

    Member
    1. Graduate School of IPS, Waseda University, 2-7 Hibikino Wakamatsu-ku, Kitakyushu-shi, Fukuoka 808-0135, Japan
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Abstract

A gate leakage current model for advanced MOSFETs has been developed and implemented into the Hiroshima-university STARC IGFET Model (HiSIM), the first complete surface-potential-based model. The model consists of four tunneling mechanisms, the gate to channel/bulk/source/drain, and requires totally 15 model parameters covering all bias conditions. Simulation results reproduce measurement for any device size and temperature without binning. Validity of the model has been tested with circuits that are sensitive to the change of stored charge due to tunneling current. Copyright © 2007 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.

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