Simplified 20-µm pitch vertical interconnection process for 3D chip stacking

Authors

  • Katsuyuki Sakuma,

    Non-member, Corresponding author
    1. Department of Science and Engineering, Waseda University, Okubo 3-4-1, Shinjuku, Tokyo 169-8855, Japan
    2. IBM Tokyo Research Laboratory, 1623-14 Shimo-tsuruma, Yamato, Kanagawa 242-8502, Japan
    • Department of Science and Engineering, Waseda University, Okubo 3-4-1, Shinjuku, Tokyo 169-8855, Japan
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  • Noriyasu Nagai,

    Non-member
    1. Department of Science and Engineering, Waseda University, Okubo 3-4-1, Shinjuku, Tokyo 169-8855, Japan
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  • Mikiko Saito,

    Non-member
    1. Department of Science and Engineering, Waseda University, Okubo 3-4-1, Shinjuku, Tokyo 169-8855, Japan
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  • Jun Mizuno,

    Member
    1. Department of Science and Engineering, Waseda University, Okubo 3-4-1, Shinjuku, Tokyo 169-8855, Japan
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  • Shuichi Shoji

    Member
    1. Department of Science and Engineering, Waseda University, Okubo 3-4-1, Shinjuku, Tokyo 169-8855, Japan
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Abstract

This paper describes a simplified vertical interconnection process for three-dimensional (3D) chip stacking. The unique feature of this new process is that the conductive filling material in the through-silicon-vias (TSVs), the microbumps, and the interconnection materials are all fabricated in one processing stage. All of the steps can be performed with the same piece of equipment. Prototype chips with 20-µm-pitch vertical interconnections have been demonstrated successfully. By using this technique, 75-µm deep high-aspect-ratio vias can be completely filled without voids using Ni electroplating and uniform 20-µm-pitch microbumps that are 4-µm tall have been fabricated using Sn-Cu electroplating. Copyright © 2009 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.

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