Special Issue on Frontier in Sensors and Micromachines / Special Issue Paper
Simplified 20-µm pitch vertical interconnection process for 3D chip stacking
Version of Record online: 22 APR 2009
Copyright © 2009 Institute of Electrical Engineers of Japan
IEEJ Transactions on Electrical and Electronic Engineering
Special Issue: Special Issue on Frontier in Sensors and Micromachines
Volume 4, Issue 3, pages 339–344, May 2009
How to Cite
Sakuma, K., Nagai, N., Saito, M., Mizuno, J. and Shoji, S. (2009), Simplified 20-µm pitch vertical interconnection process for 3D chip stacking. IEEJ Trans Elec Electron Eng, 4: 339–344. doi: 10.1002/tee.20415
- Issue online: 22 APR 2009
- Version of Record online: 22 APR 2009
- Manuscript Revised: 25 NOV 2008
- Manuscript Received: 25 AUG 2008
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