Analysis of Snapback Phenomena in VDMOS Transistor having the High Second Breakdown Current: A High ESD Mechanism Analysis

Authors

  • Kenichi Hatasako,

    Member, Corresponding author
    1. Mixed Signal Device Technology Department, Production and Technology Unit, Renesas Technology Corporation, 4-1 Mizuhara, Itami, Hyogo, 664-0005, Japan
    • Mixed Signal Device Technology Department, Production and Technology Unit, Renesas Technology Corporation, 4-1 Mizuhara, Itami, Hyogo, 664-0005, Japan.
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  • Fumitoshi Yamamoto,

    Non-member
    1. Mixed Signal Device Technology Department, Production and Technology Unit, Renesas Technology Corporation, 4-1 Mizuhara, Itami, Hyogo, 664-0005, Japan
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  • Akio Uenishi,

    Member
    1. Mixed Signal Device Technology Department, Production and Technology Unit, Renesas Technology Corporation, 4-1 Mizuhara, Itami, Hyogo, 664-0005, Japan
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  • Takashi Kuroi,

    Non-member
    1. Mixed Signal Device Technology Department, Production and Technology Unit, Renesas Technology Corporation, 4-1 Mizuhara, Itami, Hyogo, 664-0005, Japan
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  • Shigeto Maegawa

    Non-Member
    1. Mixed Signal Device Technology Department, Production and Technology Unit, Renesas Technology Corporation, 4-1 Mizuhara, Itami, Hyogo, 664-0005, Japan
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Abstract

We proposed the balanced vertical double - diffused MOS (B-VDMOS) transistor. The B-VDMOS transistor is not destroyed by avalanche breakdown and acquires the high second breakdown current. Owing to the high second breakdown current, the B-VDMOS transistor has high electrostatic discharge (ESD) robustness. This paper presents the mechanism of the snapback phenomena and clarifies the cause that the B-VDMOS transistor has the high second breakdown current. We find the cause that current does not become concentrated even after avalanche breakdown in the B-VDMOS transistor. Copyright © 2009 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.

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