Special Issue Paper / Special Issue on State-of-the-Art MEMS Technologies
Development of RIE-lag Reduction Technique for Si Deep Etching Using Double Protection Layer Method
Version of Record online: 16 FEB 2010
Copyright © 2010 Institute of Electrical Engineers of Japan
IEEJ Transactions on Electrical and Electronic Engineering
Special Issue: Special Issue on State-of-the-Art MEMS Technologies / Special Issue on Electronics, Information and Systems
Volume 5, Issue 2, pages 125–130, March 2010
How to Cite
Ohara, J., Asami, K., Takeuchi, Y. and Sato, K. (2010), Development of RIE-lag Reduction Technique for Si Deep Etching Using Double Protection Layer Method. IEEJ Trans Elec Electron Eng, 5: 125–130. doi: 10.1002/tee.20506
- Issue online: 16 FEB 2010
- Version of Record online: 16 FEB 2010
- Manuscript Revised: 22 OCT 2009
- Manuscript Received: 19 JUN 2009
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