K. Rahimunnisa, P. Karthigaikumar, Soumiya Rasheed, J. Jayakumar and S. SureshKumar FPGA implementation of AES algorithm for high throughput using folded parallel architecture Security and Communication Networks
The proposed structure combines the features of folding concept with parallel processing. The combined structure is implemented in Virtex-6 XC6VLX75T FPGA device. This work gives a high throughput of 37.1 Gb/s with a maximum frequency of 505.5 MHz, which is 20% higher than the maximum throughput reported in the literature.
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