E-mail

E-mail a Wiley Online Library Link

Volker Schmidt, Heike Riel, Stephan Senz, Siegfried Karg, Walter Riess and Ulrich Gösele Realization of a Silicon Nanowire Vertical Surround-Gate Field-Effect Transistor Small 2

Article first published online: 7 NOV 2005 | DOI: 10.1002/smll.200500181

Thumbnail image of graphical abstract

A generic process for fabricating vertical surround-gate field-effect transistors (FETs) from epitaxially grown silicon nanowires is presented. The process is demonstrated using n-type Si nanowires grown on a p-type substrate in ultrahigh vacuum using a Au catalyst. The process consists of various deposition and etching steps; no chemical or mechanical polishing is required. Individual as well as arrays of vertical surround-gate FETs can be fabricated.

Complete the form below and we will send an e-mail message containing a link to the selected article on your behalf

Required = Required Field

Choose captcha format: Image or Audio. Click here if you need help.

SEARCH