International Journal of Circuit Theory and Applications

Cover image for Vol. 46 Issue 2

Early View (Online Version of Record published before inclusion in an issue)

Edited By: Ángel Rodríguez-Vázquez

Impact Factor: 1.571

ISI Journal Citation Reports © Ranking: 2016: 145/262 (Engineering Electrical & Electronic)

Online ISSN: 1097-007X


  1. 1 - 44

    1. Synchronous and asynchronous operation in dual-band VCOs

      Antonio Buonomo and Alessandro Lo Schiavo

      Version of Record online: 22 FEB 2018 | DOI: 10.1002/cta.2454

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      A comprehensive analysis of the asynchronous and synchronous operations of fourth-order oscillators underlying dual-band voltage-controlled oscillators is presented. As far as is known to the authors, we analyze for the first time the occurrence of the self-synchronization phenomenon (internal resonance) if the ratio of normal frequencies is nearly a ratio of integers, which is 1:3 in the cubic approximation of the nonlinear oscillator characteristic. In both cases of asynchronous and synchronous operations, we get the equations describing the first-order dynamics (averaging equations) by which the stationary and transient oscillations and their stability can be easily analyzed. Solving these equations in the stationary state, we get the amplitudes of the fundamental and of the third harmonic in synchronous operation.

    2. A new topology for nonisolated multiport zero voltage switching dc-dc converter

      Ebrahim Babaei, Zahra Saadatizadeh and Pedram Chavoshipour Heris

      Version of Record online: 22 FEB 2018 | DOI: 10.1002/cta.2451

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      In this paper, a new multiport zero voltage switching dc-dc converter with cancelling the input current ripple and extending the input sources at low voltage side is proposed. The proposed topology can operate in 3 operational modes of boost, buck, and buck-boost. In addition, it has the ability of interfacing 3 different voltages only by using 3 switches.

    3. Electrical model of the alkaline electrolyser dedicated for SPICE

      Krzysztof Górecki, Paweł Górecki and Janusz Zarębski

      Version of Record online: 20 FEB 2018 | DOI: 10.1002/cta.2459

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      In this paper, properties of the alkaline electrolyser fed from the voltage source, producing the rectangular pulse train, were investigated. A model of this electrolyser for SPICE in the form of an electrical network was proposed. The structure of this electrical model was described, and the values of parameters of the model were presented. The correctness of this model was verified experimentally in a wide range of frequencies. Using the worked out model, several characteristics of the electrolyser were calculated, and the influence of amplitude, frequency, and the duty factor of the supplying voltage on productivity and watt-hour efficiency of the electrolysis process was discussed. The investigations were performed for 2 different concentration values of the KOH solution.

    4. FPGA-based implementation for improved control scheme of grid-connected PV system with 3-phase 3-level NPC-VSI

      Satabdy Jena, Gayadhar Panda and Rangababu Peesapati

      Version of Record online: 20 FEB 2018 | DOI: 10.1002/cta.2448

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      Highlights: The paper employs an improved current control algorithm for the effective operation of grid-connected PV system with three-phase three-level NPC-VSI The algorithm has been implemented in ML 605 Field programmable gate array. Hardware in loop has been demonstrated for validation of proposed control scheme.

    5. Generalized analytical formulae to compute electrical characteristics of a homogenous ladder network of the transformer winding

      Mithun Mondal and Ganesh Balu Kumbhar

      Version of Record online: 13 FEB 2018 | DOI: 10.1002/cta.2446

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      This paper derives generalized analytical expressions that can be directly utilized to obtain the electrical characteristics of a finite as well as semi-infinite homogenous ladder network by simply plugging the values of its constituent parameters without solving recursive circuit equations and avoiding complex state-space matrices.

    6. Digital implementation of biologically inspired Wilson model, population behavior, and learning

      Gholamreza Karimi, Morteza Gholami and Edris Zaman Farsa

      Version of Record online: 9 FEB 2018 | DOI: 10.1002/cta.2457

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      This paper presents a method to the implementation of Wilson neurons on digital platforms, suggesting that the available system is an attainable platform for the implementation of large-scale biologically plausible neural networks on FPGA devices. Hardware synthesis, physical implementation on FPGA and theoretical analysis confirm that the proposed model having a hardware so that makes it an appropriate model for the large scale digital implementation.

    7. Positive-real property of passive fractional circuits in W-domain

      Guishu Liang and Chang Liu

      Version of Record online: 30 JAN 2018 | DOI: 10.1002/cta.2443

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      Passive criteria of fractional circuits with rational order elements based on s-W transformation are proposed in this manuscript. Definitions of positive-real (matrix) function in W-domain are given, and the equivalence conditions of positive realness are derived. In addition, a conclusion is proposed in which the immittance (matrix) function of passive fractional circuits with rational order elements is positive real in W-domain. The applications of passive criteria in circuit synthesis are shown. The criteria solve the problem that passivity is not equivalent with positive-real property of fractional immittance (matrix) function in s-domain and extend the range for passive circuit realization and modeling.

    8. A faster phase frequency detector using transmission gate–based latch for the reduced response time of the PLL

      Aravinda Koithyar and T.K. Ramesh

      Version of Record online: 23 JAN 2018 | DOI: 10.1002/cta.2449

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      This article presents a new design of phase frequency detector without reset, in which the blind zone and dead zone issues in the phase locked loop are annihilated. The design of phase frequency detector is based on transmission gate–based latches, which produce UP and DOWN pulses only when there is a distinct phase difference between the reference and divided frequencies, thus avoiding the continuous pulses that get produced by the conventional D flip-flop–based latches.

    9. A novel active-clamp zero-voltage-switching buck-boost converter

      Pham Phu Hieu, Yao-Ching Hsieh, Jing-Yuan Lin, Bing-Siang Huang and Huang-Jen Chiu

      Version of Record online: 23 JAN 2018 | DOI: 10.1002/cta.2441

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      An active-clamp zero-voltage-switching (ZVS) buck-boost converter is proposed in this paper to improve the performance of converter in light load condition. By using a small resonant inductor, the ZVS range of switches could be adjusted to very light load condition. Moreover, 2 clamping capacitors are added in the converter to eliminate the voltage spike on the switches during switching transition. The operating principle of proposed converter is analyzed, and the optimal design guide for full range ZVS is also provided. A 60 W output prototype is experimentally built and tested in laboratory to verify the feasibility of proposed converter. The measured results show the critical ZVS operation of power switches at 1 W and 0.7 W output power for buck and boost mode, respectively. The peak conversion efficiency is up to 92.3%.

    10. A power-performance tunable logic with adjustable threshold pseudo-dynamic building blocks and CMOS compatibility

      Hanieh Ghaffarishad, Naser Mohammadzadeh and Mohammad-Bagher Ghaznavi-Ghoushchi

      Version of Record online: 23 JAN 2018 | DOI: 10.1002/cta.2447

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      In this paper, a novel logic family is proposed that enables tuning the transistor's effective threshold voltage after fabrication for higher speed or lower power. The externally static topology of the proposed logic makes it possible to replace static circuits without requiring significant changes in the system. Experimental results obtained using 90-nm CMOS standard technology show that the proposed logic improves the average power-delay product by about 40% for the attempted benchmarks.

    11. Design and analysis of a millimeter-wave injection locked frequency divider with transconductance boosting technique

      Mahsa Abomaashzadeh, Abdolreza Nabavi and Saeed Saeedi

      Version of Record online: 23 JAN 2018 | DOI: 10.1002/cta.2440

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      This paper presents a degenerated injector (mixer) with transconductance boosted by biasing the mixer transistor in the knee region of its I-V curve, without increasing the transistor size and its parasitics. This mixer can enhance the locking range of millimeter-wave injection-locked frequency dividers. To compensate the degradation of mixer transconductance due to the degeneration effect, a neutralization technique is used. It is shown that the locking range, as a function of injection strength, is improved by increasing the fundamental component of transconductance.

    12. A 0.1 to 2.7-GHz SOI SP8T antenna switch adopting body self-adapting bias technique for low-loss high-power applications

      Zhihao Zhang, Gary Zhang, Kai Yu, Junming Lin and Zuhua Liu

      Version of Record online: 3 JAN 2018 | DOI: 10.1002/cta.2437

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      This paper presents a low-loss high-power SOI CMOS single-pole 8-throw antenna switch adopting body self-adapting bias technique. The new body bias strategy that employs a diode-connected device between the gate and body of the body-contacted switch transistor helps to lower insertion loss, imbalanced voltage division, and die area. The overall insertion loss and P−0.1dB are apparently improved by approximately 0.05 to 0.13 dB and 0.5 to 0.8 dBm compared with the conventional version.

    13. A new non-isolated free ripple input current bidirectional DC-DC converter with capability of zero voltage switching

      Zahra Saadatizadeh, Pedram Chavoshipour Heris, Mehran Sabahi, Mehrdad Tarafdar Hagh and Mohammad Maalandish

      Version of Record online: 26 DEC 2017 | DOI: 10.1002/cta.2435

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      In this paper, a new nonisolated free ripple input current bidirectional dc-dc converter with capability of zero voltage switching (ZVS) is proposed. In the proposed converter by using a 3-winding coupled inductor, the voltage conversion ratio is increased and the free ripple input current condition at low voltage side is achieved for a whole range of duty cycles in comparison with common topologies. The proposed converter uses an auxiliary inductor for achieving ZVS turning ON for 2 switches for different values of output power.

    14. Compressive sensing-based adaptive sparse predistorter design for power amplifier linearization

      Yao Yao, Mingyu Li, Yi Jin, Weiliang Jiang, Yifan Wang, Mingdong Zhu and Songbai He

      Version of Record online: 26 DEC 2017 | DOI: 10.1002/cta.2445

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      In this paper, a powerful subspace pursuit greedy scheme combined with stochastic gradient descent adaptive algorithm is proposed to design a class of adaptive sparse digital predistorters (DPDs). Simulation and experimental results show that proposed algorithm can efficiently construct the adaptive sparse DPD models with only a small number of parameters. Compared with the batch mode compressive sensing model DPD, the proposed approach exhibits adaptive tracking capabilities while offers the similar compensation performance.

    15. Transfer function-matched capacitor-current sensing and its circuit implementation for high-frequency power converters

      Weiguo Lu, Shidong Yan, Yidi Yang and Huimin Fang

      Version of Record online: 26 DEC 2017 | DOI: 10.1002/cta.2442

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      In this paper, a paralleled noninvasive sensing circuit scheme for capacitor current is proposed by matching the transfer functions of the sensing circuit and the sensed capacitor branch, and further, 4 possible circuit topologies are derived in theory. Experiment results confirm the rapidity and accuracy of the proposed sensing circuit scheme, and with the application of 2 of candidate topologies to a constant-frequency hysteresis controlled Buck converter, a very fast load transient response is achieved.

    16. A portable class of 3-transistor current references with low-power sub-0.5 V operation

      Felice Crupi, Raffaele De Rose, Maksym Paliy, Marco Lanuzza, Mattia Perna and Giuseppe Iannaccone

      Version of Record online: 20 DEC 2017 | DOI: 10.1002/cta.2439

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      This work proposes a new class of current references based on only 3 transistors that allows sub-0.5 V operation. The circuit consists of a 2-transistor block that generates a proportional-to-absolute temperature or a complementary-to-absolute-temperature voltage and a load transistor. The idea of a 3T current reference is validated by circuit simulations for different complementary metal oxide semiconductor technologies and by experimental measurements on a large set of test chips fabricated with a commercial 0.18 μm complementary metal oxide semiconductor process. As compared to the state-of-art competitors, the 3T current reference exhibits competitive performance in terms of temperature coefficient (578 ppm/°C), line sensitivity (3.9%/V), and power consumption (213 nW) and presents a reduction by a factor of 2 to 3 in terms of minimum operating voltage (0.45 V) and an improvement of 1 to 2 orders of magnitude in terms of area occupation (750 μm2). In spite of the extremely reduced silicon area, the fabricated chips exhibit low-process sensitivity (2.7%). A digital trimming solution to significantly reduce the process sensitivity is also presented and validated by simulations.

    17. Design-oriented model for power-driven design optimization of SC-ΣΔ modulators

      Andrea Boni, Luca Giuffredi, Giorgio Pietrini, Alessandro Magnanini and Matteo Tonelli

      Version of Record online: 14 DEC 2017 | DOI: 10.1002/cta.2436

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      A behavioral model for SC-SD modulators, suitable for power-driven design and optimization, is presented. By means of an accurate model of the settling error and noise of the integrator, a global power minimization is achieved. In spite of the improved accuracy, the proposed model requires only a few parameters of the amplifier in the integrator. This allows to easily link the model to an external set of circuit equations, to be derived for the specific amplifier used in the modulator.

    18. Bessel-like compensation of three-stage operational transconductance amplifiers

      Gianluca Giustolisi and Gaetano Palumbo

      Version of Record online: 8 DEC 2017 | DOI: 10.1002/cta.2438

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      We introduce a simple approach for the design of fast settling amplifiers suitable for switched capacitors circuits and characterized by low capacitive loads. The design is based on a new Bessel-like compensation that set the phase of the closed-loop amplifier to be linearly related to the frequency, thus emulating the behaviour of an ideal delay. The proposed approach is validated through the design and the simulation of two three-stage amplifiers in a 65-nm CMOS process.

    19. A high-voltage gain nonisolated noncoupled inductor based multi-input DC-DC topology with reduced number of components for renewable energy systems

      Kazem Varesi, Seyed Hossein Hosseini, Mehran Sabahi and Ebrahim Babaei

      Version of Record online: 29 NOV 2017 | DOI: 10.1002/cta.2428

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      This paper proposes a modular nonisolated noncoupled inductor-based high-voltage gain multi-input DC-DC converter, in which bidirectional capability has been provided. Despite the high-voltage gain of the proposed topology, the average of normalized voltage stress (NVS) on switches/diodes is low, compared with recently presented high step-up topologies. This property leads to less loss and cost of switches/diodes. The proposed topology uses less number of components (capacitors, inductors, diodes, and switches) for producing a desired voltage gain. In other words, for the same number of components and values of duty cycles, the proposed topology presents higher voltage gains, in comparison with recently presented high step-up topologies. So, the proposed topology is expected to have less size, mass, cost, complexity and losses, and higher efficiencies. Continuous current of input sources is another main advantage of proposed topology. All abovementioned characteristics have made the proposed topology very suitable for renewable energy systems or even hybrid/electric vehicles.

    20. A minimum five-component five-term single-nonlinearity chaotic jerk circuit based on a twin-jerk single-op-amp technique

      Buncha Munmuangsaen and Banlue Srisuchinwong

      Version of Record online: 29 NOV 2017 | DOI: 10.1002/cta.2423

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      Algebraically twin chaotic jerk circuits are presented. Each circuit is based on a single op-amp. One of the circuits is a minimum 5-component 5-term single-nonlinearity chaotic jerk circuit, and is presented as the first simplest chaotic jerk circuit in a category that a single op-amp is employed. Two cross verifications of trajectories of both circuits are illustrated through numerical and experimental results.

    21. Microstrip band-pass filters without source/load inverters

      Fei Xiao

      Version of Record online: 24 NOV 2017 | DOI: 10.1002/cta.2427

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      In this paper, the concept of the distributed- to lumped-element equivalence is applied in the design of several microstrip band-pass filters without source/load impedance inverters. As demonstrated, it can help to reveal the physical mechanism of the filters such as how the resonances are created and coupled. In addition, the distributed- to lumped-element equivalence relations between filter specifications and structural parameters are presented and good initial dimensions are calculated, which will facilitate filter design.

    22. A power-efficient current-mode neural/muscular stimulator design for peripheral nerve prosthesis

      Xu Liu, Lei Yao, Kian Ann Ng, Peng Li, Wensi Wang, Minkyu Je and Yong Ping Xu

      Version of Record online: 21 NOV 2017 | DOI: 10.1002/cta.2434

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      This paper presents a 16-channel power-efficient neural/muscular stimulation integrated circuit for peripheral nerve prosthesis. First, the theoretical analysis is presented to show the power efficiency optimization in a stimulator. Moreover, a continuous-time, biphasic exponential-current-waveform generation circuit is designed based on Taylor series approximation and implemented in the proposed stimulation chip to optimize the power efficiency. Finally, the chip is implemented and the maximum stimulation power efficiency of 95.9% is achieved at the output stage of the stimulator in the measurement.

    23. A novel analog switch for high-precision switched-capacitor applications

      Saeed Naghavi, Niloofar Sharifi and Adib Abrishamifar

      Version of Record online: 14 NOV 2017 | DOI: 10.1002/cta.2432

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      This paper introduces a new technique to design a high-precision analog metal-oxide-semiconductor switch for switched-capacitor applications. The performance of a switched-capacitor circuit strongly depends on its analog switches. In this work a novel technique to minimize the charge injection and clock feedthrough errors by using a very simple structure is proposed. Moreover, an innovative approach to increase the OFF resistance of the switch and consequently minimizing its leakage current is presented.


    24. Pulsed time-of-flight pixel with on-chip 20 klux background light suppression in standard CMOS technology

      Julio Illade-Quinteiro, Paula López, Víctor M. Brea and Diego Cabello

      Version of Record online: 14 NOV 2017 | DOI: 10.1002/cta.2426

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      A novel time-of-flight pixel designed in 0.18-μm standard CMOS technology with an indirect pulsed technique is presented. This design is capable of operating in ambients with high levels of background light, since a novel in-pixel background suppression circuit makes it robust up to 20 klux of ambient light. In addition to this, the pixel incorporates an adaptive number of accumulations circuit that selects the optimum number of accumulations for each situation at pixel level, avoiding saturation even under high illumination conditions.

    25. You have full text access to this OnlineOpen article
      A systematic approach to designing a wide-current range, MOS capacitor-based switched-capacitor DC-DC converter with an augmenting LDO

      Hakan Dogan and Shady A. El-Sayed Mohammed

      Version of Record online: 10 NOV 2017 | DOI: 10.1002/cta.2433

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      A practical approach is employed to analyze switched-capacitor DC-DC converters (SC DC-DC) for loss sources, voltage regulation integrity, start-up latency, and ripple size, while the trade-offs between these metrics are derived. These analyses are used to design a SC DC-DC that achieves 75.4% peak efficiency in a wide load current range using core MOS capacitors. An augmenting LDO that only regulates during sudden load transients helps the converter respond fast to these transients.

    26. A 99.95% linearity readout circuit with 72 dB dynamic range for active pixel sensors

      Leonardo Bruno de Sá, Mauricio Henrique Costa Dias, Antoine Dupret and Antonio Carneiro de Mesquita Filho

      Version of Record online: 8 NOV 2017 | DOI: 10.1002/cta.2425

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      One of the main sources of nonlinearity and sensitivity degradation in conventional active pixel sensor architectures is the source follower amplifier. To extend the linear region of the output voltage, correct the sensitivity degradation, and improve the imager dynamic range, an output regulated voltage follower is proposed. All these enhancements are achieved without decreasing the pixel fill factor nor increasing the number of transistors and the addressing circuits complexity of a conventional 4T CMOS active pixel sensor.

    27. Full-wave analysis of traveling pulses developed in a system of transmission lines with regularly spaced resonant-tunneling diodes

      Koichi Narahara and Koichi Maezawa

      Version of Record online: 25 OCT 2017 | DOI: 10.1002/cta.2421

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      Three sentences of text summarizing the key findings:

      • -
        Full-wave analysis succeeds in describing traveling-pulse phenomenon in a system of coupled transmission lines with regularly spaced resonant-tunneling diodes.
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        The full-wave calculations illustrate the difficulties in mutual synchronization at relatively high frequencies.
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        The device structure is proposed for proper multiphase oscillations at submillimeter-wave frequencies.
    28. Reliability challenge for impedance network-based DC-DC boost converters

      Mohammad Mehdi Haji-Esmaeili and Ebrahim Babaei

      Version of Record online: 25 OCT 2017 | DOI: 10.1002/cta.2420

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      In this paper, Markov reliability evaluation approach is used to evaluate the reliability of some famous impedance network-based DC-DC converters. Components' failure rates, reliability functions, and mean time to failures are also evaluated mathematically and also numerically through the simulation results obtained from PSCAD/EMTDC. Graphical reliability comparison between the converters is provided, and the results in order from better reliability to worse will be as follows: (i) A-source, (ii) Y-source, (iii) TSTS-Z-source, (iv) ΓZ-source, (v) Γ-source, (vi) Z-source, (vii) Quasi-Y-source, (viii) Quasi-Z-source, (ix) Trans-Z-source, (x) Improved Trans-Z-source, and (xi) TZ-source.

    29. Experimentally approved generalized model for circuit applications

      Bülent Bilgehan, Ali Özyapıcı and Zehra B. Sensoy

      Version of Record online: 17 OCT 2017 | DOI: 10.1002/cta.2415

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      In this paper, generalized model based on the multiplicative least square method presented and shown that it is convenient to approximate observation in the electrical system analysis. The advantage of the method is due to exponential derivation process within multiplicative calculus and has the flexibility to represent widely used functions such as Gaussian and exponentials. The presented model is challenging because modern electrical circuits and systems are faced with different types of inputs that require exact representation for accurate processing.

    30. A 12-bit 10-MS/s SAR ADC with a binary-window DAC switching scheme in 180-nm CMOS

      Yung-Hui Chung, Chia-Wei Yen and Pei-Kang Tsai

      Version of Record online: 17 OCT 2017 | DOI: 10.1002/cta.2424

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      This study presents an energy efficient 12-bit successive approximation-register A/D converter. The proposed binary-window D/A converter switching scheme can effectively reduce D/A converter nonlinearity and switching errors to improve both spurious-free dynamic range and signal-to-noise-and-distortion ratio. The measured differential nonlinearity and integral nonlinearity are 0.57 and 0.73 least significant bit, respectively. The approximation-register The A/D converter prototype consumes a total power of 0.6 mW from a 1.5-V supply. It achieves a 64.7-dB signal-to-noise-and-distortion ratio and 83-dB spurious-free dynamic range at 10 MS/s, corresponding to a figure-of-merit of 48 fJ/conversion-step.

    31. Simple approximate phase cancellation for repetitive control of CVCF PWM inverters

      Dapeng Li and Yongqiang Ye

      Version of Record online: 9 OCT 2017 | DOI: 10.1002/cta.2400

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      In this paper, a simple approximate phase cancellation repetitive controller is proposed for a constant-voltage constant-frequency pulse-width modulation inverter. The compensator is a linear combination of linear phase compensators, which can better fit the inverse of a plant model phase curve compared with the conventional linear phase compensator. Repetitive controllers with the proposed phase compensator can improve pulse-width modulation inverter system's stability, tracking accuracy, and error convergence rate.

    32. An oscillatory noise-shaped quantizer for time-based continuous-time sigma-delta modulators

      Mohsen Tamaddon and Mohammad Yavari

      Version of Record online: 27 SEP 2017 | DOI: 10.1002/cta.2422

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      In this paper, a time-based noise-shaped quantizer (NSQ) is proposed. The NSQ is based on a binary comparator-based asynchronous pulse-width modulator. Owing to the time-based quantization, using a linearized model for the NSQ becomes more feasible. Using this model, a fully continuous-time implementation of the NSQ is realized. The ploy-phase sampler inside the NSQ is based on the combination of a time-to-digital and a digital-to-time converter. The noise-shaping order of an NSQ-based time-based continuous-time sigma-delta modulators is increased up to 2 incorporating the proposed NSQ.

    33. Circuit model of photoswitchable proteins

      Balázs Rakos

      Version of Record online: 20 SEP 2017 | DOI: 10.1002/cta.2416

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      Reversibly photoswitchable fluorescent proteins have already found applications in many biology-related areas such as superresolution cellular imaging, interaction, and movement tracking of proteins. However, they are of great potential in information storage systems, and logic computing circuits of the future, as well. In this work, we present a simple circuit model capable of simulating the photoswitching behavior of such proteins. The circuit consists of basic electronic elements, and it can be easily extended to simulate complex photoswitching behavior, as well.

    34. An extensible two-phase high voltage-boosting converter with automatic current balance

      K.I. Hwu, W.Z. Jiang and P.Y. Wu

      Version of Record online: 19 SEP 2017 | DOI: 10.1002/cta.2417

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      An extensible two-phase interleaved high step-up converter with automatic current balance is presented. This converter uses coupled inductors and energy-transferring capacitors to improve the voltage gain of the traditional two-phase interleaved boost converter as well as employs these energy-transferring capacitors to do automatic current balance. Furthermore, the voltage gain can be enhanced not only by adjusting the turns ratio but also by increasing the numbers of phases, diodes, and energy-transferring capacitors.

    35. Drawbacks of impedance networks

      Zbigniew Rymarski and Krzysztof Bernacki

      Version of Record online: 10 SEP 2017 | DOI: 10.1002/cta.2395

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      This paper presents the influence of voltage-fed impedance networks, known as Z-Source and quasi–Z-Source, in addition to some more sophisticated networks on the static and dynamic properties of voltage source inverters. The impedance networks increase output voltage distortions and decrease the power efficiency. The distortions of the output voltage increase for the discontinuous current mode of the impedance network. The DC voltage boost factor depends on impedance network power losses. The impedance network influences on the inverter control transfer function.

    36. 67-90 GHz broadband power detector with 3 GHz output bandwidth for on-chip test of millimeter-wave circuits

      David del Rio, Iñaki Gurutzeaga, Ainhoa Rezola, Igone Velez and Roc Berenguer

      Version of Record online: 6 SEP 2017 | DOI: 10.1002/cta.2396

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      This article presents the design of a broadband millimeter-wave power detector and demonstrates its performance with measurement results. It senses the output power of a power amplifier over a frequency range of 67 to 90 GHz. It detects signal envelopes with a bandwidth up to 3 GHz, which outperforms other reported detectors.

    37. Impact of the RT-level architecture on the power performance of tunnel transistor circuits

      María J. Avedillo and Juan Núñez

      Version of Record online: 5 SEP 2017 | DOI: 10.1002/cta.2398

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      In this paper, we analyze the relationship between tunnel field-effect transistors (TFETs) and RT-level architectural choices. In particular, the potential of pipeline and parallelism as power reduction techniques that, in both cases, rely on the lowering of the supply voltage allowed by relaxed timing constraints is evaluated and compared for CMOS and TFET technologies. These techniques allow taking full advantage of the distinguishing characteristics of TFETs and should be explored in the context of the design of competitive architectures.

    38. A wide range delay locked loop for low power and low jitter applications

      Motahhareh Estebsari, Mohammad Gholami and Mohammad Javad Ghahramanpour

      Version of Record online: 5 SEP 2017 | DOI: 10.1002/cta.2401

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      This paper introduces a design for analog delay locked loop using new techniques to increase operating frequency range and reduce jitter. A new delay cell is proposed with a wide delay range, resulting in using fewer cells and, consequently, a reduction in power consumption. Current mirror techniques and feedback in the proposed charge pump also cause higher current matching and better jitter performance. Our delay locked loop has been designed with TSMC 0.18-μm CMOS technology and has wide frequency range from 217 to 800 MHz. It consumes maximum 3.4-mW and minimum 2.6-mW power dissipation in a source voltage of 1.8 V, making it suitable for low power applications. It also has an appropriate lock time which is at least equal to 3 clock cycles at 217 MHz and at most 25 clock cycles at 800 MHz. Jitter performance is improved significantly: RMS jitter is 0.65 ps at 800 MHz and 2.54 ps at 217 MHz. The maximum peak-to-peak jitter is equal to 5.17 ps, and its minimum peak-to-peak jitter is equal to 1.39 ps at 217 and 800 MHz, respectively.

    39. Power-efficient burst-mode RF transmitter based on reference-adaptive multilevel pulse-width modulation

      Amir Arian and Abumoslem Jannesari

      Version of Record online: 4 SEP 2017 | DOI: 10.1002/cta.2394

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      In this paper, a novel multilevel PWM modulator is proposed that utilizes adaptive triangular reference waveforms. This architecture provides a wide design space such that the efficiency of system can be effectively optimized. A general transmitter architecture based on the proposed concept is analyzed in terms of power efficiency. Based on the proposed modulator, an optimized RF transmitter is designed in a 0.18-μm CMOS process. The circuit-level simulations show that it achieves 28.8% (average) efficiency at 17.3-dBm (average) output power for a 20-MHz WiMAX signal with 8.5-dB PAPR.


    1. Wide-band dual-resonance capacitive cross-coupled divide-by-5 injection-locked frequency divider

      Sheng-Lyang Jang, Kei-Wu Lu and Yi-Ru Huang

      Version of Record online: 31 AUG 2017 | DOI: 10.1002/cta.2393

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      A wide-locking range CMOS divide-by-5 injection-locked frequency divider, in Figure 2A, uses dual-resonance RLC resonator, two injection transistors, and a capacitive cross-coupled pair. Figure 5 shows the measured input sensitivity plot. The measured locking range of the divide-by-5 ILFD is 3.2 GHz, from the incident frequency 9.4 to 12.6 GHz at the core power consumption 2.98 mW.


    1. Performance analysis and calculation of critical inductance and output voltage ripple of a simple non-isolated multi-input bidirectional DC-DC converter

      Kazem Varesi, Seyed Hossein Hosseini, Mehran Sabahi and Ebrahim Babaei

      Version of Record online: 25 AUG 2017 | DOI: 10.1002/cta.2392

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      This paper proposes a simple multi-input DC-DC topology which can operate in buck, boost, or buck-boost modes. It utilizes a battery pack to realize the bidirectional operation. Excess energy of inputs can be stored in the battery and be injected to the load when needed. Simultaneous/independent power transfer of inputs is provided. The proposed topology utilizes less number of components. The efficiency of the proposed topology is higher than the topology that it has been derived. Generalized relationships have been proposed for calculating the critical inductance and output voltage ripple of proposed n-input boost topology.

    2. Nonaveraged control-oriented modeling and relative stability analysis of DC-DC switching converters

      Y. Al-Turki, A. El Aroudi, K. Mandal, D. Giaouris, A. Abusorrah, M. Al Hindawi and S. Banerjee

      Version of Record online: 18 AUG 2017 | DOI: 10.1002/cta.2387

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      This paper presents a non-averaged approach for studying the relative stability of switching converters. By treating the modulator as a gain, the model is formulated in a way that standard control-oriented tools such as Bode diagrams and root-loci can be used hence giving gain and phase margins that are highly useful in controller design. The paper points out the sources of discrepancies between the new approach and the averaged model. The theoretical results are validated by simulations using the switched model.

    3. A 6-bit 4 MS/s 26fJ/conversion-step segmented SAR ADC with reduced switching energy for BLE

      Behnam Samadpoor Rikan, Hamed Abbasizadeh, Sung-Hun Cho, Sang-Yun Kim, Imran Ali, SungJin Kim, DongSoo Lee, YoungGun Pu, MinJae Lee, KeumCheol Hwang, Youngoo Yang and Kang-Yoon Lee

      Version of Record online: 16 AUG 2017 | DOI: 10.1002/cta.2388

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      This paper presents a 6-bit 4 MS/s successive approximation register analog-to-digital converter in which new switching is applied in segmented digital-to-analog converter. This structure achieves high energy efficiency by avoiding the requirement of common mode voltage and skipping some of the unnecessary conversion steps in a VCM-based successive approximation register analog-to-digital converter. To ensure the common mode voltage remains comparatively steady, and to avoid employing power-hungry common mode reference voltage circuits, each capacitor is divided into 2 identical small capacitors, connecting one of them to “high” and the other one to “low”. Silicon fabrication and measurement results are presented for this structure.

    4. Modeling power supplies of LED lamps

      Krzysztof Górecki and Przemysław Ptak

      Version of Record online: 7 JUL 2017 | DOI: 10.1002/cta.2382

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      In the paper, the model of the power supply of the LED lamp in the form dedicated for SPICE is proposed. The form of the worked out authors' model is presented, and the results of experimental verification of this model for the LED lamp of the type CLA25 are shown. The presented model is elaborated only for the power supply of LED lamps, in which the constant output voltage is stabilized. This model has the form of a subcircuit for SPICE, and it describes the influence of load resistance, amplitude of the input voltage, and the ambient temperature on both the input current and the output voltage. It is confirmed that the worked out model describes correctly both the waveform of the current received from the electroenergy network and the influence of the load current, the ambient temperature, and the supply voltage on the output voltage.


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