International Journal of Circuit Theory and Applications

Cover image for Vol. 45 Issue 9

Edited By: Ángel Rodríguez-Vázquez

Impact Factor: 1.571

ISI Journal Citation Reports © Ranking: 2016: 144/260 (Engineering Electrical & Electronic)

Online ISSN: 1097-007X

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About International Journal of Circuit Theory and Applications

The International Journal of Circuit Theory and Applications is devoted to the publication of original work on both the theory and its applications. It brings together papers describing advances in the theory and in the application of circuit theoretic concepts intendeds to be of interest both in stimulating the wider use of such concepts and in posing new challenges for the circuit theorist.

Read the journal's full aims and scope here

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Call for papers - Special Issue on Computational Image Sensors and Smart Camera Hardware

The International Journal of Circuit Theory and Applications invites authors to submit their papers to this special issue on computational image sensors and smart camera hardware. Read the full aims and scope of the issue here.

Paper submission deadline:September 30, 2017

Recently Published Articles

  1. Circuit model of photoswitchable proteins

    Balázs Rakos

    Version of Record online: 20 SEP 2017 | DOI: 10.1002/cta.2416

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    Reversibly photoswitchable fluorescent proteins have already found applications in many biology-related areas such as superresolution cellular imaging, interaction, and movement tracking of proteins. However, they are of great potential in information storage systems, and logic computing circuits of the future, as well. In this work, we present a simple circuit model capable of simulating the photoswitching behavior of such proteins. The circuit consists of basic electronic elements, and it can be easily extended to simulate complex photoswitching behavior, as well.

  2. An extensible two-phase high voltage-boosting converter with automatic current balance

    K.I. Hwu, W.Z. Jiang and P.Y. Wu

    Version of Record online: 19 SEP 2017 | DOI: 10.1002/cta.2417

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    An extensible two-phase interleaved high step-up converter with automatic current balance is presented. This converter uses coupled inductors and energy-transferring capacitors to improve the voltage gain of the traditional two-phase interleaved boost converter as well as employs these energy-transferring capacitors to do automatic current balance. Furthermore, the voltage gain can be enhanced not only by adjusting the turns ratio but also by increasing the numbers of phases, diodes, and energy-transferring capacitors.

  3. Drawbacks of impedance networks

    Zbigniew Rymarski and Krzysztof Bernacki

    Version of Record online: 10 SEP 2017 | DOI: 10.1002/cta.2395

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    This paper presents the influence of voltage-fed impedance networks, known as Z-Source and quasi–Z-Source, in addition to some more sophisticated networks on the static and dynamic properties of voltage source inverters. The impedance networks increase output voltage distortions and decrease the power efficiency. The distortions of the output voltage increase for the discontinuous current mode of the impedance network. The DC voltage boost factor depends on impedance network power losses. The impedance network influences on the inverter control transfer function.

  4. 67-90 GHz broadband power detector with 3 GHz output bandwidth for on-chip test of millimeter-wave circuits

    David del Rio, Iñaki Gurutzeaga, Ainhoa Rezola, Igone Velez and Roc Berenguer

    Version of Record online: 6 SEP 2017 | DOI: 10.1002/cta.2396

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    This article presents the design of a broadband millimeter-wave power detector and demonstrates its performance with measurement results. It senses the output power of a power amplifier over a frequency range of 67 to 90 GHz. It detects signal envelopes with a bandwidth up to 3 GHz, which outperforms other reported detectors.

  5. Impact of the RT-level architecture on the power performance of tunnel transistor circuits

    María J. Avedillo and Juan Núñez

    Version of Record online: 5 SEP 2017 | DOI: 10.1002/cta.2398

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    In this paper, we analyze the relationship between tunnel field-effect transistors (TFETs) and RT-level architectural choices. In particular, the potential of pipeline and parallelism as power reduction techniques that, in both cases, rely on the lowering of the supply voltage allowed by relaxed timing constraints is evaluated and compared for CMOS and TFET technologies. These techniques allow taking full advantage of the distinguishing characteristics of TFETs and should be explored in the context of the design of competitive architectures.

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