Investigation of Maximum Junction Temperature for 4H‐SiC MOSFET During Unclamped Inductive Switching Test

SUMMARY

Normally, thermal breakdown is one of the serious failure phenomena in the power device application, which drives the researchers to focus on exploration of the failure mechanism and the new evaluation method for power device. In this paper, unclamped inductive switching test is presented to evaluate energy handing ability and maximum junction temperature of 1200 V/19 A SiC MOSFET during avalanche mode. It is verified that commercial 1200 V/19 A SiC MOSFET can easily withstand almost 10 μs avalanche time and around 924 K maximum junction temperature with 1 mH inductance and 400 V dc bus at the case temperature of 300 K in avalanche mode. In addition, three reasonable evaluation methods of the maximum junction temperature for SiC MOSFET are summarized at different case temperatures.

1. Introduction

Silicon carbide (SiC) is a wide‐gap‐band semiconductor offering excellent properties, namely, high breakdown field strength and thermal conductivity; this material is expected to be widely used instead of silicon (Si) wherever withstanding high voltage and current as well as high‐temperature operation are required. Particularly, SiC MOSFET is the most promising as an ideal wide‐gap‐band semiconductor for electric power systems in terms of not only allowing high‐temperature operation but also low‐power consumption in ON state. Recently, high‐voltage heavy‐current SiC MOSFETs have started entering some markets.

In order to use SiC MOSFET at same voltage and current as Si IGBT, the same or higher level of breakdown endurance and reliability is required. In order to improve the breakdown performance, one needs to clarify device failure mechanisms in avalanche mode, in high‐power density operation, or under high voltage so as to modify or optimize device structure. There are evaluation reports of avalanche characteristics of SiC power devices using experiments and simulations 1-3. These reports demonstrate that due to its unclamped inductive switching (UIS) capability, SiC does not break down even at a temperature three times as that of Si. However, maximum junction temperature during avalanche mode has not been experimentally analyzed. In this study, we conducted UIS test on SiC MOSFET rated at 1200 V/19 A, and evaluated avalanche energy and maximum junction temperature that the device can withstand under measurement conditions of supply voltage: 400 V, inductance: 1 mH to 10 mH, case temperature T_c: 300 K to 450 K. Here, case temperature T_c pertains to the temperature on backside of MOSFET TO‐type package; the temperature was controlled using a heater attached to the backside. In this study, maximum junction temperature T_max is assumed as the highest temperature inside the semiconductor; we analyzed T_max experimentally, clarified avalanche breakdown mechanism in more detail, and found that UIS capability is dictated by thermal damage to the device.

SiC MOSFET is expected to be employed in power systems as a device with low ON resistance. In this study, we analyzed internal device operation of SiC MOSFET under conditions of UIS breakdown test to clarify the mechanism of SiC MOSFET breakdown. As a result, we found how the element structure should be improved toward higher breakdown performance, which leads to higher reliability of SiC MOSFET. Due to higher reliability, SiC MOSFET can be used in power systems to achieve reduction of power loss, which is supposed to contribute to the Green Innovation in power industry as an energy‐saving technology.

2. UIS Test and Evaluation of Maximum Junction Temperature

2.1 Evaluation of maximum junction temperature

UIS test system and its equivalent circuit are shown in Fig. 1. The equivalent circuit is composed of a power supply V_in, smoothing capacitor C, inductor L, voltage/current probe, and 1200‐V/19‐A SiC MOSFET. When a gate signal higher than threshold voltage is inputted to SiC MOSFET, current from the power supply passes through the inductor, and flows from the drain to the source. At the same time, energy is accumulated in the inductor until a target peak current is reached. After that, when the device turns off, energy accumulated in the inductor is released via drain‐source current; as drain‐source voltage V_ds rises, the device goes into avalanche mode. The energy released from the inductor is obtained as shown below:

(1)

Figure 1

Basic UIS test hardware and equivalent circuit. [Color figure can be viewed at wileyonlinelibrary.com]

Here, t_av is avalanche time, V(t) is breakdown voltage, and I(t) is drain current.

Current and energy (heat release) are important elements of analysis in avalanche mode. Here, we focused on current and heat to experimentally analyze a main cause of breakdown.

First, we measured UIS capability of SiC MOSFET at room temperature. The measurement conditions were––supply voltage: 400 V, inductance: 1 mH, T_c of SiC MOSFET: 300 K. Avalanche energy E_av in UIS test can be also calculated by the following expression:

(2)

Here, E_av is avalanche energy, L is inductance, I is avalanche current, V_break is breakdown voltage, and V_in is supply voltage.

As follows from this expression, V_in must be lower than V_break. In this study, we focus on drain current, and V_in should be set low in order to achieve current close to rated value. However, because of limitations of the measurement system, turn‐on time longer than 300 μs could not be set, and the device could not be destroyed at V_in lower than 400 V. Thus, we set the voltage to 400 V. Drain current and voltage waveforms are shown in Fig. 2. The device failure was confirmed when drain current I_d reached 22.1 A, while turn‐on time was varied form 30 μs to 67 μs (Fig. 2(a)). The drain voltage waveforms in Fig. 2(b) show that the device entered avalanche mode, and V_ds increased above 1600 V. At the same time, energy is consumed by the device via current I_d, and avalanche voltage in the dotted region grows due to the rise of junction temperature. After that, device failure is supposed to occur. These experimental results show that when drain current reaches I_d = 22.1 A at turn‐on time of 67 μs, voltage V_ds grows together with temperature, and the device fails.

Figure 2

Evaluation of UIS capability as function of turn‐on time. [Color figure can be viewed at wileyonlinelibrary.com]

Measured results for temperature dependence of SiC MOSFET breakdown voltage are presented in Fig. 3. The withstand voltage with respect to temperature can be approximated by a straight line. With α denoting gradient of the best‐fit straight line, device's maximum temperature can be determined as follows:

(3)

Figure 3

Breakdown voltage as function of temperature and corresponding fit curve for 1200‐V SiC MOSFET (n = 3).

Here, T_max is maximum junction temperature, and T_c is case temperature, V_max and V_start are maximum voltage and breakdown onset voltage in avalanche mode, respectively; from Fig. 3, α is 0.25 V/K.

From the results of Figs. 2 and 3, we estimated junction temperature at avalanche failure. At turn‐on time of 67 μs when the breakdown occurs, V_max – V_start = ΔV = 156 V is obtained, and T_max = 924 K is determined from Eq. 3.

Next, we examined relationship between avalanche failure and peak current. Results of UIS test performed at room temperature and varied inductance L are shown in Fig. 4. The measurement was performed at L = 1, 5, 10 mH; thus, obtained current waveforms at avalanche failure are shown in Fig. 4(a). As can be seen from the diagram, peak current at breakdown decreases with higher inductance. As indicated by voltage waveforms in Fig. 4(b), variation ΔV of withstand voltage remains unchanged irrespective of inductance (though current values are different here). As can be concluded from the mentioned temperature dependence of breakdown voltage, T_max at failure changes almost not at all with inductance. Therefore, breakdown is caused mainly not by the magnitude of current but by the temperature rise due to heat release.

Figure 4

UIS capability as function of time at different inductance. [Color figure can be viewed at wileyonlinelibrary.com]

Next, we measured case temperature dependence in UIS test. This experiment confirmed whether T_max remains unchanged at different case temperature. In the measurement, peak current was fixed at 22.3 A, while T_c was varied at 300 K to 450 K. The measured results for temperature dependence of UIS breakdown voltage are shown in Fig. 5; thus, we found that the time from avalanche onset through breakdown shortens. This is because the higher is T_c, the lower is energy required to reach the breakdown temperature. As regards drain voltage in Fig. 5(b), the voltage variation ΔV during avalanche decreases with higher T_c. Using this ΔV to calculate T_max at different values of T_c by Eq. 3, the following is obtained: T_max = 924 K at 300 K, T_max = 910 K at 350 K, T_max = 900 K at 400 K, T_max = 890 K at 450 K; that is, the upper and lower temperature limits lie within a range of 3.7%.

Figure 5

UIS evaluation at constant drain peak current. [Color figure can be viewed at wileyonlinelibrary.com]

Evaluated results for minimum breakdown current at varied case temperature are shown in Fig. 6. The minimum breakdown current was defined as the drain current at which breakdown occurred while varying drain current through gradually increasing turn‐on time. As indicated by the drain current waveforms in Fig. 6(a), the minimum breakdown current decreases with higher T_c, namely, being 22.1 A at T_c = 300 K, 21.1 A at 350 K, 20.1 A at 400 K, and 19.5 A at 450 K. Corresponding voltage waveforms are shown in Fig. 6(b); here, absolute value of the voltage variation ΔV during avalanche was almost same as in the experimental results of Fig. 5. In addition, we observed an interesting phenomenon in which breakdown occurs near zero current at T_c = 350 K as shown in Fig. 6(a). This might be attributed to leakage current. Theoretically, thermally induced leakage current follows Eq. 4 2:

(4)

Figure 6

UIS evaluation at alterable drain peak current. [Color figure can be viewed at wileyonlinelibrary.com]

Measured temperature dependence of thermally induced leakage current is shown in Fig. 7. From these results, the following relationship between temperature T and thermally induced leakage current I_leakage is derived:

(5)

Figure 7

Thermal leakage current as a function of temperature (n = 3).

Since Eqs. 4 and 5 offer similar temperature dependences, one can assume that thermally induced leakage current as defined in Eq. 5 flows immediately before the breakdown. This leakage current may be responsible for device failure. Therefore, one can say that heat is an important factor that determines breakdown.

Approximating curves for the measured results of Figs. 5 and 6 are shown in Fig. 8. Specifically, we plotted temperature dependencies of minimum breakdown current I_peak and avalanche energy E_max of breakdown in SiC MOSFET to estimate T_max at breakdown; in so doing, we compared reliability of estimating T_max from energy and from current. T_max at breakdown was defined as the temperature at which approximating curves of E_max and I_peak become zero; thus, we obtained 940 K and 1551 K, respectively. The value of T_max estimated from I_peak greatly deviates from the calculated results in Figs. 2 to 4. This is because of the difference in current components. Specifically, I_peak pertains only to current component that flows into MOSFET via inductor L, while thermally induced leakage current, discharging current of drain‐source parasitic capacitance and so on are not included. In other words, analysis results based on I_peak in Fig. 8 disregard the effect of heat, being assumed as the main cause of breakdown; as a result, reliability of T_max estimation is likely to be low. Thus, from the results for E_max based on Figs. 2 to 4 as well as Figs. 5 and 6, T_max of breakdown can be assumed in a temperature range of 890 K to 940 K.

Figure 8

Peak current and avalanche energy as functions of temperature. [Color figure can be viewed at wileyonlinelibrary.com]

3. Breakdown Mechanism

3.1 Identification of breakdown causes

We simulated UIS tests to identify the causes of breakdown. By combining two‐dimensional device simulation with circuit simulation, we analyzed heat release and breakdown mechanism in avalanche mode of UIS test circuit. In so doing, SiC MOSFET was assumed as 1600‐V device with drift layer thickness of 10 μm and doping concentration of 5.0 × 10¹⁵ cm⁻³, the active area was set same as in the measured device for the purpose of comparability. In simulations, a system of three equations––Poisson equation, current continuity equation, and nonlinear heat equation––was solved.

Results of UIS test simulations at a temperature close to assumed maximum junction temperature of SiC MOSFET failure are presented in Fig. 9. The diagrams (a) to (d) show distributions of various parameters in avalanche mode at maximum temperature inside the device about 953 K. In the electric field distribution in Fig. 9(a), electric field about 3.0 MV/cm is applied to pn‐junction due to avalanche mode. Figures 9(b), 9(c), and 9(d) pertain, respectively, to current density distribution, electron current density distribution, and hole current density distribution. As can be seen from Fig. 9(b), current flows in the channel and in p‐well layer just beneath n+ source layer. Figure 9(c) indicates that current flows due to MOSFET operation, while Fig. 9(d) indicates that holes produced due to avalanche in pn‐junction pass through p‐well layer to reach source electrode so that hole current flows. This hole current passes through p‐well layer resistance R_b just beneath n+ source layer, thus causing turn‐on of parasitic BJT. The resistance R_b can be expressed as follows 5:

(6)

Figure 9

Current density distribution during avalanche failure time at T_max = 953 K. [Color figure can be viewed at wileyonlinelibrary.com]

Here, μ_po is hole mobility at room temperature, T₀ is room temperature, q is elementary charge, N_p is doping concentration of p‐well layer, and A is a constant.

Parasitic BJT turns on when R_b grows as temperature is increased, and base‐emitter potential difference in parasitic BJT exceeds diffusion potential difference. However, the simulation results suggest that parasitic BJT is not fully turned on. Temperature dependence of intrinsic carrier density is as shown below 2:

(7)

Here, n_i is intrinsic carrier density, and T is temperature.

From the above expression, intrinsic carrier density at 953 K is n_i = 1.66 × 10¹¹ cm⁻³, which is extremely low as compared to the doping concentration of 5.0 × 10¹⁵ cm⁻³ in drift layer. Therefore, increase in carriers with temperature rise in SiC MOSFET does not result in thermal runaway.

The above simulation results show that the cause of breakdown is other than turn‐on of parasitic BJT or thermal runaway due to temperature rise.

Next, we analyzed real device failure. Measured post‐breakdown resistance between electrodes was R_gs = 0.3 Ω (gate‐source), R_gd = 0.5 Ω (gate‐drain), and R_ds = 0.2 Ω (drain‐source). Thus, all the resistances between electrodes were close to zero, and one can think that pn‐junction and gate oxide film broke down during turn‐off. A photograph of destroyed SiC MOSFET surface is shown in Fig. 10; as can be seen from the photograph, aluminum electrode on the surface of source electrode has melted, and a black breakdown mark can be observed near the bonding wire. The temperature T_max of 890 K to 940 K estimated from the experimental data is of the same order as the melting point 933 K of aluminum electrode 4, and the meltdown of aluminum electrode can be assumed as the main cause of device breakdown. In the simulation results shown in Fig. 9, BJT is not turned on fully, and thermal runaway does not occur at the temperature of 953 K; hence, one can assume that the real device fails prior to thermal runaway when maximum junction temperature T_max has reached the aluminum melting point of 933 K.

Figure 10

Breaking point of SiC MOSFET and its enlarged image. [Color figure can be viewed at wileyonlinelibrary.com]

4. Conclusions

In this study, we analyzed, via experiments and simulations based on UIS test, maximum junction temperature and avalanche breakdown mechanism in 1200‐V/19‐A SiC MOSFET. The main results are summarized below:

1. We estimated maximum junction temperature in SiC MOSFET under UIS test. Using temperature dependence of withstand voltage, we focused our evaluation on heat and breakdown current measured at varied case temperature T_c and inductance. As a result of analysis, we estimated that maximum junction temperature T_max at breakdown lies within a range of 890 K to 940 K.

2. In simulation‐based analysis of SiC MOSFET, parasitic BJT does not work in full around 950 K, while intrinsic carrier density does not increase with temperature rise so high as to cause thermal runaway; that is, one can assume that avalanche failure is not due to heavy current of parasitic BJT. Thus, the main cause of avalanche breakdown is likely to be melting of aluminum electrode that occurs as maximum junction temperature T_max approaches the melting point 933 K of aluminum.

The above results of experiments and simulations suggest that SiC MOSFET can withstand temperature above 890 K; in addition, UIS capability of SiC MOSFET is more than twice as high as that of Si IGBT 6, and therefore, SiC MOSFET is a promising next‐generation device usable in electric power systems.

5. Afterword

According to results of this study, one can expect that in a few years SiC MOSFET will become a mainstream device in industrial equipment. Presently, primary components of power electronics in medium‐to‐high voltage range are Si IGBTs. As a result of estimation of junction temperature and UIS capability in this study, we clarified mechanism of SiC MOSFET breakdown in OFF state due to avalanche mode, and determined maximum junction temperature that the device can withstand. Particularly, we found that SiC can operate even at an extremely high junction temperature above 890 K, thus proving excellent turn‐off thermal reliability of SiC MOSFET. Being advantageous in terms of operation at high voltage and current as well as high temperature, SiC MOSFET is likely to become an indispensable device for the Green Innovation (energy‐saving technology) in a few years.

Biographies

• 

  Junjie An, nonmember. In 2013, An completed postgraduate studies at University of Electronic Science and Technology of China (School of Electronic Engineering) and in 2015, he started second term of doctorate at University of Tsukuba. He is involved with research in breakdown strength of SiC devices and simulation of power devices.

• 

  Masaki Namai, nonmember. In 2016, Namai graduated from University of Tsukuba (School of Science and Engineering) and in 2016, he started first term of doctorate at the University. He is involved with research in breakdown strength of SiC devices.

• 

  Dai Okamoto, nonmember. In 2011, Okamoto completed doctorate at Nara Institute of Science and Technology. He is a Doctor of Engineering. In 2011, he was employed by AIST Advanced Power Electronics Research Center and since 2015, he has been an assistant professor at University of Tsukuba (Pure and Applied Science). He is involved with the development of SiC thermal oxidation processes and research in SiC power devices.

• 

  Hiroshi Yano, nonmember. In 2001, Yano completed doctorate at Kyoto University (Graduate School of Engineering). He is a Doctor of Engineering. In 2001, he was employed as assistant by Nara Institute of Science and Technology (Graduate School of Materials Science), in 2007 he became an assistant professor, and in 2013 he became an adjunct professor at University of Tsukuba. He is involved with research in SiC MOS interface and devices.

• 

  Hiroshi Tadano, member. In 1980, Tadano completed postgraduate studies at Tohoku University (Graduate School of Engineering). He is a Doctor of Engineering. In 1980, he was employed by Toyota Central R&D Labs. He is involved with research in static induction transistors, Si‐IGBT, Si diodes, SiC devices, and GaN devices. Since 2013, he has been a professor at University of Tsukuba (Pure and Applied Science). He is involved with research in power converters using novel power devices. He has a membership of IEEE, IEEJ, IEICE, JIPS, JIEP, and JSAE.

• 

  Noriyuki Iwamuro, senior member. In 1984, Iwamuro graduated from Waseda University (Faculty of Science and Technology, Electrical Engineering). From 1992 to 1993, he was a visiting researcher at PSRC, North Carolina State University. In 1998, he became a Doctor of Engineering (Waseda University). In 1984, he was employed by Fuji Electric. Since 1988, he has been involved in R&D and production of silicon and SiC power semiconductor devices. In 2009, he joined National Institute of Advanced Industrial Science and Technology (AIST). Since 2013, he has been a professor at University of Tsukuba (Pure and Applied Science). He has a membership of IEEE (senior member) and JSAP.