Memristive Synapses for Brain-Inspired Computing

Although the structure and function of the human brain are still far from being fully understood, brain‐inspired computing architectures mainly consisting of artificial neurons and artificial synapses have been attracting more and more attentions due to their powerful computing capability and energy efficient operation. Synaptic plasticity is believed to be the origin of learning and memory. However, it is still a big challenge to realize artificial synapses with high reliability, good scalability, and low energy consumption, comparable to their biological counterparts. The memristor is a two‐terminal electronic device whose conductance can be reversibly regulated by electric stimuli. Memristive devices are considered ideal synaptic emulators due to their superior performance such as high speed and low power operation. This work reviews the recent advances in the development of memristive synapses based on different types of memristors. First, various working mechanisms of memristive synapses are discussed and compared. Then, different integration approaches of synaptic devices are described and compared. Various cognitive functions implemented with synaptic crossbar circuits are also described. Finally, the approaches for optimizing the performance parameters of memristive synapses and challenges to integrate the synaptic devices with complementary metal oxide semiconductor (CMOS) or memristive neurons are overviewed and discussed briefly.


Introduction
The human brain is far superior to modern computers in performing complicated computing tasks such as learning and cognition due to its ultralow power consumption and highly parallel computation. [1] For the brain, learning and memory are believed to be implemented by adjusting the weight of synapses linking two adjust neurons. [2] The synaptic weight can I-V plane (i.e., resistive or memristive switching). [9] The memristance (or resistance) of a memristor shows a nonlinear variation with the amount of charge flowing through it, which is retained after stopping electrical stimulation. It follows that the memristance can be reversibly adjusted by voltage or current pulses, and therefore multilevel conductance states can be realized in a memristor. These conductance states can be employed to emulate synaptic weights. Memristive devices are considered ideal for artificial synapse applications due to their superior performance such as high scalability and low power consumption. [6] In this review, we discuss the recent advances in the development of memristive synapses, mainly focusing on their working mechanisms, integration, and cognitive functions. The device performance improvement techniques as well as the challenges of integrating memristive synapses with artificial neurons are also briefly discussed.

Metal Ion Migration
Lu and co-workers developed a two-terminal memristive synapse in 2010 based on a Si/Ag composite film. [10] The biological synapse varies its weight by the release of neurotransmitters from the preneuron induced by action potentials (spikes); similarly, the memristive synapse varies its conductance by the metal ion migration upon external electrical stimuli. As schematically shown in the top inset of Figure 1a, a properly designed Ag/ Si ratio gradient results in the formation of a Ag-rich region and a Ag-poor region, which show relatively low resistivity and relatively high resistivity, respectively. Under positive bias, the Ag-rich region gradually extends due to Ag ion migration along the electric field direction, thus leading to an analog high-resistance-state (HRS or OFF-state)-to-low-resistance-state (LRS or ON-state) switching process (SET, see the left panel of Figure 1b). Under negative bias, the Ag-poor region gradually extends, thus resulting in an analog LRS-to-HRS switching process (RESET, see the right panel of Figure 1b). Then, the device resistance (or conductance) can be incrementally increased by the application of positive voltage pulses, and the resistance (or conductance) can be incrementally decreased by the application of negative voltage pulses, as shown in Figure 1c. It indicates that both types of synaptic plasticity, potentiation and depression, are emulated in such a memristive device with metal ion migration as its working mechanism. Furthermore, this memristive synapse can also emulate complex synaptic functions such as spike-timing-dependent plasticity (STDP), an important Hebbian learning rule that demands the variation of synaptic weight to be a strong function of the pre/postneuron spike timing (see Figure 1d). Afterward, memristive synapses with the same working mechanism have been realized based on Ag/ Ge 30 Se 70 , [11] Ag/InSbTe, [12,13] Cu/SiO 2 , [14] Ag/polyurethane, [15] and Ag/TiO 2 composite thin films. [16] Furthermore, a similar mechanism most likely plays a role in Ag 2 S-and Li x CoO 2based memristive synapses given that these materials contain movable Ag and Li ions. [17,18] However, till now, nobody can provide direct or even indirect evidence for the uniform movement of the metal-rich or metal-poor region in the movable metal ion-or metal cluster-containing systems. On the contrary, localized metallic conducting paths have been clearly observed in a Ag/SiO x N y composite film under electrical bias (see Figure 2). [19] Therefore, although movable metal ions or metal clusters are uniformly distributed in the semiconducting or insulating matrix for a memristive synapse, the HRS-to-LRS (or LRS-to-HRS) switching likely originates from the formation (or rupture) of localized conducting filaments composed of metal atoms instead of uniform extension of the metal-rich (or metal-poor) region due to environmental perturbations such as irregular surface morphology of electrodes and nonuniformly distributed electric field. Generally, there is only a single complete metal filament for the device in LRS (see Figure 3). [20] The origin of multilevel switching may be direct tunneling between the growing or rupturing filament and the electrode. [21] According to the working mechanism discussed above, another type of memristive synapses has also been developed. The difference is that the semiconducting or insulating switching layer does not contain movable metal ions or metal clusters; movable metal ions come from the redox reaction at the active electrode/switching layer interface upon electrical bias. The active electrode material is always Cu or Ag, and the Jingrui Wang received her Ph.D. degree in materials science from Zhejiang University, Hangzhou, China, in 2008. Since 2014, she has been an assistant professor in the School of Electronic and Information Engineering, Ningbo University of Technology. Her current research interests focus on memristive materials and devices and brain-inspired computing. Figure 1. Si/Ag composite film-based memristive synapse. a) Schematic illustration of the concept of utilizing memristors as synapses connecting two neurons. The left and right insets display the schematics of the device geometry and structure of the memristor, respectively. b) Measured (blue) and calculated (orange) I-V curves of the device. The inset shows the extracted (blue) and calculated (orange) values of the normalized Ag front position (w) during positive bias sweeps. c) Potentiation (P) and depression (D) processes of the device by positive and negative voltage pulses, respectively. d) STDP learning rule emulated with the memristive synapse. The inset shows the scanning electron microscope (SEM) image of the memristor crossbar structure. The scale bar is 300 nm. All panels reproduced with permission. [10] Copyright 2010, American Chemical Society.

Figure 2.
In situ transmission electron microscopy (TEM) observation of the threshold switching process of the Ag/SiO x N y composite film-based memristive device. All scale bars are 20 nm. Reproduced with permission. [19] Copyright 2016, Springer Nature. www.advmattechnol.de switching layer can be Ta 2 O 5 , [22] ZnO, [23] HfO 2 , [24] WO 3−x , [25] ZnS, [26] GeSe, [27] SiGe, [28] amorphous silicon, [29,30] amorphous carbon, [31] polymer, [32] and silk fibroin. [33] It has been found that lightly oxidized ZnS films present highly controllable memristive switching and synaptic performance, originating from a two-layer structure of ZnS thin films, i.e., the lightly oxidized layer and unoxidized layer. [26] The metal filament rupture/ rejuvenation is likely confined to the two-layer interface region with a thickness of several nanometers due to different metal ion transport rates in these two layers (see Figure 4). Another technique for improving the reliability and stability of the device performance is utilizing threading dislocations in a single-crystalline SiGe layer. [28] In this case, metal filaments can be confined in a defined, 1D channel.

Oxygen Vacancy/Ion Migration
Yu et al. fabricated a memristive synapse based on a HfO x /AlO x bilayer structure in 2011. [34] The memristive synapse varies its conductance due to the oxygen vacancies/ions migration upon external electrical stimuli (see Figure 5a), similar to the case of the biological synapse. The gradual SET and RESET processes can be realized by consecutively increasing the SET compliance and amplitude of the RESET stop voltage, respectively, as shown in Figure 5b. At a larger SET compliance, stronger or more conducting filaments composed of oxygen vacancies will form, thus resulting in the gradual SET. [35] A higher amplitude of the RESET stop voltage will lead to shorter residual conducting filaments or less filaments, which may be the origin of the gradual RESET. [36] Then, the synaptic potentiation and depression, and STDP learning rule can be implemented in such a device, as shown in Figure 5c,d.
Furthermore, a trilayer structure of TiO x /HfO x /TiO x has been developed to reduce the power of memristive synapses. [54] Figure 7a presents the I-V curves of the TiO x single-layer, HfO x /TiO x bilayer, and TiO x /HfO x /TiO x trilayer structures. For the single-layer devices (see the top panel of Figure 7a), the operation currents are high for both SET/ RESET processes. In addition, the memristive switching performance degrades upon repeated cycling. It may originate from the presence of a large amount of oxygen vacancies in TiO x . These devices operate somewhat like a resistor. The memristive switching likely originates from the migration of a small amount of oxygen vacancies (see the left panel of Figure 7b). In the case of the bilayer devices (see the middle panel of Figure 7a), the operation currents decrease by approximately four orders of magnitude. Furthermore, the devices present an improved switching stability upon repeated cycling. Compared to the HfO x single-layer devices, the bilayer ones present lower operation currents and higher ON/OFF ratio. For the HfO x /TiO x structures, the memristive switching may occur in the HfO x layer while the TiO x layer behaves like a resistor (see the middle panel of Figure 7b). Given that the energy levels of oxygen vacancies in TiO x are ≈0.3 eV below the conduction band edge much shallower than that in HfO x (≈0.9 eV), [55,56] the difference of the oxygen vacancy energy levels may be the reason for the low operation currents. As expected, the trilayer configuration leads to even lower operation currents and higher ON/OFF ratio due to the presence of two TiO x resistors (see the bottom panel of Figure 7a and right panel of Figure 7b). Although all these three structures can emulate the synaptic potentiation and depression, the conductance variation for the bilayer and trilayer devices presents much higher symmetry and linearity compared to that for the single layer ones, as shown in Figure 7c.
Interestingly, a four-layer structure of HfO x /TiO x /HfO x / TiO x has been fabricated for memristive synapse applications. [57] However, no obvious advantage can be found over  The Cu top electrode was removed before the measurement. A low voltage of 50 mV was utilized. All panels reproduced with permission. [20] Copyright 2015, The Authors, published by American Institute of Physics.
It is worth noting that, the working mechanism of oxide memristive devices may be much more complicated than we thought. By combining scanning tunneling microscopy and potentiodynamic I-V measurements, Valov and co-workers found that in 2 nm thick TaO x , HfO x , and TiO x films, the host  RESET process. f,g) SET process. h) RESET process. All panels reproduced with permission. [26] Copyright 2017, Wiley-VCH. metal ions are mobile. [110] They can form metallic filaments and play a role in the memristive switching. Therefore, to precisely understand the working mechanism of oxide memristive synapses, the migration of both oxygen vacancies/ions and host metal ions should be taken into account.

Charge Trapping/Detrapping
Zhuge and co-workers developed a purely electronic memristive synapse based on a Ti/ZnO structure in 2016. [111] Figure 8a shows the nonlinear I-V curves of the device. Linear fitting Figure 5. Memristive synapse based on the HfO x /AlO x bilayer structure. a) Similarity between the biological synapse and the memristive synapse. b) I-V characteristics of the device measured by a modified voltage sweep. c) Potentiation and depression cycles of the device by positive and negative voltage pulses, respectively. d) STDP learning rule mimicked by the memristive synapse. The inset schematically shows the spike scheme. All panels reproduced with permission. [34] Copyright 2011, IEEE.

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results of the double-logarithmically plotted I-V curves suggest that the charge transport in both LRS and HRS is governed by the trap-controlled space charge limited conduction mechanism. [112] The memristive switching can be attributed to a carrier trapping/detrapping in ZnO films. Figure 8b presents strong evidences for the homogeneous memristive switching behavior. First, the resistance of both LRS and HRS decreases strongly with temperature, showing a typical semiconducting behavior. Second, the device presents a strong device size dependence of the resistance in both LRS and HRS. Third, the ratio of the resistance of the half device to the resistance of the whole device is about two for both LRS and HRS. Forth, the device in LRS exhibits a uniform current distribution. Figure 8c,d illustrates the synaptic potentiation/depression and STDP learning rule emulated in such purely electronic devices. It is believed that oxygen vacancies and zinc interstitials are the most important intrinsic donor defects in ZnO. The energy levels of oxygen vacancies are much deeper than those of zinc interstitials. [113,114] It can be inferred that the injected electrons are first trapped by oxygen vacancies and then by zinc interstitials. During the detrapping process, the electrons trapped by zinc interstitials are first detrapped by a reverse electric field (see Figure 8e). [115] Memristive synapses with a similar working mechanism have been realized based on Cu-doped MoO x /GdO x , [116] Ge 2 Sb 2 Te 5 , [117] Nb 2 O 5 , [118] Bi 2 S 3 , [119] HfO 2 /Al 2 O 3 /Si 3 N 4 , [120] CeO 2 , [121] and CuPc/LiF. [122] An organic memristive synapse based on PEDOT:PSS/graphene quantum dot composite films has also been fabricated. [123] The memristive switching originates from the trapping and detrapping of electrons from the graphene quantum dots (see Figure 9).
Memristive synapses based on ion migration generally show noticeable device performance variations upon repeated cycling of potentiation and depression. It comes from an inevitable change of microstructure induced by ion migration. These performance variations are unfavorable for practical applications of memristive synapses. Given that no microstructure change occurs for the devices based on carrier trapping and detrapping, such purely electronic memristive synapses are preferable over the ionic devices due to their potentially better reliability. [124]

Proton Intercalation
Shang and co-workers developed a solid state electrochemical memristive synapse based on MoO x thin film in 2017. [125] The operation mechanism of the device is attributed to the interfacial electrochemical reaction of the MoO x film with the adsorbed water. Under an electric field, the decomposition of water produces protons, which diffuse into the MoO x film  www.advmattechnol.de and intercalate into the oxide lattice, leading to the synaptic plasticity.

Spin-Torque Effect
A magnetic tunnel junction consists of two thin film metallic megnets separated by an insulating layer (typically MgO), which is thin enough for electrons to tunnel between these two magnetic layers (see Figure 10a). [126][127][128][129][130][131] By changing the relative magnetization alignment of the magnetic layers, the junction current is composed of spin-up and spin-down electrons. Given that spin-up and spin-down electrons interact differently with the counter megnet, HRS and LRS can be obtained for the antiparallel alignment and parallel alignment, respectively. This   [111] Copyright 2016, American Institute of Physics. (e) Reproduced with permission. [115] Copyright 2016, American Institute of Physics.

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phenomenon is referred as the tunnel magnetoresistance effect. On the contrary, the megnetization direction of a megnet can also be changed by the angular momentum of the spin-polarized electrons at a high current. This phenomenon is known as the spin-transfer torque effect, which allows for magnetic tunnel junctions to act as current-driven memristive devices. [130,131] Adv. Mater. Technol. 2019, 4, 1800544    [131] However, the synaptic plasticity comes from a resistance change induced by a voltage-driven oxygen ion/ vacancy migration in the MgO layer. Lequeux et al. developed a spintronic memristive synapse based on a spintorque memristor in 2016. [132] As shown in Figure 10b, the memristor is a magnetic tunnel junction consisting of an anti-ferromagnetic layer (CoPt/Ru/CoPt/Ta/FeB), a tunnel barrier (MgO), a magnetic free layer (FeB/Ta/FeB), and a capping layer (MgO/Ta). There is a single magnetic domain wall in the free layer. The memristive switching originates from the displacement of the domain wall by spin-torques. By applying positive or negative voltages to the two-terminal junction, the magnetic domain wall can be displaced back and forth. After removing the voltage, the domain wall will stabilize in various pinning sites (see Figure 10c). Given the tunnel magnetoresistance effect, each domain wall position will exhibit a different resistance value. Besides two-terminal memristive magnetic tunnel junctions, synaptic or neuromorphic computing functions have also been mimicked in spin-torque nanodevices acting as binary memories or oscillators with two-, three-or four-terminal structures. [126,127,[133][134][135][136][137][138][139][140][141][142]

Ferroelectric Polarization Switching
A ferroelectric tunnel junction comprises of a few-unitcell-thick ferroelectric film sandwiched between two electrodes. [143,144] The ferroelectric polarization can be switched by applying an electric field across the ferroelectric thin film. It results in two logic states with polarization pointing either up or down. The ferroelectric polarization switching will induce a large change in the tunnel resistance. [145] Boyn et al. developed a ferroelectric synapse based on a ferroelectric tunnel memristor. [146] The conductance variations are governed by nucleation-limited ferroelectric domain switching. As sketched in Figure 11a, the memristor is composed of a ferroelectric tunnel junction of Co/BiFeO 3 (BFO)/(Ca,Ce)MnO 3 (CCMO). The junction resistance varies with the relative fraction of ferroelectric domains with polarization pointing toward the top or bottom electrode. [147] The domain population can be changed by applying voltage pulses to the junction. Then, the resistance can be modified by voltage pulses (see Figure 11b). Furthermore, we see from Figure 11b that there exist two voltage thresholds, V th + and V th − , which are associated with the coercivity of the ferroelectric. Thanks to the existence of such voltage thresholds, the STDP learning rule can be emulated in these ferroelectric tunnel junctions (see Figure 11c). Synaptic functions have also been implemented in ferroelectric    [148,149] In addition, three-terminal ferroelectric synapses have also been developed by using Pb(Zr,Ti)O 3 and Hf 0.5 Zr 0.5 O 2 based ferroelectric tunnel junctions. [150,151]

Phase Transition
A phase change memristor consists of a phase change material layer sandwiched between two metal electrodes. [152][153][154][155] By applying electric pulses to the device, the phase change material shows a unique resistive switching behavior between amorphous and crystalline states. The amorphous state has a relatively high resistivity while the crystalline state has a relatively low resistivity. Chalcogenide glass, more specifically Ge 2 Sb 2 Te 5 , is one of the technologically mature phase change materials used for optical data storage and nonvolatile memory. Wong and co-workers developed an artificial synapse based on Ge 2 Sb 2 Te 5 phase change memristor in 2011. [152] Continuous resistance transitions obtained in the device enable the implementation of synaptic learning rules. Different forms of STDP can be emulated in such memristive synapses.

Integration and Cognitive Functions of Memristive Synapses
A memristive synapse is a two-terminal device thus allowing for crossbar circuit integration and aggressive size scaling, which are important for the practical implementation of large-scale artificial neural networks. [6] As illustrated in Figure 12, a memristor crossbar array is composed of a set of parallel bottom electrodes and a set of perpendicular top electrodes with memristive switching material sandwiched between top and bottom electrodes. [156] Each crosspoint represents a synaptic device. However, the existence of sneak paths is an inherent disadvantage of crossbar arrays. For example, as schematically shown in Figure 12, the addressed element is in a relatively low conductance state (red), while all other elements are in relatively high conductance states (green). When reading, a current will flow through the addressed element (I element ). However, a significant current will also flow through the adjacent elements (I sneak ). It is impossible to distinguish between both currents. Thus, the conductance state of the addressed element cannot be correctly obtained. Moreover, the current and voltage drop over the addressed element depend on the current flowing through sneak paths. Then the size of a crossbar array (maximum numbers of rows and columns) will be limited by the sneak paths. [157] Till now, three approaches have been employed to address the sneak path problem: i) nonlinear switching characteristics of memristive synapses, ii) self-rectifying behavior of synaptic devices, and iii) using a transistor at each crosspoint (1T1M).

Nonlinear Memristive Switching
Strukov and co-workers fabricated a 2 × 10 crossbar circuit using TiO x -based memristive synapses in 2013. [6] The nonlinear I-V characteristics of synaptic devices are utilized to solve the sneak path problem. Pattern classification can be implemented by such crossbar circuits using ex situ and in situ training. However, due to significant variations in the memristive switching behavior, each device is disconnected from the crossbar for individual electroforming with external wires. To overcome this problem, a 12 × 12 memristive crossbar with TiO x /AlO x -based synaptic devices has been developed. [158] Figure 13a,b shows the corresponding crossbar structure and typical I-V characteristics of an electroformed memristive device. Figure 13c illustrates the absolute values of device conductance variation upon different voltage pulses as a function of the initial conductance. The devices show high nonlinearity of the I-V curves (with the current at the SET/RESET voltage more than ten times the current at half of the SET/RESET voltage), low electroforming/SET/ RESET voltages, and a low variability in the switching behavior. The good uniformity of pristine synaptic devices is important for the implementation of a convenient electroforming process. The memristive crossbar is employed to construct a simple artificial neural network with ten inputs and three outputs, which are connected with thirty synapses. Such a circuit is used to perform the classification of 3 × 3 pixel black-and-white images into three classes with nine inputs corresponding to the pixel values. The network is tested on a set of thirty patterns, consisting of three stylized letters and three sets of nine noisy versions of each letter. Each input signal is represented by a voltage of +0.1 V or −0.1 V corresponding to the black or white Adv. Mater. Technol. 2019, 4, 1800544   Figure 12. Memristive crossbar array and sneak path problem. Reproduced with permission. [156] Copyright 2010, Springer Nature. www.advancedsciencenews.com www.advmattechnol.de pixel, respectively. The bias input is fixed at −0.1 V. This way of coding makes the benchmark input set balanced. In order to sustain such balance at the output, each synapse is composed of two memristors (see Figure 13d). Differential current output signal can be obtained according to Ohm's law. The network is trained in situ using a coarse-grain variety of the delta rule algorithm. An example of the classification operation for the stylized letter "z" is shown in Figure 13e. The synaptic weights are adjusted in parallel for each column of the crossbar following the Manhattan update rule (see Figure 13f). When the devices are initialized somewhere in the middle of their conductance range, the best classification performance can be Adv. Mater. Technol. 2019, 4, 1800544   Figure 13. Crossbar array with TiO x /AlO x -based memristive synapses and its pattern classification function. a) Memristive crossbar structure. b) Typical I-V characteristics of an electroformed device. The inset schematically shows the device structure. c) Absolute values of device conductance variation upon different voltage pulses as a function of the initial conductance. d) Schematic structure of a single-layer artificial neural network using a 10 × 6 fragment of the crossbar. e) Classification operation for the stylized letter "z." The input signals are equal to +V R or − V R , corresponding to the black or white pixel. f ) Synaptic weight adjustment in the first positive column. Only the memristive synapses whose weights should be increased, i.e., marked by "+" in the table on the left, are adjusted. g) Convergence of network outputs to zero for six training runs from different pristine states. The inset illustrates the distribution of synaptic weights (W) in the pristine state and immediately after epoch 21. h) Output signal evolution of the network. The signals are averaged over all patterns of a specific class. The classification is considered successful when the output signal (f) of the correct class of the applied pattern is larger than other outputs. All panels reproduced with permission. [158] Copyright 2015, Springer Nature.
Lu and co-workers developed a 32 × 32 crossbar array of WO x -based memristive synapses, as shown in Figure 14a. [159] The typical I-V characteristics of the devices are illustrated in Figure 14b, [160] demonstrating a highly nonlinear memristive switching behavior. The crossbar array-based artificial neural network is used to implement sparse coding algorithms, which are believed to be a key mechanism by which biological neural systems can handle a large amount of complex sensory data while very little power is required. The reconstruction of natural grayscale images is successfully performed using a 16 × 32 sub-array by the sparse coding algorithm. The dictionary elements are trained offline and then programmed into the array. As shown in Figure 14c-e, the image is divided into 4 × 4 patches, and then based on the sparse coding algorithm, each patch is handled using the memristive crossbar. The artificial neural network can stabilize after about eighty forwardbackward iterations (see Figure 14f). Finally, the reconstructed image is realized by integrating the individual reconstructed patches (see Figure 14g).
Besides the single-layer artificial neural networks discussed above, a bilayer network composed of two crossbars of Al 2 O 3 / TiO x -based memristive devices with a nonlinear switching behavior has been implemented (see Figure 15). [161] This work is an important step toward the construction of multilayer artificial neural networks. In addition to 2D crossbar arrays of memristive synapses, a monolithically integrated 3D crossbar structure of Al 2 O 3 /TiO x -based nonlinear synaptic devices has also been developed. [162] 3D integration of memristors is necessary for the construction of ultrahigh density artificial neural networks.

Self-Rectifying Memristive Switching
Zeng et al. fabricated a Ag/polymer-based memristive synapse showing a clear self-rectifying switching behavior in 2013 (see Figure 16a). [32] This rectification phenomenon is similar to the unidirectional information conduction of biological chemical synapses. In 2016, Emelyanov et al. realized a bilayer artificial neural network based on polyaniline memristive synapses with a strong rectification characteristic  [159] Copyright 2017, Springer Nature. (b) Reproduced with permission. [160] Copyright 2011, Springer-Verlag.
www.advmattechnol.de (see Figure 16b). [163] Utilizing NbO x /Al 2 O 3 -based self-rectifying devices (see Figure 16c), a 16 × 16 memristor crossbar array has been fabricated for the emulation of Hebbian learning. [51] As illustrated in Figure 16d, the crossbar array is connected to a custom printed circuit board holder through wire bonds. Each device can be addressed through different sets of analogue switches. During the operation, all devices are left floating except for the addressed one. In addition, a 3D artificial synapse network has also been constructed using Cu-doped poly(methylsilsesquioxane)-based self-rectifying synaptic devices. [164]

1T1M Configuration
A one-transistor-one-memristor architecture has been adopted for the integration of memristive synapses with neither nonlinear nor rectifying behavior. Figure 17 illustrates the 1T1M configuration and the integration process for the 1T1M synaptic device array. [165] Front-end-of-the-line complementary metal oxide semiconductor (CMOS) transistors and corresponding wiring form the base structure. Then individual memristive devices can be precisely accessed during the programming process. The memristive device layer is integrated on top of the CMOS through a foundry-compatible back-end-of-the-line process. In the 1T1M structure, rows and columns share bottom electrode lines and top electrode/transistor gate lines, respectively. The lines are isolated by the interlayer dielectric.
A 2T1M structured synapse has also been proposed. [174,175] This architecture allows for a detailed control of both potentiation and depression via current-controlled SET and voltagecontrolled RESET processes, respectively. Furthermore, the existence of two transistors makes it possible to discriminate between the two functions of the synapse. Spikes are transmitted through normal information processing in the neural  www.advmattechnol.de network, and the synaptic plasticity is implemented by the learning process. [1]

Summary and Outlook
Brain-inspired computing architectures composed of memristive neurons and memristive synapses provide a promising scheme for hardware implementation of artificial intelligence with highly efficient information processing and ultralow power consumption. Although great progress has been made in developing memristive synapses and corresponding artificial neural networks in the last decade, the techniques are still far from practical applications. The working mechanisms of most memristive synapses are based on metal or oxygen ion migration, which generally leads to stochastic formation/rupture of nanoscale conducting filaments. It will inevitably induce large device-to-device and cycle-to-cycle performance variations, which is a key obstacle to implement large scale artificial neural networks. In this perspective, purely electronic memristive synapses based on carrier trapping/detrapping, spin-torque effect, or ferroelectric polarization switching may be a promising candidate due to their potentially better reliability, since no microstructure change occurs during the operation. In addition, the existence of the sneak path problem in memristive crossbar arrays severely restricts the size of arrays (maximum number of rows and columns). Actually, simple cognitive functions such as associative learning and pattern recognition can be emulated with small memristor crossbars even if disregarding the sneak path problem. [74,97,[176][177][178][179][180][181][182] However, such a problem will become rather serious for large scale crossbar arrays. Although the 1T1M configuration can effectively address the sneak path problem, the additional three-terminal transistors will significantly increase the circuit complexity and then affect the integration density of crossbar arrays. Then memristive synapses showing nonlinear or self-rectifying switching behavior are preferable for the construction of large scale crossbar arrays. In this case, a high nonlinearity or rectification ratio is needed.
For fast and efficient learning, it is important that the synapse conductance presents a high linearity and a high symmetry of  update. Namely, a fixed pulse induces a known potentiation/ depression by an additive or multiplicative term and similar update characteristics can be obtained under potentiation and depression bias. [1] However, memristive synapses generally present strongly nonlinear and asymmetric weight update. The following techniques may be used to address this problem: i) employing multiple devices with fewer resistance levels to represent each weight such as binary memristive devices; [183] ii) adopting two-memristor synapse in which the two memristors act as excitatory and inhibitory synapses to control the weight update in both directions; [184,185] iii) using voltage pulses with linearly increasing amplitude; [80] iv) utilizing onetransistor/two-memristor (1T2M) structured synapses; [81] and v) optimizing the applied voltages and pulse widths. [5] By delicately modifying the amplitude and width of the voltage pulses, the conductance of memristive synapses can also be precisely tuned. [5] In addition, a high ON/OFF ratio of memristive devices ensures large read margins between multiple resistance levels, which can counteract the defect-related resistance fluctuations and noise. [1,[186][187][188] It is important for the realization of stable multiple resistance states.
Although hardware artificial neural networks based on various memristive synapses have been successfully constructed, the neuronal functions are implemented either by CMOS circuits or in software running on the processors. [6,86,158,159,[161][162][163][164][165][166][167][168][169][170][171][172] It severely limits further improvements on scalability, stackability, and energy efficiency of the networks. [173] The very recent work (by Yang and co-workers) on a fully memristive neural network implemented using diffusive memristors as artificial neurons and 1T1M devices as artificial synapses is an important milestone toward realization of extremely energy-efficient ultrahigh density artificial neural networks. [173] Adv. Mater. Technol. 2019, 4, 1800544 Figure 17. 1T1M configuration and integration process for the 1T1M synaptic device array. Reproduced with permission. [165] Copyright 2018, Wiley-VCH. Figure 18. Fully memristive neural network. a) Optical microscope imge of the memristive neural network, which consists of an 8 × 8 1T1M memristive synapse crossbar and eight diffusive memristive neurons. Note that each neuron has an external capacitor which is not shown here. b) SEM image of a single 1T1M cell. Memristive devices of the same row share bottom electrode lines. Memristors of the same column share top electrode and transistor gate lines. c) Cross-sectional TEM image of the integrated Pd/HfO x /Ta drift memristive synapse. d) SEM image of a single diffusive memristor junction. e) Cross-sectional TEM image of the Pt/Ag/SiO x :Ag/Ag/Pt diffusive memristor. All panels reproduced with permission. [173] Copyright 2018, Springer Nature.