Interlayer band-to-band tunneling and negative differential resistance in van der Waals BP/InSe field effect transistors

Atomically thin layers of van der Waals (vdW) crystals offer an ideal material platform to realize tunnel field effect transistors (TFETs) that exploit the tunneling of charge carriers across the forbidden gap of a vdW heterojunction. This type of device requires a precise energy band alignment of the different layers of the junction to optimize the tunnel current. Amongst two-dimensional (2D) vdW materials, black phosphorus (BP) and indium selenide (InSe) have a Brillouin zone-centered conduction and valence bands, and a type II band offset, both ideally suited for band-to-band tunneling. Here, we demonstrate TFETs based on BP/InSe heterojunctions with diverse electrical transport characteristics: forward rectifying, Zener-tunneling and backward rectifying characteristics are realized in BP/InSe junctions with different thickness of the BP layer or by electrostatic gating of the junction. Electrostatic gating yields a large on/off current ratio of up to 108 and negative differential resistance at low applied voltages (V ~ 0.2V). These findings illustrate versatile functionalities of TFETs based on BP and InSe, offering opportunities for applications of these 2D materials beyond the device architectures reported in the current literature.


Introduction
The progressive miniaturization of electronic devices has propelled several technologies to higher performance and efficiency, but further progress and innovative solutions to global challenges require a shift from traditional approaches towards transformative material systems and integration technologies. [1,2] Atomically thin layers of van der Waals (vdW) crystals and their heterostructures, [3][4][5] generally referred to as two-dimensional (2D) materials, offer opportunities to study and exploit quantum phenomena for a wide range of applications. [6][7][8][9][10] These crystals have strong covalent atomic bonding in the 2D planes and weak vdW interaction between the layers, which enable the fabrication of stable thin films down to the atomic monolayer thickness and stack them into multi-layered heterostructures. [11][12][13] The science of these 2D systems is developing rapidly with important technological breakthroughs emerging from recent studies.
Amongst the extended family of 2D systems, the metal chalcogenide indium selenide, InSe, [14][15][16][17][18] and the elemental compound black phosphorous, BP, [19][20][21][22][23][24] have received increasing attention. These two semiconductors have electronic properties distinct from those of other 2D materials, such as transition metal dichalcogenides (TMDCs), including a higher electron mobility beneficial for field effect transistors (FETs). [15,17,25] Also, the direct (e.g. BP) and "quasi-direct" (e.g. InSe) band gap energy of the 2D layers increases markedly with decreasing layer thickness down to a single layer, leading to an optical spectrum ranging from the violet to the infrared wavelength range. [26,27] Thin layers of InSe and BP has been used in a diverse range of functional devices, ranging from quantum point contacts, [18] giant quantum Hall effect devices, [16,28,29] and high polarization-sensitive photodetectors. [23,30] However, the electronic properties of the InSe/BP heterostructure [31][32][33][34] remain 4 still largely unexplored. Of particular interest is the opportunity to exploit tunneling across this heterojunction as BP and InSe present a number of attractive features: they both have a Brillouin zonecentered conduction band (CB) and exhibit a type II band offset, [31][32][33] which are well suited to control and exploit the transmission of charge carriers between different bands of the heterostructure for the realization of a tunnel-FET (TFET). This type of device concept has been demonstrated using junctions based on graphene and other 2D materials, [7,35] including WSe2/SnSe2 heterojunctions [36] and tunnel diodes based on MoS2/WSe2 with a symmetric dual-gate architecture. [37] However, for many 2D materials, such as TMDCs, the band edges are located at the K-point of the Brillouin zone. Thus, a precise alignment of the different layers of the junction is required to optimize the tunnel current across the heterostructure.
Here, we report on tunnel-FETs (TFETs) based on a BP/InSe heterostructure contacted with graphene electrodes and capped with a hBN layer acting as an effective encapsulating layer and dielectric for electrostatic gating. Compared to TFETs based on lateral structures, [35,38] in our TFETs the graphene, BP and InSe layers are vertically stacked leading to thin tunnel barriers for the charge carriers. This is beneficial for controlling and modulating the tunnel current across the junction. We demonstrate the operation of these TFETs at low applied voltages (< 0.5 V) and a diverse range of electrical characteristics controlled by the field effect, including negative differential resistance (NDR) due to interlayer band-to-band tunneling (BTBT). In particular, we show that with increasing the BP layer thickness from ~ 6 nm to ~ 60 nm, the heterojunction changes its properties revealing a transition from a forward rectifying pn-diode behaviour to Zener tunneling and backward rectification. The 5 transition between these diverse functionalities can also be achieved in a single device through a dual gate modulation approach. Figure 1a shows a schematic and an optical image of a typical BP/InSe heterojunction onto a SiO2/Si substrate (thickness tSiO2= 300 nm). The junction is capped with hBN and contacted with graphene electrodes. The Si-substrate serves as a bottom gate (bG) of the FET. Ta/Au contact pads on two graphene electrodes serve as source (s) and drain (d). The InSe-layer is grounded (s) and the drain voltage, Vds, is applied to the BP (d). The top hBN capping layer (thickness thBN = 20 nm) is covered with graphene, serving as a top gate electrode (tG), and is contacted with Ta/Au. In this device, the graphene sheets serve as charge extraction electrodes. In particular, the bottom graphene electrode acts to screen dopant states from the SiO2 substrate, thus providing a clean interface.  [17,39] resulting into a type-II heterojunction with a small offset of 0.10 eV between the CB of InSe and the valence band (VB) of BP. We note that the neutrality point of the Dirac cone of graphene (g = -4.5 eV) is close to the VB maximum of BP and to the CB minimum of InSe, thus facilitating the injection and extraction of holes or electrons from the graphene electrodes into/from the BP/InSe heterostructure under appropriate applied source-drain voltages and/or electrostatic gating. Due to the unintentional doping of the crystals during the growth, the BP and InSe bulk crystals are p-type and n-type doped, respectively 6 (Supplementary Information S3). For InSe, the electron density is n = 10 15 cm -3 at room temperature.

BP/InSe heterojunction
For BP, the carrier concentration tends to increase from p = 3.9×10 15 cm -3 to p = 2.7×10 17 cm -3 with increasing the layer thickness from tBP <10 nm to tBP >50 nm. A similar p-type doping of BP and dependence of the hole density on the BP layer thickness were reported before. [40,41] Figure S1. The three different transport characteristics shown in Figure 1 indicate that the behaviour of the BP/InSe junction is very sensitive to the thickness of the BP layer. We note that quantum confinement of carriers in BP can be neglected for all the flake thicknesses (tBP > 5 nm) considered in our structures. On the other hand, the work function of BP depends on the layer thickness tBP: with increasing tBP from 6 nm to 60 7 nm, it was found that the Fermi level comes closer to the valence band edge; in particular, BP can become a degenerate p-type semiconductor for thick layers. [39] This change, which remains still largely unexplored, can be exploited to tune the energy band alignment and transport characteristics when BP is combined with other 2D materials. [40,41] Since electrostatic gating represents an effective way to control and modulate the carrier density, we now examine the properties of the BP/InSe junction under different applied gate voltages.

Electrostatic gating of BP/InSe heterojunctions
The three transport characteristics shown in Figure  induces a transition from a backward-to a forward-type rectifying behaviour, which can be explained 8 by the bipolar behavior of BP [20,42] : The positive top gate voltage VtG modulates the unintentionally ptype doped BP to n-type, resulting into an n-BP/n-InSe junction. A negative back gate voltage can counterbalance this effect. Thus, p-BP/n-InSe (VbG < -20V) and n-BP/n-InSe (VbG > -20V) junctions can be both realized at VtG = +8V. To examine further the tunnel current across the BP/InSe junction, we zoom in the Ids-Vds curves in the low bias Vds-region. Figure 3 shows the Ids-Vds curves at VbG = -50V and VtG = 0V for different temperatures T from 10 to 300K. A well-defined peak in Ids-Vds and corresponding region of NDR are clearly seen in forward bias at low temperatures (T < 60K). The NDR is observed at low voltage Vds ~ 0.2V and is followed at high voltages by a steep increase of the current. In the region of NDR the 9 current density is of up to 100 2 A/m 2 . Such a well-defined peak in Ids-Vds and high current density were never reported in heterojunctions based on BP or TMDCs. [35,39] We assign the region of NDR to Zener tunneling across the p-BP/n-InSe junction. When the temperature increases to T = 60K, the NDR tends to broaden revealing a switching on/off behavior of the tunnel current. Following a further increase of temperature, this switching behavior disappears and the NDR becomes weaker and broader, disappearing when the temperature increases above T = 150K. The measured temperature dependence reveals two competing conduction mechanisms due to tunneling and thermionic emission. At low temperatures (T < 60K), the contribution of thermionic emission is small and the current is dominated by tunneling, leading to NDR. We assign the on/off switching behavior of the current to thermally assisted ionization of charge carriers onto localized states at the heterojunction interface. With increasing temperature the NDR region broadens due the thermal broadening of the carrier distributions in the layers and scattering of charge carriers by phonons. Also, the increasing contribution of thermionic emission tends to mask the NDR region in Ids-Vds.
The tunnel current and region of NDR in Ids-Vds are strongly dependent on electrostatic gating.

Figure 4a
shows the dependence of the NDR on the negative back gate voltage, VbG, at T = 50K. With increasing the back gate voltage from VbG = -50V to 0V, the NDR tends to shift to higher Vds and its peak-to-valley ratio decreases. In particular, for VbG < -15V, the current is strongly suppressed and no NDR is observed. This behavior is illustrated in the colour scale plot of the differential conductance temperatures, we measured an on/off ratio that exceeds 10 8 . This is 1 to 2 orders of magnitude higher than that of TFETs based on TMDCs. [35,41]

Conclusions
In conclusion, we have demonstrated band-to-band tunneling in BP/InSe heterostructures by using a dual-gate device architecture. The electrical transport properties of the devices vary from forward rectification to Zener-like tunneling and backward rectification with increasing the thickness of the BP layer. These diverse device functionalities can also be realized in a single device by electrostatic gating. The type II band alignment between BP and InSe enables the realization of a Zener diode with a large on/off ratio of the current, which reaches a value of up to 10 8 under low applied biases. Notably, a robust NDR region can be observed under a forward bias at low temperatures and different gate voltages, confirming that the measured electrical current is mainly due to band-to band 11 tunneling across the interface of the BP/InSe heterojunction. This work demonstrates versatile functionalities of tunnel-FETs based on BP and InSe, opening opportunities for further research and applications such as polarization-sensitive photodetectors and impact avalanche diodes. Also, different designs based on the incorporation of a tunnel barrier (e.g. hBN) at the BP/InSe interface could be envisaged to minimize carrier thermal diffusion and enhance the region of NDR for potential applications in microwave electronics.

Experimental Section
The dry transfer method for stacking the layers inside a glove box is as follows. The few-layer flakes of InSe and BP were mechanically exfoliated using adhesive tape from bulk crystals. The InSe was grown by the Bridgman method; the bulk BP crystal was purchased from Hefei Kejing Materials Technology. The tape with the InSe or BP flakes was adhered to a polymethyl methacrylate (PMMA) stamp on a glass slide to facilitate handling and identification of specific flakes by optical microscopy.
The target InSe sheet was then transferred onto the top of the first graphene electrode (drain) on a SiO2/Si substrate. Using the same method, the BP sheet was transferred on top of the InSe sheet to create a BP/InSe/graphene stack. Hence, another graphene layer was stamped onto the BP sheet to form the top electrode (source). The graphene/BP/InSe/graphene stack was capped with a 20 nm-thick hBN layer and a graphene layer was then dry transferred onto the hBN for electrostatic gating. The thicknesses of all flakes were measured by atomic force microscopy (AFM).
Graphene was grown by chemical vapor deposition (CVD) on a copper foil substrate and then transferred onto the SiO2/Si substrate to form microstamps. The graphene layers were shaped into electrodes using electron-beam lithography, oxygen plasma etching and buffered oxide etching (BOE). 12 Au/Ta electrodes (50/10 nm) were fabricated on the SiO2/Si substrate prior to the transfer using standard photoetching, thermal evaporation and lift-off.
The Ids -Vds curves were measured by an Agilent Technology B1500A Semiconductor Device Analyzer. The measurement resolution of the Semiconductor Device Analyzer was down to 0.1 fA and 25 μV.

Supporting Information
Additional data on the samples and their properties are in the Supplementary Information.

S1. Dependence of the rectification ratio on the thickness of BP
We calculated the rectification ratio for devices with different thickness of the BP layer. With increasing thickness from 6 nm to 60 nm, the rectification ratio decreases from 2 to 0.04, indicating a transition from a forward-to a backward-type rectifying behaviour.

S2. Back gate modulation of BP and InSe layers
We measured the room temperature transfer characteristics of FETs where individual BP and InSe layers are sandwiched between two graphene electrodes. For the BP-based FET, with sweeping the back gate voltage from -60V to 60V, the current first decreases, reaching a minimum at a positive gate voltage VbG ~ 10 V, and then increases, demonstrating a bipolar behavior for BP ( Figure S2a).
For the InSe-based FET, the transfer curve of Figure S2b shows that the current increases with 23 increasing gate voltage, indicating a n-type conductivity for InSe. The current on/off ratio is smaller than for BP.   Figure S5c-d shows the measured dependence of the amplitude of the current, Ids, on the source-drain voltage, Vds, at T = 300K for different applied top-gate voltages, VtG, and a bottom-gate voltage VbG = + 50V. A noticeable feature of these data is the different form of the Ids-Vds curves for VtG = -5V ( Figure S5c) and VtG = 0, +5V ( Figure S5d). At VtG = -5V ( Figure S5c), the Ids-Vds curve shows the characteristic forward-type rectifying behaviour of a pn-junction, i.e. for low applied voltages the current under a forward bias, Vds > 0, is higher than for Vds <0. The current exhibits a steep rise at Vds < -1V, suggesting a breakdown of the junction and Zener tunnelling of electrons from p-BP to n-type InSe. At VtG = 0, +5V ( Figure S5d), the Ids-Vds curves exhibit backward-type rectifying characteristics and a saturation behaviour at Vds > +0.5V.
We examined the modulation of the current by the top gate voltage in the device with thinner BP layer. The VtG-dependence of current Ids at low (T = 11 K) and room temperature (T = 300K) was measured at various VbG and Vds. As shown in Figure S6a, at T = 300K, Vds = -0.5V and VbG = 0V, the amplitude of the current, Ids, reaches a minimum at a negative top-gate voltage VtG ~ -3 V. The minimum of Ids (VtG) shifts to a lower VtG ~ -5 V at VbG = +50 V and to a higher VtG ~ -1 V at VbG = -50 V. A similar behavior is observed for Vds = +0.5V ( Figure S6b). The transfer characteristics change with lowering the temperature from T = 300 to 11K: at VbG = 0V and T = 11K, the current goes to zero; furthermore, at low temperature the modulation of the current by the top-gate voltage becomes stronger for VtG > -3V at VbG = +50 V and for VtG < +1 V at VbG = -50 V. The subthreshold swing is defined as  backward-type rectifying characteristics and a saturation behaviour at Vds > 0V; also, the current exhibits a steep rise at Vds < 0 V, suggesting a breakdown of the junction and Zener tunnelling of electrons from p-BP to n-type InSe. For VtG = 8 and 0 V, with the increases of back gate voltages, the Ids-Vds curves exhibit symmetrical characteristics, which corresponding to a n-BP/n-InSe junction.
This dependence is similar to that observed in BP/InSe heterostructures with a thinner BP layer ( Figure   S5).