Flexible Oxide Thin Film Transistors, Memristors, and Their Integration

Flexible electronics have seen extensive research over the past years due to their potential stretchability and adaptability to non‐flat surfaces. They are key to realizing low‐power sensors and circuits for wearable electronics and Internet of Things (IoT) applications. Semiconducting metal‐oxides are a prime candidate for implementing flexible electronics as their conformal deposition methods lend themselves to the idiosyncrasies of non‐rigid substrates. They are also a major component for the development of resistive memories (memristors) and as such their monolithic integration with thin film electronics has the potential to lead to novel all‐metal‐oxide devices combining memory and computing on a single node. This review focuses on exploring the recent advances across all these fronts starting from types of suitable substrates and their mechanical properties, different types of fabrication methods for thin film transistors and memristors applicable to flexible substrates (vacuum‐ or solution‐based), applications and comparison with rigid substrates while additionally delving into matters associated with their monolithic integration.

Flexible electronics have seen extensive research over the past years due to their potential stretchability and adaptability to non-flat surfaces. They are key to realizing low-power sensors and circuits for wearable electronics and Internet of Things (IoT) applications. Semiconducting metal-oxides are a prime candidate for implementing flexible electronics as their conformal deposition methods lend themselves to the idiosyncrasies of non-rigid substrates. They are also a major component for the development of resistive memories (memristors) and as such their monolithic integration with thin film electronics has the potential to lead to novel all-metal-oxide devices combining memory and computing on a single node. This review focuses on exploring the recent advances across all these fronts starting from types of suitable substrates and their mechanical properties, different types of fabrication methods for thin film transistors and memristors applicable to flexible substrates (vacuum-or solution-based), applications and comparison with rigid substrates while additionally delving into matters associated with their monolithic integration. DOI: 10.1002/adfm.202213762 mechanical flexibility, thus limiting the application range. Properties such as conformability, stretchability, or bendability are required for applications in wearables, health-care, communication and building integrated devices. [1][2][3] These challenges are approached by finding the combination of compatible fabrication techniques and suitable materials that can offer stretchable, bendable, biocompatible, and transparent features with minimum production costs and complexity at large scale. Oxide thin films are of main interest in flexible electronics due to their ability to be deposited on flexible substrates at low temperature and low thicknesses (nm range) compatible with the thermal limits of common flexible substrate. Thin Film Transistors (TFTs) can provide significantly higher electrical performance than the conventional flexible transistors amorphous hydrogenated Si (a-Si:H) TFTs, at lower costs, which can be realized as the new building blocks of flexible electronics. TFTs have shown great advances on flexible substrates, especially using Polyimide (PI), enabling them to maintain good performance compared to regular devices on flat and rigid substrates.
Memristive devices are another application of thin films, which can store bits of memory according to a switch in their electrical resistance under an applied electric field. Most importantly, they can function as neural synapses that may be applied in new computer architectures to overcome the current von Neumann computing bottleneck. [4] When both TFTs and memristors are combined in crossbar arrays of 1-Transistor 1-Memristor (1T1R), they enable performant non-volatile and volatile memories, in-memory computing or neuromorphic applications. Recently, high performing memristors and transistors have been developed on flexible substrates. The common thin film fabrication procedures are either vacuum or solution-based depositions and their relative properties are depicted in Figure 1a. Vacuum processing techniques such as physical vapour deposition (PVD) or chemical vapour deposition (CVD) are more mature with optimized performance and high reproducibility. [5] They allow a well-controlled deposition process since parameters such as the chamber pressure, temperature, and elemental composition can be accurately monitored. Therefore, the resulting films typically have micro and nano structures with high uniformity and low defect densities, good step coverage, and excellent adhesion even for room

Introduction
Currently, most of the electronic applications are based mainly on silicon substrates that can offer high-performance but no temperature (RT) fabrication processes. [5] Nevertheless, these procedures involve expensive tools and high energy consumption due to the level of required vacuum. [5,6] In contrast, solution-processing methods [7,8] have a lower degree of deposition complexity and they usually operate in ambient conditions that directly reduces the overall cost. [9,10] However, solutionprocessed depositions are limited by lower reproducibility compared to vacuum-based counterparts that hinders a large-scale commercialization. Other limitations involve lower uniformity, due to less controlled deposition parameters and more difficult to control crystallization, which can lead to defects. Figure 1b compares the different semiconductors used for TFTs in terms of deposition maturity, charge carrier mobility, temperature required during fabrication, fabrication cost and on/off current ratio (I on/off ). A detailed description of the how the values related to Figure 1 were calculated is presented in Tables S1 and S2 (Supporting Information). For TFTs, materials of interest are amorphous hydrogenated silicon (a-Si:H), [11] Low-Temperature Polycrystalline Silicon (LTPS), [12] organic semiconductors [13] and Metal Oxides (MOs). [8] A-Si:H is deposited by vacuum techniques, does not require high temperature, exhibits n-type conduction [15] and it is used typically in flexible displays. [16,17] However, the low charge mobility µ ≈1 cm 2 V −1 s −1 , [11] and instable threshold voltages at bias stress, caused by dangling bonds and trap charges, [18] is currently still a limitation. Organic semiconductors have a developing maturity, exhibit the highest mechanical flexibility out of all the materials presented here, [19] perform better on hole conduction (≈10 cm 2 V −1 s −1 ), can be fabricated under room-temperature (RT), and are costefficient. [20] On the contrary, organic semiconductors still have low n-type electrical performance, they are more sensitive to environmental degradation under moisture, oxygen or UV exposure [19] which affects the device stability. LTPS TFTs offer high electron mobility, stable Threshold Voltage (V th ) and long-term reliability for flexible organic light emitting diodes (OLEDs), [21] but LTPS has high manufacturing costs, complexity and high processing temperature (<500 °C). [10] Fortunately, these drawbacks can be overcome by MOs due to a more cost-efficient fabrication and simpler design structure than LTPS and crystalline-Si MOSFETs. [22] Moreover, they maintain a relatively high n-type charge carrier transport, provide high transparency due to their wide bandgaps (>3.4 eV), exhibit low leakage current, [10] and in some cases even ambipolarity. [23] MOs are a promising material class for the next generation of electronics, and flexible applications, as detailed in this review. In Chapter 2, we present an overview of the most common flexible substrates used for MO TFTs and memristive applications. Then, Chapter 3 highlights the advances in vacuum and solution based TFTs and memristors on flexible substrates, whereas Chapter 4 shows the final conclusions.

Flexible Substrates
Several flexible materials have been explored as substrates ( Figure 2) including PI, [41] Polyethylene Terephthalate (PET), [42] Polyethylene Naphthalate (PEN), [43] Thermoplastic Polyurethane (TPU), [44] cellulose paper, [45] Polyestersulfone (PES), [46] and Colorless Polyimide (CPI), [47] whereas their properties are exposed in Table 1. PI is a widely commercialized polymer and due to its attractive properties [44] and it is the most popular substrate for both TFTs and memristive applications, as noted in Tables S3 and S5 (Supporting Information). In particular, it exhibits high mechanical performance under compressive and tensile forces, has superior wearability and it is resistant to most chemical solvents that are often required for MO TFT fabrication (Figure 2a). [48] Moreover, it has relatively high glass temperature (T g ) and low Thermal Expansion Coefficient (CTE) 30-60 ppm °C, [27] which allows device fabrication up to 350 °C. [26] However, PI has a high cost in general (287£ per 300×300 mm film of ≈0.1 mm thickness [49] ) is more permeable to water when comparing with PEN substrates (8.4 vs 4.3 g m −2 day −1 ), [24,50] so a buffer layer is required prior the deposition of the charge transporting layer to improve device performance and stability. [48] PI is sensitive to alkali and acids and has a yellow tint color associated with low transparency. [26] Colorless Figure 1. Spider charts comparing: a) vacuum versus solution based fabrication processes, summarizing the electrical parameters mobility and I on/off as well as the fabrication characteristics deposition maturity, accuracy, and room-temperature (RT) deposition. b) Active layer materials for TFT channels: a:Si:H, LTPS, organics, MOs compared by the electrical parameters (mobility and I on/off ), mechanical parameter (bending flexibility), [19] as well as the fabrication characteristics (deposition maturity, cost-efficiency and RT fabrication). More details on how the respective categories are defined and quantified can be found in the Tables S1 and S2 (Supporting Information).
Similarly to mica substrate, stainless steel foils (Figure 2f) [70] have a high melting point (1400 °C), excellent ductility and corrosion resistance, and they usually preserve their size under thermal processing (low CTE). The high Young modulus (193)(194)(195)(196)(197)(198)(199)(200) ) limits the stretchability of this foil, but the tensile strength is high. Similar to paper, stainless steel has a rather high surface roughness. Additionally, because it is a conductive alloy, the application of a buffer layer is required. This may be a limiting factor regarding the temperature range in further fabrication processes and it might restrict the mechanical flexibility. [71] The properties of each flexible substrate strengthen the next chapter where the improvements and structure of the latest flexible devices are presented. In order to benefit from the flexible substrates, there are several techniques that allow the electronics to be transferred or patterned on them. Therefore, the next section reviews the available related procedures. [71]

Flexible Substrate Delamination and Transfer
In order to build thin film electronics on flexible substrates, a solid support is often required during fabrication steps. Glass substrates are a common carrier [21,62,72,73] due to their nonreactive state, low CTE and resistance to high temperatures (<1000 °C). One main challenge is the separation of the flexible substrate from the carrier without affecting the device performance. Several methods have been explored for overcoming the delamination challenge including Laser Lift Off (LLO) that is currently used in industry and utilizes an excimer laser for the effective separation. [74][75][76] The laser heats the polymer locally and sequentially across the substrate area that results in ablation at the interface between the flexible and carrier substrate [77] due to the difference in the thermal expansion coefficient between them. This behavior makes it possible to unstick the two layers by heat exposure (Figure 3a). [21,72] However, for large area electronics this technique has several challenges, including the use of expensive lasers, the uniformity depends on power fluctuations of the laser and it is a time-demanding process. [78] To overcome these challenges, Weidling et al. [77] proposed a less complex and faster approach using a non-laser Photonic Lift-Off (PLO) that exposes a single pulse (150 µs of broadband light at 45 kW cm −2 ) onto the glass wafer. Before the flexible substrate is attached to the wafer, a light adsorbing layer (250 nm) is initially deposited onto the glass to reduce the incident lighting onto the polymer substrate, thus avoiding ashing. They showed effective delamination of the polymer support by PLO and demonstrated Indium Zinc Oxide (IZO) TFTs with µ FE = 3.15 cm 2 V −1 s −1 and SS = 152 mV. They also performed bending tests, which showed slight degradation on the IZO TFT performance (δ µ = 0.04, δ SS = 18 mV) under bending radius of 10 mm.
The insertion of sacrificial layers between the flexible substrate and carrier have also been explored in an effort to replace the LLO process. To this end, a solution-processed layer of Carbon-Nanotubes and Graphene Oxide (CNT/GO) was deposited on a glass substrate prior a coating of PI. As the CNT/GO layer reduces the adhesion of PI on the glass substrate, this approach was proposed as an alternative method to LLO. [58,62] In cases where a lower number of process steps are required, a simple mechanical peel-off can separate a thin CPI layer (12 µm) from a Si/SiO 2 wafer. [47] Furthermore, PI was used as sacrificial layer between a Si wafer and PES layer during the fabrication of aluminium oxide-based memristors. PI was chosen due to its resistance to electrode wet etch processes that allow it to maintain the attachment to the carrier wafer ( Figure 3b). [58,73] In an effort to develop free standing memristors, Lin et al. [79] developed a method where NaCl crystals were utilized as the carrier substrate (Figure 3c). They successfully demonstrated this method for vacuum-based Pt/WO X /Ti memristors. A protective layer of PMMA was applied on top of the device prior to dissolving the NaCl in water. The resulting devices were transferred on a PEN substrate and, similarly, it was also demonstrated that this method is compatible with other substrate types, i.e., printing paper, glass dome, polydimethylsiloxane (PDMS) and even the biocompatible pectin.

Flexible Electronic Devices
TFTs are of great importance in memristive applications due to their role as selector switch. Memristors are usually fabricated in Single Line (SL) or Crossbar Array (CA), whereas the latter is used for implementing more complex applications as memory or for computing purposes. Unfortunately, selectorless CAs suffer from sneak current paths altering the correct  TFT, separating a PI substrate from a glass carrier due to a CTE mismatch at their interface. Reproduced with permission. [72] Copyright 2019, American Chemical Society. b) Sacrificial layer separation method using a PI glue layer which reduces the binding force between a PES and Si wafer for RRAMs. Reproduced with permission. [58] Copyright 2008, American Institute of Physics. c) Four sequential steps in separating a WOx memristor from a soluble NaCl substrate and the subsequent transfer onto other flexible substrates. Reproduced with permission. [79] Copyright 2018, WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.  [44] Copyright 2021, American Chemical Society. b) Semi-fixed-clamp press acting on an attached PI substrate, bending it using the second mobile clamp, creating a circle arc. Adapted with permission. [83] Copyright 2021, Wiley-VCH GmbH.
bias and reading on any memristor cell, subsequently leading to an erroneous behavior. A selector is a piece of electronics, such as a diode or a transistor, that is responsible for biasing the corresponding selected cell and blocking any leakage current from neighboring memory cells. Currently, there are several linear and nonlinear selectors available according to the International Roadmap for Devices and Systems (IRDS). [85] Si rectifier diodes represent a potential non-linear selector due to the ability to reject reverse current. However, Si diodes usually have high leakage current (µA range) compared to MO TFTs and require high temperature fabrication (1000 °C), [86] which is incompatible with flexible substrates. Similarly, Si MOS-FETs could act as CA selector due to their small size and high switching performance. The high processing temperatures and rigidity are not making them an ideal candidate. Transfer methods from Silicon on Insulator (SOI) have been explored on flexible substrates, but further development is required to improve the electrical stability under mechanical deformation. [87] Si thinning from SOI chips can produce flexible Si devices as Si-diodes or c-Si crystalline-silicon (c-Si) transistors, however the process is complex, costly, and the back grinding process could potentially damage the Si layer. [88] On the other side, MO diodes [89][90][91][92] based on sputtered IGZO are fabricated at lower temperatures, with low complexity and lower leakage current (nA) than Si-diodes and can be patterned either as heterojunction or Schottky diodes. Thus, they enable an optimal solution for producing flexible diodes, enabling compatibility with memristor arrays (1D1R: 1-Diode 1-Resistor), and to serve as selector and further flexible electronics. Similarly, MO TFTs can be used as selector in memristor arrays (1T1R: 1-Transistor & 1-Resistor), with low structure complexity, flexible substrate compatibility and low leakage current (pA range). They are the most common type of selectors used in memories although they have a slightly higher footprint (6 − 8F 2 ) than the highest 2D device density found in crossbar arrays (4F 2 ). [85] Lower footprints of 4F 2 could be achieved through vertical TFTs structures disposed in 3D stacks, [64] and therefore in 1T1R 3D structures, [72] although the thermal stress and the gate terminal could cause integration challenges due to the structure compactness. Other nonlinear devices (tunneling-based nonlinear selector or Mixed Ionic and Electronic Conduction -MIEC) or volatile switches (Threshold switch or Mott switch) are suitable for selectors according to IRDS [85] although MO TFTs and diodes are more commonly explored in flexible electronics fabrications. However, in this work only MO TFTs and memristive arrays are reviewed for exploring them in the next generation integrated flexible electronics.

Vacuum-Based TFTs
Table S3 (Supporting Information) summarizes the characteristic parameters of the latest developments in flexible MO TFTs, including µ, I on/off , V th , and Subthreshold Swing (SS). It is worth noting that the recent flexible n-type TFTs frequently exhibit I on/off ratio of 10 6 − 10 8 , whereas flexible p-type devices show lower values 10 3 − 10 4 . Several reviews have been published on flexible MO TFTs in the last decade including Fortunato et al. [10] with main emphasis on solution-processed p-type (with articles up to 2011); Petti et al. [71] focusing on rigid and flexible both solution and vacuum processed MO TFTs (with articles up to 2016); Mohammad et al. [19] summarizing the advances on flexible TFTs from MOs, LTPS, a-Si:H, and organic materials with emphasis on flexible properties (articles up to 2017); Cantarella [93] presented an overview on flexible MO TFTs in analog and complementary circuit configurations (with articles up to 2019). Figure 5 presents an overview of the vacuum processed flexible TFT results as presented in the literature in the last decade, classified by fabrication and performance parameters. Figure 5a shows the maximum processing temperature during the device fabrication at any point during or after the semiconductor deposition, as well as the flexible substrate material and the achieved mobility ranges. It can be seen that there is an increase in studies of flexible MO TFTs since 2016. Although, there is no immediately apparent trend in the evolution of the maximum processing temperature, a slight decrease of the average fabrication temperature from 2017 onward can nevertheless be observed, as shown Figure S1d (Supporting Information). According to their T g , as presented in Section 2, each substrate seems to cover a specific process temperature range. PI represents the most used substrate across the whole range of temperatures up to 400 °C followed by PET and PEN ( Figure S1b, Supporting Information). Figure 5b presents the flexible MO TFT mobility evolution over time classified by the semiconductor material, either n-type or p-type (SnO only). Over the investigated period, most devices present mobilities of over 10 cm 2 V −1 s −1 even when processed at RT. IGZO represents the most preferred material, followed by IZO and ZnO ( Figure S1a, Supporting Information) due to their attractive properties described in Section 3.2. Most n-type devices achieve high mobilities in between 10 and 100 cm 2 V −1 s −1 , whereas most p-type devices peak at the lowest mobility range of < 1 cm 2 V −1 s −1 .
From this investigation it can be deducted that the electrical properties of the TFTs (particularly n-type) needs to be maintained under various mechanical stress conditions, therefore the challenge remains to design devices more electrically resilient to mechanical damage than solely increasing their electrical specs. Additionally, in p-type MO TFTs, the focus should also be directed more toward generating more research results and also overcoming the poor hole conduction for a further flexible CMOS integration. The next subsections present the approaches used to improve the recent flexible MO TFTs in terms of their conduction type and most significant results available.

Approaches for Improving Flexible n-Type MO TFTs
IGZO is one of the most utilized metal-oxide semiconductors for its high transparency, uniformity and good charge transporting properties. IGZO was first developed in 2003 by Nomura et al. [94] on flexible PET and since then this technology has been further developed and implemented in commercial products, i.e., for Liquid Crystal Display (LCD) or Active Matric Organic Light Emitting Diode (AMOLED) applications from Samsung and Apple. [96] Billah et al. [96] revealed that tensile bending seems to damage the thin films more than compressive bending. Microcracks can form in the dielectric layer during bending that increases the interface defect states. [96,97] In addition, infiltration of humidity through these cracks poses another challenge. [97] One way to circumvent microcrack formation is the use of island TFTs; [19,67] their unique structure enables mechanical flexibility by having an array of individual rigid TFTs on a main flexible substrate, connected with flexible highly conductive links in between them. This technology allows the device itself to not bend intrinsically as much as the connections, preserving the integrity of the device structure and performance. Park et al. [98] reported a flexible island-type IGZO TFT presenting moderate electrical characteristics of electron mobility (µ e ) of ≈12 cm 2 V −1 s −1 and I on/off > 10 7 whose performance was found to be independent of the applied substrate bending. The authors showed that TFTs could withstand 10 000 bending cycles at 1.5 mm radius without significant deviation in the electrical performance as (Δµ e < 10%). [98] More recently, Han et al. [44] reported IGZO TFTs on polyimide islands, deposited on a largerTPU layer with slightly improved electrical performance (12.8 cm 2 V −1 s −1 and I on/off ∼10 8 ). Most importantly, the bending test was repeated 15 times more than in the previous report, [98] whereas the deviation in saturation mobility (µ sat ) and SS maintained nearly at 10%. Furthermore, a stretchability test of up to 15% to 30% strain has been repeated for 10 000 times with minimum implication on the SS and µ sat . These improvements are likely due to low Young modulus of TPU (26 MPa [99] ) that reduced the curvature of the PI islands.
A recent work proposed using an acrylic based substrate for a structure of ITZO TFT islands that supported 50% to 100% strain with subsequent release to 0% without performance degradation (µ e = 30 cm 2 V −1 s −1 ). [100] This was possible due to the strong adhesion between the acrylic substrate and a PI base that was part of each TFT island. This adhesion would prevent the islands delamination during severe stretching. In addition, the islands benefit from an individual rigid passivation layer that helps the islands to avoid the applied strain. Altering the device structure has shown to improve resilience under bending. In particular, vertical TFTs (VTFTs) can improve the bending capabilities due to higher resilience to in-plane cracking of the active semiconductor. [1] Also, recent studies on VTFTs successfully demonstrated low operating voltages, as low as 0.1 V, and small SS (≈80 mV dec −1 ) [45] that is ideal for low-power and portable electronics.
Another method to improve electrical stability after mechanical deformation is to use Elevated Metal-Metal Oxide (EMMO) structures. [101] EMMO IGZO is a relatively new TFT architecture, fabricated from vacuum procedures, which resembles the typical bottom gate TFT with Back Channel Etch (BCE) delivering significantly high I on/off ratio (10 10 ) and low leakage current (10 −14 A), and a charge carrier mobility of 14 cm 2 V −1 s −1 . [101] Later, the first flexible EMMO TFT exhibited slightly lower performance (average µ FE = 8 cm 2 V −1 s −1 and I on/off = 6.5 × 10 8 ) but it maintained electrical stability under mechanical strain of 2.5-25 mm bending radius with low deviations in drain current (<15%). [102] More recently, other investigations on EMMO IGZO TFT have been carried on PI. For instance, the Self-Heating Effect (SHE) that resulted from bias stress (V g = 40 V and V d = 20 V) was significantly higher on PI than on Si substrates, and it induced a negative V th shift from ≈0 V to −12 V. [103] Moreover, EMMO has been integrated in unipolar digital circuits (inverter, nor gates) on PI. [104] In unipolar design circuits with TFTs, the open-loop gain is significantly lower than what a similar bipolar CMOS could exhibit; however, the proposed unipolar design could achieve comparable open-loop gain with an increase in the design complexity. Also, the three inverter implementations proposed a hybrid-TFT structure, made of both depletion and enhancement EMMO transistors, that provided ratio-less design, high gain, and wide noise margin compared to pseudo-CMOS designs.
Another successful method was reported by Lee et al. [62] where they split the TFT channel (100 µm) in thinner subchannels with 2 and 1.5 µm spacing, which resulted in devices with electron mobility of 76.8 cm 2 V −1 s −1 . An Etch-Stopper layer (ES) of SiO 2 was deposited by PECVD on the IGZO layer to preserve its semiconductive properties and it was patterned by dry etching using a plasma source of NF 3 /H 2 . [62] Additionally, the devices could be attached to a latex glove and could be bent for 5000 times without significant performance degradation of V th . [62] The increase in the mobility was attributed to the lowering of interface density states by improvements on the top interface by metal-F bonds. [62] Even when TFT performance suffer from excessive mechanical strain, researchers found that this effect can be partly reversible. For instance, Jeong et al. [105] demonstrated that mechanically degraded MO TFTs after 40 000 bending cycles can be approximately restored to their initial mobility and SS, by applying an external thermal energy of 150 °C for 4 h. Similarly, Bilah et al. [106] showed that a V th shift of −3.5 V after an IGZO TFT is mechanically bent by 1.65% strain for 10 000 bending cycles was completely corrected after a Positive Bias Recovery (PBS) of 30 V (V G = V D ) in 1 millisecond, or partially recovered under exposure to 60 °C and V G = 30 V for 1 h. [106] This recovery is due to Joule heating that cures the existing traps by a local annealing. [106] Using ternary compounds such as IZO has proven an efficient way to increase charge carrier mobility due to more oxygen vacancies. [107,108] However, when implemented in TFTs, they lead to lower I on/off ratios due to the high carrier densities that increases the I off . [109] Mixing two or more cations with different charges and sizes suppresses the MO crystallization and will create an amorphous material. As a result, an improved uniformity regarding parameter spreads of, e.g., threshold voltage shifts and better stability to environmental conditions such as light or heat can be found. [109] There are several reports on flexible IZO-based TFTs, [107,108,[110][111][112] as summarized in Table S3 (Supporting Information). The main fabrication procedure for the active layer is magnetron sputtering, [107,110,111] but a more uniform and conformal deposition has been reported by atomic layer deposition (ALD). [108] However, the fabrication of ternary components grown by ALD requires further exploitation. [108] Recently, Lu et al. [81] presented a Nd-doped IZO TFT deposited via magnetron sputtering using a ratio of Nd 2 O 3 :In 2 O 3 :ZnO (1:62.5:36.5) and an Ar/O 2 (100:1) gas flow. This resulted in devices with a high charge carrier mobility of 40.3 cm 2 V −1 s −1 , and an increased I on/off of 1.24 × 10 8 compared to sputtered IZO TFTs. In terms of contact electrodes, Cu, or Al, or ITO produced a depletion mode TFT, in the same article. [81] However, by using an alloy of Cr and Zr as S/D, the Nd:IZO device operated in enhancement mode and could withstand 120 000 bending cycles without damage due to the high stability and adhesion strength of the Cu-Cr-Zn (CCZ) alloy. Also, a good energy alignment between the alloy electrode work function and Fermi levels of the channel enhanced the ohmic contact at their interface.
A key obstacle in IGZO-based devices, is the presence of Indium in the compound as it is a rare element. In an effort to minimize Indium, the mixture of Indium Tin Gallium Zinc Oxide (ITGZO) [47,51] was proposed, which replaces part of Indium with Tin due to their compatibility of ions in terms of quantum number that directly impacts the conductive electron pathway. [113] Flexible ITGZO TFTs have been demonstrated on CPI films with excellent mobilities of 34.32 cm 2 V −1 s −1 and SS of 169 mV, with good electrical stability under bending to a 2 mm radius. [47] Lee et al., [47,51] reported ITGZO TFTs under repetitive mechanical stress and demonstrated robust electrical performance of ≈30 cm 2 V −1 s −1 below 50000 bending cycles.
Electrical degradation by 10% in the SS was observed beyond 50 000 cycles that was correlated with an increase of oxygen interstitial defects. [47,51] On the other hand, a thermally cured IGZO, showed a slightly lower SS degradation than ITGZO (7%), after a mechanical deformation. [105] Two-cation oxide TFTs based on Tin Silicon Dioxide (STO) have also been explored. TFTs utilize Si as carrier suppressor that turns the polycrystalline SnO 2 n-type channel into an amorphous phase. [83] The resulting flexible STO TFT exhibits moderate mobility (7.59 cm 2 V −1 s −1 ) and I on/off of 10 7 after 3500 bending cycles. TFTs were fabricated by RF magnetron sputtering at room temperature without any post annealing that is suitable for many flexible applications. [83] Binary metal-oxide compounds including ZnO, [114][115][116] InOx, [48] SnOx [117] have been investigated for their compatibility for flexible TFTs. They are able to provide fast switching resulting from high field effect mobilities (10-20 cm 2 V −1 s −1 ). But they also suffer from nonuniform performance over large area, which is attributed to the polycrystalline phase of binary compounds. This can cause large threshold voltage shifts and results in low bias stability. [109] In conclusion, there are several methods of improving n-type MO TFTs presented such that focus on preserving the electrical performance under mechanical stress (e.g., island TFTs, EMMO or VTFT structures), improving the electrical performance (e.g., split-channels TFT, ternary compound semiconductors), or restoring the TFT electrical properties after mechanical damage by annealing.

Approaches for Improving Flexible p-Type and CMOS MO-TFTs
Flexible p-type MO TFTs have been reported over the past decade with notable results from SnO, [118][119][120][121] , Cu 2 O, [46,122] and NiO x . [71,93] They are important in order to enable full-oxide CMOS integrated circuits for power efficiency, negligible signalto-noise ratio and compatibility to current electronic circuit configurations. However, p-type MOs still require improvements of their electrical performance and generally exhibit lower I on/off ratio and hole mobility compared to n-type devices. SnOx TFTs were developed on PI substrates using vacuum-based techniques at temperatures in between 175-350 °C. [123][124][125][126][127] The semiconductors were deposited solely by magnetron RF sputtering, whereas the dielectrics for the substrate buffer layer, gate dielectric and passivation were produced by ALD and RF sputtering, and the metal electrodes by electron-beam evaporation.
Hsu et al. [125] studied the effect of the mechanical stress on the electrical properties of SnOx TFTs. Devices were fabricated on polyimide with a bottom-gate structure and realized modest p-type performance (µ h = 0.4 cm 2 V −1 s −1 , I on/off ≈10 3 ). Under tensile strain TFTs showed a degradation in mobility (≈20%) and SS (10%) but no significant deviation was observed under compressive forces, both at a 1 cm bending radius (Figure 6a). Furthermore, Cheng et al. [124] found that a 10% V th shift under gate bias stress while the devices were bent outward for 10 000 s at 0.8 V. Also, only negligible deviation was observed on an inward bending. [125] Both studies, [124,125] showed similar results indicating that tensile bending causes slightly more gate-induced stress than compressive bending. This effect may www.afm-journal.de www.advancedsciencenews.com 2213762 (9 of 24) © 2023 The Authors. Advanced Functional Materials published by Wiley-VCH GmbH be correlated with an increase of trap states in the channel interface. Also, the difference in bottom-gate [125] and top-gate [97] channel position relatively to the bending point might influence the level of device damage at a similar bending radius due to the degree of channel interface strain.
P-type TFTs performance can be enhanced by various active layer treatments. Cheng et al. [124] demonstrated that for a coplanar top-gate SnOx TFTs, an optimal annealing temperature of 165 °C can enhance hole mobility from 0.065 (195 °C) to 1.3 cm 2 V −1 s −1 (165 °C) that is correlated to an increase in drain current for a range of V GS . Similarly, the I on/off , V th , and SS showed improvements when annealing temperatures below 185 °C were tested. Mohanty et al. [128] showed that furnace annealing or microwave annealing improved the Ion/off by at least one order magnitude, as well as increasing the transmittance from 55% to 75 and 82%, respectively (Figure 6b). In another study, [82] it was found that an O 2 plasma treatment applied on the TFT channel after annealing (200 °C) and before the top electrode (TE) deposition, can enhance the SnOx hole mobility and I on/off to 10.7 cm 2 V −1 s −1 and 5.7 × 10 5 respectively, which are the highest values reported so far for flexible p-type MO TFTs. Plasma treatment can set the film's conduction mode according to the amount of O 2 plasma struck on the film (Figure 6c), leading to ambipolar SnOx devices. [82] Therefore, the manufacturing process can be simplified, and with further improvement, CMOS integration could be achieved on the same SnOx film.
Oxide-based CMOS circuits have also been explored on flexible substrates. For example, a high gain (370 v/v) flexible inverter based on IGZO and SnOx TFTs was fabricated on a 5.5 µm thick PI substrate. [126] CMOS inverters on plastic substrates could also be demonstrated with a high gain up to 131.57 and a 98% yield (Figure 7a). [123] In a further study, flexible IGZO/SnOx inverter exhibited good electrical stability (µ FE , V th , SS) under 5 mm compression and tension strain ( Figure 7b) and a static voltage gain of 370. [127] Lastly, a flexible CMOS inverter based on ZnOx/SnOx inverters was demonstrated on PI exhibiting 12 V/V gain and functional ring oscillator at ≈18.4 kHz and deviation of under 15% for output voltage and oscillating frequency for a range of bending strains (Figure 7c). [126] In conclusion, the articles presented, highlight a progress in flexible SnOx p-type devices including CMOS where several mechanical stress tests have been performed including methods to improve the developing hole conduction by either thermal and microwave annealing. N-type SnO 2 could be achieved from plasma treated p-type SnO, in the benefit of a less complex and further CMOS integration, while maintaining a low fabrication temperature for achieving flexible devices. However, the p-type and CMOS MO TFT are still requiring more input from the research community in order to counterbalance the progresses in flexible tests on n-type devices, and electrical performance.

Solution-Based TFTs
Like vacuum-based techniques, solution processing of flexible metal MO TFTs is limited by the same temperature restrictions that arise from the use of the typically polymer-based flexible substrates. Most solution processes use chemical precursor formulations, such as solutions of metals salts, which require a certain amount of energy input to drive a chemical conversion into the fully formed MO. Contrary to common vacuum processes, solution-based techniques therefore often consist of a two-step fabrication with a deposition step and a subsequent conversion, typically initiated by thermal annealing (TA). The annealing temperatures for the latter process historically required conditions above 300 -400 °C, ruling out the usage of inexpensive standard polymer foils as substrates. [129,130] However, since a lot of the envisioned benefits of solution processing center around the inexpensive, large-area and high-throughput fabrication, e.g., in roll-to-roll printing as well as digital ondemand processes such as ink-jet printing, a lot of concurrent research efforts are in progress to a) lower the overall process temperatures, b) improve printing speed and resolution and c) to improve the operational stability of flexible devices.
While different fabrication techniques, low temperature approaches as well as techniques to improve the resistance to bending stresses will be mentioned below, a full breakdown of each of those is out of scope for this article. Instead, the reader is directed to a number of recent review articles that deal with specific aspects of solution-processed MOs for flexible TFTs in more detail than is possible here. For example, a general overview of solution-processed MOs is given by Ahn et al., [129] or Chen et al., [131] while the reviews by Jo et al., [132] Park et al., [130] and Petti et al., [71] focus specifically on MOs for flexible electronic devices. Peng et al. took a closer look on ZnO as the semiconductor (SC) in flexible applications. [133] While Liu et al. summarized work on solution-processed high-k dielectrics made from MOs. [134] The publications by Tiwari et al. and Carlos et al. give breakdowns of the various approaches for low temperature fabrication of MOs. [135,136] Among those approaches, the variation in precursor chemistry has proven quite effective. Here, the work by Cochran et al. [137] offers detailed insights into the features of metal nitrate-based precursors. Additionally, the benefits and principles behind working with precursors based on combustion-chemistry are laid out in the reports by Pujar et al. [138] and Wang et al., [139] respectively. The latter study also summarized the effect of polymer doping the MO precursors, i.e., the admixture of discrete amounts of insulating polymers in order to frustrate semiconductor crystallization, to tune device performance and to improve the mechanical stability under bending. Another aspect for low-temperature fabrication of MO devices is the use of various forms of light and photonic processes, as was summarized by Yarali et al. [140]

Deposition Methods
Although high throughput large-area fabrication is among the goals for solution processing routes, the majority of research reports on flexible MO TFTs still relies on spin coating as the Adv. Funct. Mater. 2023, 33, 2213762   Figure 7. a) IGZO/SnOx CMOS device representation (top) and D-latch logic integrated circuit (IC). Adapted with permission. [123] Copyright 2019, IEEE. b) Normalized parameters of field effect mobility, subthreshold swing, and threshold voltage for a IGZO (top); and SnOx (bottom) inverter at several bending strains under compression and tension. Adapted with permission. [127] Copyright 2021, IEEE. c) Peak-to-peak voltage and oscillation frequency (kHz) versus bending curvature and of a ZnO/SnOx inverter (top); and its real implementation on PI film. Adapted with permission. [126] Copyright 2015, IEEE.  Figure S2a, Supporting Information). To a lesser degree other methods such as ink-jet or electrohydrodynamic ink-jet printing that directly allow a patterned deposition find usage [141][142][143][144][145][146][147] as well as spray processes (spray coating/pyrolysis, aerosol-jet printing) that facilitate large-area depositions, [148][149][150] , low temperature hydrothermal growth of ZnO, [151,152] or blade coating. [153] Additionally, deposition methods that are closer to industrial roll-to-roll printing techniques such as flexography [145,154] and reverse offset printing [155] are evaluated. For the former, printing speeds of 50 m min −1 have been demonstrated, for the latter a high resolution of printed In 2 O 3 with a 2 µm minimum feature size was achieved.

Approaches for Low Temperatures Processing
In order to achieve low process temperatures that allow the use of common flexible substrates a number of different approaches can be undertaken and have been explored in the past. One approach is to avoid the use of precursors altogether and instead utilize nanoparticles of the desired MO. This removes the need for an energy intensive conversion step after the film deposition, however, post-deposition treatments are nevertheless often required in order to remove stabilizers and surface ligands and thus to improve the interparticle contacts. [143,146] When precursor inks are used to form MOs, there are a lot of options to consider and the choice of the starting metal compound, the solvent and potential additives can have profound impacts on the final device performance and temperature requirements. For example, when comparing different metal compounds (nitrates, acetates, chlorides, fluorides) as the starting point it was found that the lowest conversion temperatures and best device performance was possible using the metal nitrate species. [156,157] Besides typical organic solvents such as 2-methoxyethanol, using the "aqueous" route and choosing water as the solvent has proven not only environmentally friendly but also effective in reducing the required annealing temperatures. [158] This was attributed to the complex formation between a central In 3+ cation and neighboring ions whose relatively weak coordination bond can be broken at low temperatures. Aqueous ammonia has become a popular solvent for the low temperature fabrication of ZnO thin films. It allows the facile dissolution of zinc hydroxides or plainly ZnO powder and enables carbon-free processing of polycrystalline ZnO films at low temperatures, even down to 100 °C. [159][160][161][162][163][164][165][166][167][168] A very versatile way to reduce processing temperatures and improve device performances was introduced by Kim et. al. [169] who made use of precursors containing an oxidizing component (metal nitrates) and a fuel component (acetylacetone or urea). This initiated an exothermic combustion reaction at moderate temperatures, thus locally generating further heat to help form the final MO. The combustion approach has since been adapted for a variety of MO's acting as semiconductors, dielectrics or conductive electrodes, and a range of different oxidizer/fuel compositions has been evaluated. [138,139,145,149,153,[169][170][171][172][173][174] Photonic processing is an umbrella term that encompasses the use of light in a variety of implementations, which can help to reduce fabrication temperatures, improve device performance or allow short process times. [140] For example, Kim et al. [175] demonstrated that Deep UVRadiation (DUV) from a low-pressure mercury lamp can be absorbed by suitable MO precursors that helps to photo-activate the metal-oxide-metal network formation. While it was observed that DUV irradiation leads to an unintentional substrate heating of up to 150 °C, the technique has nevertheless proven to be an effective method for the fabrication of semiconductors and dielectrics in flexible TFTs. [144,145,162,167,[175][176][177][178][179][180][181][182] Similarly, DUV treatments can also be employed to remove the ligand shell of NPs and thus improve interparticle contact and TFT performance. [143] Additionally, DUV light can also function as a tool for patterning of MO layers. Using a shadow mask on top of the substrate, only portions of the precursor film are illuminated and begin to form M-O-M networks. Consequently, these parts become insoluble while the rest of the precursor can be washed away by suitable solvents. [170][171][172]183] Flash lamp annealing (FLA) is process where high energetic white light pulses are sent to the substrate where the energy is either absorbed by a precursor material itself or by an absorber element (such as a metallic gate electrode) that then locally heats up any precursor material in the vicinity. With the right combination of materials, FLA allows the rapid fabrication of MO films (timescale of seconds compared to tens of minutes or hours for conventional TA) while keeping the substrate temperature low, making it a promising technique for flexible electronics. [184,185] Laser annealing (LA) can be used to very precisely deliver energy to the MO films where it is needed. Examples for the application of LA for flexible MO TFTs include the precursor conversion to IGZO using a fs-pulsed laser of 800 nm wavelength, [131] as well as the ligand shell removal of In 2 O 3 NPs using a low power (6 mW) continuous wave He-Cd laser (325 nm wavelength). [143] In both cases, device fabrication could be realized with low maximum temperatures of 120 °C and room temperature, respectively.
Other low temperature post-deposition treatments that have yielded good results include, e.g., the microwave, [164,176,186,187] or high pressure annealing, [188] as well as hydrogen plasma exposure. [189] For an overview of performance parameters, composition and deposition methods of solution-processed flexible MO TFTs see Figure 8, Table S5 and Figure S2 (Supporting Information). Figure 8a shows a timeline of the maximum process temperatures (T max ) during the MO semiconductor fabrication for flexible TFTs as well as the respective substrate materials that were used. Although temperatures well below 400 °C are accessible, there does not appear to be a clear trend for the evolution of the maximum process temperature over time. Rather, T max is dictated by the respective substrate material, which can even go up to 500 °C when, e.g., devices are fabricated on ultrathin flexible glass. [190] Polyimide (PI) is the most commonly used substrate as it still allows TA up to 350 °C, with PEN, PAR, PET and PES following suit ( Figure S2b, Supporting Information). Despite the large range of process temperatures, it is possible to make flexible TFTs with mobilities > 10 cm 2 V −1 s −1 across the whole temperature range, even for an effective T max at room temperature, as was the case for laser annealing process of In 2 O 3 NPs. [143] www.afm-journal. The mobility evolution for flexible solution-processed MO TFTs is presented in Figure 8b grouped by their respective base MO semiconductor. Although there is an overall slight upwards trend over time, there exists a large spread of reported values for all MOs. Indium oxide, ZnO as well as IGZO are the MO materials that are most often employed, with a relative even distribution among them ( Figure S2c, Supporting Information). For each of those, flexible devices with mobilities > 10 cm 2 V −1 s −1 can be identified. Based on this overview, there exist a number of low temperature processing approaches that allow the fabrication of MO TFTs on a variety of flexible substrates. With mobilities above 10 cm 2 V −1 s −1 the base performance of such devices is already sufficient for a lot of applications. However, for long-term and commercial applications, attributes such as mechanical resistance and bias stress stability will have to be a stronger focus of future investigations.

Methods to Improve Resistance to Bending
When devices are fabricated on spin-on PI substrates, the release of the PI film from the glass carrier can cause the devices to roll-up spontaneously and in turn lead to crack formation in the active layers that degrade the device performance. For solution-processed devices, it was found that applying a 400 nm thick PMMA overcoat on 3 µm thick PI substrates before the release procedure helps to prevent such crack formation and leads to devices that can withstand bending to a radius of 1 mm. [178,191] While (poly)crystalline MOs generally are able to achieve higher mobility values compared to their amorphous counterparts, the latter tend to have an advantage when it comes to resistance to mechanical stresses. It was demonstrated that the admixture of small amounts of the insulating polymer poly(4vinylphenol) (PVP) to a nitrate-based precursor could frustrate the crystallization of In 2 O 3 yet still allowed it to achieve a mobility over 10 cm 2 V −1 s −1 . This way, the amorphous In 2 O 3 -PVP hybrid TFTs could retain 90% of their initial mobility after bending of 100 cycles at a radius of 10 mm. [173] The same concept was later extended to a range of In 2 O 3 :polymer blends wherein the amino group content of the polymers was systematically varied between 0% and 12.6%. While the beneficial resistance to bending stress was apparent in all blends, the electrondonating amine character additionally leads to an increased mobility of 31.2 cm 2 V −1 s −1 for the optimal composition. [174] In another hybrid approach to improve the bendability, the addition of graphene nanosheets to an IGZO precursor leads to an improved mobility deterioration of only 8% compared to 70% for IGZO-only devices when bent 100 times at a 70 mm radius. [190] Recently, Le et al. [192] produced hybrid inorganicorganic superlattice structures containing alternating thin MO layers and a phosphonic acid based organic Self-Assembled Monolayer (SAM). The SAMs can act as organic springs in between the MO layers and thus help to distribute mechanical stresses. While such superlattice structures have successfully been demonstrated with conductive Indium Tin Oxide (ITO), insulating Zirconium Oxide (ZrO x ), as well as semiconducting Indium Gallium Oxide (IGO) for the fabrication of TFTs on flexible PI substrates, only the IGO superlattice on top of ALD processed Al 2 O 3 dielectric were reported. Nevertheless, the flexible devices based on the hybrid IGO superlattice showed excellent bending resistance with little change in device characteristics even after 10 000 bending cycles at 1 mm radius. In addition, the same IGO superlattice devices exhibited improved bias stability compared to non-superlattice IGO reference devices.

Vacuum-Processed Flexible Memristors
The memristor is a relatively new special passive element that resembles a MO resistor sandwiched between two metal electrodes with the ability to modify its resistance according to the applied bias across it. This fact allows memory storage in the form of resistance values. The typical memristor architecture is in the form of 2D crossbar arrays, [193] which enables a range of applications for the next generation electronics  such as:Resistive Random Access Memories (RRAM) [194] or inmemory computing. [195,196] The resistance switching in memristors occurs typically due to a formation/rupture of a Conductive Filament (CF) intrinsically in the bulk MO as a result of applied biases. This effect enables a High Resistive State (HRS) and a Low Resistive State (LRS) that can represent for example a digital "0" and "1"; however, multiple states were obtained too. [197] Physically, the resistive switching mechanism behind the CF formation considers an initial electroforming step to force the first CF formation. Then, HRS and LRS can be toggled by rupture and subsequent reconstruction of the filament. The latter can be achieved by Valence Change Memory (VCM) -a CF of oxygen vacancies forms due to oxygen redox reaction according to the bias applied, and Electrochemical Metallization (ECM) -metal ions diffuse from a reactive metal electrode through the oxide film. [198] The switching behavior can be categorized either as analog or digital, each with its own applicability, which will be reviewed in the next sections. Memristors with digital switching provide a consistent delimitation between resistive states with an abrupt switch suitable for representing and storing binary values. Whereas the analog switching presents a continuous conductance modulation suitable for synaptic-like behavior in neuromorphic applications. [199] Mohammad et al. [198] explained in a review article in depth the switching mechanism, structure and challenges of stateof-the-art memristors. Later, reviews based on rigid neuromorphic computing have been reported including crossbar array integration for analog computing. [200,201] Despite the progress of memristors, either in SL or crossbar array architectures, and the increasing interest in flexible electronics, very few reviews on flexible devices have been published to date. So far, in terms of flexible memristive devices, only oxide and organic Non-Volatile Memories (NVM), [202] and more recently crystalline memristors have been reviewed. [203] Additionally, flexible nickel oxide (NiO X ) devices have been generally reviewed. [204] Analog rigid neuromorphic memristors have been reported by Sokolov et al., [205] including several flexible memristor-based synapses.
The subsections below summarize the latest advances brought to analog and digital vacuum-based memristors with an emphasis on their mechanical flexibility. However, the main challenge in flexible MO memristors remains to achieve high switching stability over large fabricated area including more mechanical tests (e.g. stretching), electrical stress bias, or recovery after mechanical damage.

Analog Vacuum-Based Memristors
Analog memristive devices are suitable for a selection of emerging architectures in analog computing as a solution for the bottleneck von Neuman computers such as crossbarbased computing, [206] neuromorphic computing [79] or analog memories. [207] So far, flexible analog memristors have only been reported in neural-inspired computing applications to reproduce synaptic functions in a biological neuron network, where the memory and processing coexist. [79,208] Mechanical flexibility in neuromorphic computing is of great interest as an AI-enabled hardware for the expansion of the IoT. A biological synapse acts as a link between neurons and performs several functions that have been reproduced by flexible memristors in recent papers discussing: Spike-Timing-Dependent Plasticity (STDP), [43,79,209] Long-Term Potentiation (LTP), [57,70,79,210] Short-Term Potentiation (STP), [57,70,79,209,210] Paired-Pulse Facilitation (PPF), [56,57,63,79,210,211] Long-Term Depression (LTD), [56,57,70,79,209,210] forgetting behavior, [57] Excitatory Postsynaptic Currents (EPSC), [56,209,211] and Paired-Pulse Depression (PPD). [63] The synaptic devices have been built typically in an electrode array format (Figure 9a), [79,209,211] but crossbar structures have been demonstrated too (Figure 9b). [210] Both RF-Sputtering [70] and ALD [210] have been used as fabrication techniques; however, the former is less temperature demanding but the latter has more control over the surface morphology, which is suitable for 3D designs. Table S6 (Supporting Information) presents the latest electrical and mechanical memristor specifications in recent research publications.
As a requirement to mimic the brain architecture in computing systems, low power consumption is a significant target due to the high number of interconnected neurons (10 billion) and synapses (10 trillion). [56,211,212] Wang et al. [212] presented a Flexible RRAM (FRRAM) with reduced power consumption during switching by incorporating Ag nanoparticles in the Al 2 O 3 /ZnO stack. This helped to reduce the relative fluctuation between the resistive states from ≈167% to ≈30%, as it can been seen in Figure 9c and it is attributed to a more controlled CF formation of random filaments due to the Ag particles. [56,57,212] Lin et al. [211] reduced the power consumption of ZnO-based flexible memristors to 56 fJ by nitrogen-doping, which acts as a carrier-suppressor still maintaining essential synaptic behavior (Figure 9d). High energy consumption is often required in the forming process for memristor operation. In an effort to reduce the energy consumption, Wang et al. [56] developed forming-free NiOx memristors with the ability to withstand multiple tensile repetitions at 10 mm bending radius. In addition, a dual-layer Ta 2 O 5 /WO 3 -based memristor maintains a partially formed oxygen-redox CF as a seed for lower operating voltages, even at 2 mm bending conditions. [208] High-density neuromorphic synapses have recently been demonstrated in HfAlO x -based flexible RRAM 3D architecture, which could support three stacked layers of synapse arrays as well as multiple resistive states (Figure 9b,e). [210] The synaptic functionality has been maintained in the 3D structure with emphasis on stable LTP/LTD behavior under 10 mm bending strain applied on PET substrates (Figure 9f). [210] Five states resistive switching of flexible MO memristors has been demonstrated by Wang et al., [56] allowing synaptic plasticity, a lower number of fabrication steps by PVD techniques as well as mechanical strain resilience to 10 mm bending radius. These results offer high potential for both RRAM memories and neuromorphic computing as well as in CMOS integration due to conventional fabrication procedures.
In terms of wearability properties, a highly transparent (84.6%) synaptic array has been reported by Liang et al. [209] simultaneously allowing 2000 bending cycles at 10 mm radius. In contrast, it was observed that higher initial bias voltage (100 V) reduces the HfO x grain size that correlates to fewer film fractures after bending. [209] Improvements in neuromorphic www.afm-journal.de www.advancedsciencenews.com

(14 of 24)
© 2023 The Authors. Advanced Functional Materials published by Wiley-VCH GmbH Ta 2 O 5 memristors were achieved by inserting an additional WO 3 layer, enhancing the switching stability (>10 6 retention, > 10 9 AC endurance) under 4 mm bending stress for 10 4 cycles (Figure 9g). [208] The device was successfully tested in neuromorphic applications by employing it in a Hopefield neural network to process a binary image.
It is important to note that fabrication temperatures higher than the melting point of the targeted flexible substrate can be utilized if certain processing schemes are followed. For example, a synaptic device based on Pt/WO x /Ti could be deposited on a NaCl substrate and afterward easily delaminated and transferred onto a variety of flexible substrates for neuromorphic applications. [79] Bending tests showed no synaptic degradation after 100 bending cycles at 15 mm radius using a variety of substrates such as PDMS or printing paper. Yan et al. [63] proposed another high-temperature resistant fabrication employing a mica substrate for IGZO-based neuromorphic memristors processed at 400 °C. The device could withstand higher operation temperatures (300 °C) than previous work, [208] exhibiting PPF, PPD, and STDP synaptic behavior, as well as stable switching.
Overall, the recent studies on flexible analog memristors focused on achieving low-power artificial synapses (e.g., Ag particles, N doping etc.), high density structures (e.g., 3D stacks, or multi-state switching) and switching stability (e.g., using WO 3 interlayer). Simultaneously, the memristor mechanical properties were developed to support high transparency, bending tests up to 2 mm radius, delamination using a sacrificial NaCl layer or higher operating temperature (up to 300 °C) using a mica substrate.

Digital Vacuum-Based Memristors
Digital memristive devices are employed typically in NVM, and digital in-memory computing. [57] In the past 10 years, a number of flexible digital memristor devices based on   [209] Copyright 2021, IOP Publishing Ltd. b) 3D flexible crossbar array (or cross-point) with 3 layers of Pt/ HfAlOx/TaN fabricated by low-temperature ALD on PET substrate. Adapted with permission. [210] Copyright 2021, John Wiley & Sons Australia, Ltd on behalf of UESTC. c) Power consumption during set and reset resistive switching for devices with and without Ag-embedded nanoparticles. Adapted with permission. [212] Copyright 2016, IEEE. d) PPF synaptic response versus pulse time in the Au/ZnO:N/TiN device after N (0-100) bending (left); synaptic weight versus relative spike timing in both flat and bent states (right). Adapted with permission. [211] Copyright 2021, American Institute of Physics. e) Multiple resistive states for a range of switching cycles in a 3D flexible crossbar with HfOx active layer. Adapted with permission. [210] Copyright 2021, John Wiley & Sons Australia, Ltd on behalf of UESTC. f) Synaptic response versus pulse numbers for the 3D-based crossbar. Adapted with permission. [210] Copyright 2020, John Wiley & Sons Australia, Ltd on behalf of UESTC. g) DC endurance of a single-and double-layer Ta 2 O 5 /WO 3 -based memristor for a number of bending cycles. Adapted with permission. [208] Copyright 2021, IEEE.
vacuum-processed MO have been published, a summary of which is presented in Table S7 (Supporting Information). In terms of bending curvature tests, Fang et al. [213] presented a bipolar RRAM of TiN/HfO 2 /FTO on PET substrate that could achieve the smallest bending radius of 1 mm. However, a positive shift in switching voltage for both resistive states has been noticed while reducing the radius from 4 to 1 mm, corresponding to mechanically induced cracks in the FTO film. [212,213] In another study, as shown in Figure 10a (top), the switching of a TiN/ZnO/TiN device happens when a conical conductive filament of oxygen vacancies forms under a positive bias on the TE, and partially breaks near the top interface when a negative bias is applied on TE. However, this causes the CF to lose oxygen ions through the interface, reducing the on/off ratio. To overcome this issue, Al 2 O 3 layers are symmetrically deposited across the ZnO semiconductor (Figure 10a bottom) to preserve the CF in the ZnO layer. As Al 2 O 3 forms a thinner CF due to the lower level of oxygen vacancies, the CF breaks in this layer, which reduces the leakage current, and then maintains the on/off ratio. In addition, the Al 2 O 3 MIM configuration was stable at 4 mm bending test on the on PET (Figure 10b). A more comprehensive mechanical stress was performed under 10 000 bending cycles, maintaining a memristive endurance of 10 000 iterations and stable retention of 10 000 s that is suitable for flexible NVM memories. [214] Stable performance has been reported for unipolar RRAM even at 100 000 bending cycles by [215] using a Nb/Nb 2 O 5 / Au stack on PI tape and an anodic oxidation of the Nb film. However, the devices exhibit low endurance cycles (12), and moderate on/off ratio (100). [215] In terms of optical transparency, Le et al. [65] reported a NiOx memristor with symmetrical AZO electrodes on a mica substrate providing 80% visible light transmittance. The devices perform excellent in retention and endurance even at bending under 6.5 mm for 1000 cycles. However, the high fabrication temperature (400-600 °C) limits the range of potential substrates. Later, Lee et al. [42] reported a flexible crossbar array with a high transparency of 86% fabricated at a much lower temperature 110 °C, on a cross stack of ZnO/ Ag/ZnO and Al 2 O 3 /Ag/Al 2 O 3 bars (Figure 10c). Each dielectricmetal-dielectric stack (DMD) acts as a transparent conductive electrode (TCE), summing up a to a transmittance of 86% for the whole device (Figure 10d), whereas the combined electrodes provide the resistive switching. Apart from the improved transparency, the crossbar required less voltage on switching (V th ≈ 2.4 V), which is suitable for low power memories. Interestingly, Zhang et al. [207] found that an increase in the work function difference between the TE and BE correlates with a reduction in the switching voltage indicating an improvement in the flexible RRAM power consumption, effect observed on a MIM of TiN/HfO 2 /ITO. [216] In conclusion, the latest results on flexible digital memristors focus more on maintaining a stable switching (e.g., by a symmetrical confinement layer of Al 2 O 3 ), [42] reducing power consumption (by increasing the work function between TE and BE) [207] improving transparency (e.g., by using symmetrical AZO electrodes), [65] and reducing fabrication temperature (using cross stack of DMD materials) [42] in an effort to achieve multiple bending under low radius (up to 1 mm).  [214] Copyright 2020, IEEE. b) Al 2 O 3 -based memristor retention curve under bending up to 2.5 mm radius. Reproduced with permission. [214] Copyright 2020, IEEE. c) Crossbar array based on DMD electrodes on PET substrate. Reproduced with permission. [42] Copyright 2019, American Chemical Society. d) Transmittance versus wavelength plot for every electrode used in the DMD structure for the crossbar array in Figure 10c. Reproduced with permission. [42] Copyright 2019, American Chemical Society.

Solution-Based Memristors
Solution-based memristors have a high potential in the electronics industry, due to low-cost and scalable manufacturing, similar to the solution-based TFTs. By tuning the composition in the MO layer and by increasing the number of layers deposited, Martins et al., [217] recently demonstrated IGZO devices with 8 different resistive states and retention up to 10 5 s in air. The fundamentals of solution-based MOs, along with the latest advances on flexible substrates were recently summarized in a review article by Carlos et al. [218] Inkjet-printed AlOx memristors with high reproducibility (95%) and retention time of 10 5 s with up to 4 states have also been demonstrated. [219] In an effort to overcome the high annealing temperatures that are required for the oxide conversion, Xue et al., [220] developed a combustion method for the Mn-ZnO that allowed the memristor fabrication on PEN substrates. Acetylactone was used as a fuel in this exothermic reaction, which allowed the initiation reaction without additional energy. Memristors exhibited low switching voltages (−0.6/0.7 V) with high on/off ratio (2700) along with multilevel storage capability (5 states).
Finally, the integration of solution-based electronics was further demonstrated by Kanao et al. [221] who showed an all solution-processed NiOx ReRAM integrated with a tactile touch sensor and some resistors. They demonstrated successful writing and erasing function in real time measurements.

Advances and Challenges in Rigid and Flexible Memristive Arrays
The standard von Neumann computing presents several limitations in regards to the reduction of energy consumption or in processing latency, which results from the information exchange between the processor and external memory. This computing bottleneck requires the development of alternative architectures that are envisioned to be the base of the new electronics generation. Certainly, both MO memristors and TFTs present high potential in overcoming the stated challenges by virtue of their mechanical flexibility, simple structure, high performance as well as small device area. However, in order to realize practical applications, the resistive memory devices need to be further expanded and integrated in high-density structures as crossbar and 3D structures and operate in multi-state switching. Usually, multi-level RS memristive arrays are currently preferred over 3D structures due to their reduced integration complexity.
Resistive memory arrays could be patterned in several structures as: 1T1R; cross-point -1-resistor (1R) and 1-Diode 1-Resistor (1D1R); 1-Transistor (1T); 1TnR and CMOL (CMOS and MOLecular) memory, each with their own advantages discussed in more details by Chengning et al. [222] Nevertheless, mostly 1T1R and cross-point arrays have been implemented on flexible substrates so far. Although a flexible 1D1R cross-point was demonstrated on PI (Figure 11a), [223] it works only in unipolar operation with a Ni/HfO 2 /Pt MIM, suitable mostly for volatile memories. In short, 1T1R involves a 2D array, easily controllable, made of memristive cells with a corresponding CMOS transistor per cell [224] to suppress the sneak current. However, the smallest transistor area is 6 F 2 [225] which is comparatively larger than the smallest cell area (4 F 2 ) which limits the array scaling to the transistor size. A cross-point array is formed with crossed top and bottom electrodes (BEs) separated by an active MO semiconductor bringing the smallest feature size to 4 F 2 . It can have a bidirectional diode as cell selector in line with the MO (1D1R) [223,226] that reduces sneak current, or it can be selectorless (1R). [42] Despite the area mismatch between the selector and cell, the 1T1R has more potential in flexible electronics due to the MO TFT selector and lower programming voltages than diode selectors. [225] There are several reports of 1T1R memristive arrays on rigid Si wafers both for analog [206,[227][228][229] and digital memristors [224] and they all use CMOS technology for patterning the selector. For instance, a 1T1R digital comparator was demonstrated to be more area-efficient than a CMOS comparator by using only one memory cell, compared to 2 AND, 2 NOT and 1 NOR gates. [228] An in-memory integrated computer chip based on reprogrammable CMOS-RRAM architecture demonstrated VMM computation for neuromorphic AI applications, comprising a 54×108 crossbar RRAM coprocessor and a mixed-signals platform for managing the inputs/output interface. [229] Flexible memristive arrays have also been demonstrated, for instance 1R arrays were reported for NVM purposes, [42] with excellent electrical performance and stability under mechanical bending. Subsequently, the integration of flexible RRAM crossbars with NMOS or IGZO switches have been demonstrated, [193,230] respectively, as the next step toward flexible NVM memories. Kim et al. [230] built the earliest flexible 1T1R structure (Figure 11b), with a NOR functionality, polyimide substrate and high-performance NMOS transistors. Nevertheless, with conventional Si MOSFET technology, it is difficult to achieve mechanical flexibility. In this respect, Lebanov et al. [193] demonstrated a functional monolithic integration of one MO IGZO and TaO X RRAM in 1T1R structure (Figure 11c). Despite the integration of a polyimide substrate and low temperature fabrication, the array was not exfoliated and bended for further tests. A novel approach combines the RS switching with transistor operation in flexible IGZO TFT on PI, with low cost and high density (1T) (Figure 11d). [231] A memristive HfO 2 layer was added to the insulating oxide TFT layer, and RS could occur at each gate-source and drain-source in both IGZO staggered and coplanar structures. The 1T cells were deployed in arrays and were bended for 10 4 cycles and presented good RRAM electrical performance -a switching speed of 50 ns (coplanar), cycling endurance > 10 6 and small set/ reset voltages (2/−1 V); and typical n-type TFT performanceµ FE = 21 cm 2 V −1 s −1 , SS = 120 mV dec −1 and V th = 1/1.2 V (flat/ bended).
There is a great potential in fully flexible 1T1R for the next generation of computing, low-power, faster and denser memories, synapse-array platforms for brain-inspired computing and AI hardware. Considering the addition of resilience against mechanical, thermal and electrical stress, 1T1R could find its place in flexible electronics applications. However, there are several challenges left to be approached. The main challenge is the integration of both devices in a homogeneous and functional memristive array as the RRAM and TFT require a very close operating voltage and rigorous optimized deposition conditions (O 2 /Ar ratio) of the IGZO films to allow the  [232] Moreover, sneak paths, device area efficiency, and cost/bit issues still need to be optimized and addressed. However, the potential integration of 1T1R is promising as deducted from Datta et al. [233] who describe the benefits and a modelling of MO TFT and RRAM integration for in-memory computing based on existing and suitable TFT and RRAM devices that can offer low-power and performant computation systems and even 3D monolithic computing.

Other Applications
Recently, flexible System-On-Chip (SoC) devices have been implemented on plastic substrates using n-type IGZO TFT patterned with conventional NMOS techniques (Figure 11d). [234,235] Emre et al. [234] created a domain-specific flexible processor using 1024 logic gates based on 0.8 µm (channel length) IGZO TFTs for odor classification using machine learning algorithms (Figure 11e). The system is 20-45 times higher in density than other digital flexible ICs based on MO TFTs. Although there were no flexibility tests conducted the chip could show potential for smart packaging, or healthcare systems like food package states or wound-monitoring systems. Similarly, John et al. [235] developed more advanced flexible SoC (including microprocessor, buses, interconnects, ROM and RAM) on 32-bit Arm technology with a 0.8 µm IGZO-base fabricated on an inhouseproduced plastic (Figure 11f). The flexible IC contains the largest number of NAND2 gates (19 334) on a flexible IC known to present and was tested on simple algebraical programs, having potential for conformable and low cost IoT applications.
Adv. Funct. Mater. 2023, 33, 2213762 Figure 11. Diagram of flexible IC including the processing and I/O mixed signals (external circuits) and the memory (memristive array). In addition, the diagram includes several published technologies for implementing both the memory and processing units, ordered from a-f. a) 1D1R I-V unipolar plot and its corresponding schematic circuit of serial resistances for TE, BE, MO and diode. Reproduced with permission. [223] Copyright 2012, The Japan Society of Applied Physics. b) 1T1R diagram based on Al/TiO2/Al memristors and NMOS selector displayed in cross-point configuration. Reproduced with permission. [230] Copyright 2011, American Chemical Society. c) Diagram of a 1T single cell based on IGZO-channel and HfO 2 /SiO 2 insulating/ memristive layer. It behaves both as a TFT with Ti/Ni source and drain, and as a memristor with RS happening between the gate/source and gate/ drain. Reproduced with permission. [193] Copyright 2018, IEEE. d) Domain-specific Standard Operating Procedure (SoP) hardware diagram manufactured on IGZO TFT for odor classification gathered from OTFT sensors. e) SoP diagram of a flexible Arm microprocessor and corresponding peripherals and memory. The RAM and ROM memory could be replaced by a memristive array. Reproduced with permission. [234] Copyright 2020, Springer Nature. f) Flexible System on Chip (SoC) schematic flow diagram with its adjacent components fabricated with 0.8 µm NAND IGZO technology. Adapted with permission. [235] Copyright 2021, Springer Nature.
Additionally, repeated bending tests under 3 mm curvature radius were performed without any damage but no other data was extracted after bending. An interesting note to these technologies is that they could benefit from the RRAM technology in the future by replacing the SoC NAND RAM/ROM memory with flexible RRAM arrays for enhanced memory performance and area efficiency (see a comparative study of emerging memories). [236] Finally, Chang et al. [232] proposed an integration solution of 1T1R by having a bi-layer of IGZO and Al 2 O 3 on both devices and fewer deposition steps which resulted in a retention of 10 4 s for as many as 100 DC cycles. This approach has applicability in memory in-pixel (MIP) displays for lowering the power consumption by storing the image information and reducing the static power on standby.

Conclusions
This review highlights the current advances and challenges to enable flexible metal oxide (MO) 1T1R architectures. The main challenge is the integration of both devices from either vacuum or solution processes that will allow emerging electronic applications such as RRAM memories, neuromorphic computing, sensors and other computing architectures, all on flexible substrates. In terms of flexible substrates (Section 2), polyimide (PI) seems the most preferred choice of substrate due to its high tensile and compressive bending (below 0.5 mm bending radius), its resistance to most processing chemical solvents and as it is enabling relatively high fabrication temperatures (< 350 °C). Also, PET is widely used as a substrate due to its chemical stability, lower cost and better transparency than PI. Recent advances in MO TFTs focus more on improving the electrical performance under mechanical deformation and bias conditions. There is a noticeable ascending trend in researching flexible MO TFT in the last 6 years, although there is no clear evidence of a reduction in the maximum fabrication temperature (according to Sections 3.1, 3.2). Improvements on the vacuum-processed n-type transistor structure using island-TFTs proved to allow devices to withstand 10 000 bending cycles under bending radius of 1.5 mm, where mobility deviated <10% [98] or where stretchability achieved 15%-30% stretch stress. [44] Similarly, it was found that outward bending cause more V th shift (10%) than inward bending (negligible) in ptype SnOx TFTs when a bias stress of 0.8 V was applied for 10 000 s. [125] In solution-processed TFTs (Section 3.3) the challenges are represented by exploring roll-to-roll fabrication techniques and spray processes for large area depositions, [148][149][150] by approaching low temperatures processing using, e.g., nanoparticles instead of precursors altogether, [143,146] exploring novel precursor formulations such as with combustion chemistry [169] or by photonic processing. [140] Moreover, methods to improve resistance to bending have been investigated such as the polymer admixture to precursors in order to frustrate MO crystallization or the application of flexible MO-SAM multilayers. [173,176,189,192] Next, analog and digital memristors are described in Section 3.3, where the highlight is on synaptic response memristors with low power consumption: by incorporating Ag nanoparticles (thus realizing 56 fJ per synaptic event), [211] by nitrogen-doping, [211] or by using a dual layer Ta 2 O 5 /WO 3 -based memristor that also allows mechanical bending of under 2 mm [208] or 10 mm, in a NiOx study. [56] Furthermore, digital memristors were reviewed, emphasizing the effect of: mechanically induced stress resulting in cracks in HfO 2 devices, [213] stabilizing the oxygen ion migration for better switching performance in ZnO memristors, [214] repetitive bending cycles of 10 000 repetitions, [214] transparency improvements in NiOx devices, [65] or power consumption reduction in HfO 2 MIMs. [216,220] Similarly, analog memristors were investigated in Section 3.4, concerning multi-state resistance, [219] reducing annealing temperatures by combustion methods, [220] or integrated solution-processed ReRAM on tactile sensors. [221] Finally, recent rigid and flexible memristive arrays were reviewed in Section 3.5. This includes rigid 1T1R comparators [228] or in-memory integrated CMOS-RRAM computer. [229] In terms of flexible arrays, 1R arrays for NVM purposes were highlighted with excellent electrical performance under bending, [42] 1T arrays with intrinsic resistive switching functionality [231] RRAM and IGZO NMOS integration, or NOR functionality using 1T1R. [230] More flexible applications using TFTs were reviewed in Section 3.6 such IGZO TFTs on plastic foils for flexible ICs or SoC. [234,235] There are further challenges that need to be approached in flexible memristive arrays, such as optimized deposition conditions and integration of both TFT and RRAM in a homogenous structure, avoiding sneak current paths, further mechanical tests and finding a standard methodology for evaluating mechanical flexibility in order to provide emerging computing applications on flexible structures.
Themis Prodromakis holds the Regius Chair of Engineering at the University of Edinburgh and is Director of the Centre for Electronics Frontiers. His work focuses on developing metal-oxide Resistive Random-Access Memory technologies and related applications and leads an interdisciplinary team comprising 40 researchers with expertise across materials process development to electron devices and circuits and systems for embedded applications. He holds a RAEng Chair in Emerging Technologies and is Adjunct Professor at UTS Australia and Honorary Fellow at Imperial College London. He is Fellow of the Royal Society of Chemistry, the British Computer Society, the IET and the Institute of Physics.