Unraveling the Electrochemical Electrode Coupling in Integrated Organic Electrochemical Transistors

Organic electrochemical transistors (OECTs) have gained enormous attention due to their potential for bioelectronics and neuromorphic computing. However, their implementation into real‐world applications is still impeded by a lack of understanding of the complex operation of integrated OECTs. This study, for the first time, elaborates on a peculiar behavior that integrated OECTs exhibit due to their electrolytic environment—the electrochemical electrode coupling (EEC), which has severe implications on the device and circuit performance, causing a loss of output saturation and a threshold voltage roll‐off. After developing a physical model to describe this effect, it is substantiated with experimental data, and the crucial role of the gate electrode is discussed. Furthermore, the impact of the electrode/channel overlap on the saturation in the output curve is evaluated. It is then investigated how its detrimental effect on circuit performance can be minimized, and the optimization of a simple logic gate is demonstrated. This study has fundamental implications for researchers exploring materials and device architectures for OECTs and for engineers designing integrated OECT‐based circuits.


Introduction
Over the past years, organic electronics have attained special interest for low-cost bendable electronics and bioelectronics.For example, organic electronics for smart bioelectronics, which promises combined sensing and subsequent local data computation (i.e., autonomous biosensors), has gained increasing attention and is commonly considered the future of biosensing [1] and low-voltage data processing. [2]Here, organic materials profit, in DOI: 10.1002/adfm.202302205addition to their ability to be fabricated on large areas at low costs, from their potential biodegradability and physiological compatibility.Given the technological challenge and its huge application potential, researchers have been actively looking for different materials, devices, and paradigms for smart bioelectronics. [3,4]n this scenario, the organic electrochemical transistor (OECT) emerged as a possible candidate [5] due to the softness and flexibility of the polymeric layer and its ability to operate at low voltage.Similar to traditional field-effect transistors, OECTs feature a similar three-electrode architecture.However, an electrolyte rather than an insulator separates (and connects) the channel and the gate electrode. [6]Moreover, an organic mixed ion-electron conductor (OMIEC) acts as the channel material, which allows ions from the electrolyte to penetrate the channel. [7]The OECT operation is likewise to that of traditional transistors, that is, by applying a potential at the gate electrode, the channel's conductance is altered.In contrast, the underlying mechanism follows that of electrochemical doping. [6,8]At a single-device level, impressive figures of merit are obtained using OECTs: high transconductance, low threshold swing down to the thermodynamic limit, and good on-off ratio. [9]OECTs operate at low voltages, typically below 1 V, allowing for operation in an aqueous environment.Moreover, material development allowed for the making of both p-and ntype OECTs, in accumulation and depletion mode. [7]In fact, OECTs encompass all the key requirements for bioelectronics: low-voltage operation, mechanical softness, stability in physiological environments, and biocompatibility. [5][17][18][19] While immense progress was achieved in terms of material development for OECTs and OECT-based concepts of smart bioelectronics, the implementation into real-world scenarios is still challenging.The implementation challenge is based on the fact that OECTs are typically characterized by an Ag/AgCl pellet as the gate electrode.This configuration is a very useful way of investigating OECT-based materials, sensors, and AI approaches because the Ag/AgCl pellet can be simply immersed into a liquid electrolyte that covers the channel.During measurement, it undergoes a faradaic reaction with the electrolyte, allowing for efficient gating of the OECT.From the electrochemical standpoint, it provides (or extracts) an infinite amount of ions into (or from) the electrolyte system and is, therefore, an extremely effective gate. [6]owever, to go beyond single device characteristics, using an Ag/AgCl pellet is far from practical implementation into smart bioelectronic circuitry.][22] They replaced Ag/AgCl electrodes with integrated gates that must be patterned on the same substrate.Such gates are typically covered with the same OMIEC material as the channel, which has a finite double-layer capacitance.As shown in OECT-based sensing applications, [23] small changes in the gate chemistry of integrated gates result in the transistor characteristics being altered significantly-a situation not ideal for ICs that require reliable gate operation.Considering the huge potential of OECT-based ICs for smart bioelectronics, it is surprising that integrated gate electrodes in micro-integrated devices have never been explicitly investigated, and a fundamental understanding has so far not been achieved.
Moreover, while Bernards [8] and Friedlein [24] provide models that describe Ag/AgCl-gated OECTs, integrated OECTs lack theories that describe their switching behavior.This becomes especially important for non-ideal device geometries.For example, for analog and digital circuits, one requires faster OECTs, with the operation frequency depending on the specific application.Such an increase in the maximum operation frequency naturally comes with a reduction of device dimensions.For miniaturized devices, the resolution and alignment tolerances of the patterning technique being used (e.g., inkjet or screen printing) need to be carefully taken into account as they will result in significant overlap between the electrodes, OMIEC, and electrolyte.Such overlaps, naturally in contact with the electrolyte, can create significant double-layer capacitances that can impact the OECT's switching behavior.As we will show in this work, OECTs cannot be treated with traditional models, [24,25] and while OECT-based ICs were developed that use either an Ag/AgCl gate pellet [19] or have device dimensions in the millimeter range, [18] an accurate understanding of the electrochemical processes in miniaturized and integrated OECTs is yet to be developed.
In this work, we first disclose a particular effect present in integrated OECTs that has a detrimental influence on the performance of ICs: The electrochemical electrode coupling (EEC) between the channel and the electrode/channel interfaces.We first prove the existence of the EEC and investigate its effect on OECTs, where we find that it creates a shift in threshold voltage with increasing drain-source voltage and poor saturation in the output characteristics in integrated devices.We establish a mathematical framework to explain and predict EEC in electrochemical three-terminal devices.We will then use the model to validate experimental data and, on this basis, optimize the OECT's architecture.Finally, we demonstrate how a strong EEC translates into low gain in logic gates (inverters) and show how to circumvent this problem by appropriate device design.Understanding EEC in three-terminal devices, that is, in OECTs, is utterly important in designing analog and digital integrated circuits.Our results are, thus, highly relevant for the practical implication of OECT-based integrated circuits, and we see this work as a general guideline for both researchers and engineers in the field of electrolyte-gated devices.

Basics of the Electrochemical Electrode Coupling (EEC)
In traditional inorganic and organic semiconductors, free charges are subject to drift under the influence of an external electric field, while dopants are immobile and remain at their position in the lattice of the semiconductor.In OMIECs, this is not the case: The dopants are typically ions, and OMIECs are good ionic conductors.Therefore, both holes/electrons and the ions that mediate the (de)doping of the organic semiconductor are freely moving charges subject to diffusion and drift.When a bias is applied between two electrodes bridged by an OMIEC film, electronic and ionic charges both drift according to their charge and mobility.
In OECTs, holes and electrons are injected from and ejected into the metallic electrodes (g arrow in Figure 1), accounting for the drain current.Ions cannot pass the OMIEC/electrode interface and accumulate there, forming an electrochemical double layer in the entire volume of the OMIEC.That is, it creates an ionic capacitance, an effect that is responsible for the transistor gating (blue arrow in Figure 1).The area of the OMIEC/electrode interface at the source and drain, where ions can accumulate, is negligible in perfectly aligned devices (or devices where the channel length is much greater than the overlap).However, in real devices, the area of the OMIEC/electrode interface is not negligible, and the contact overlap length needs to be considered for a quantitative description of device operation.This overlap constitutes a "sink" that can welcome ions effectively by forming an electrochemical double layer and thus removing them from the film.From a device physics perspective, this description is a capacitive coupling, which we call the electrochemical electrode coupling (EEC); orange arrow in Figure 1.
For simplicity reasons, we first consider a two-terminal device.Such a device, consisting of an OMIEC layer between two electrodes (denoted as the source and drain) immersed in an electrolytic solution, is expected to behave like a resistor.However, as depicted in Figure S1 (Supporting Information), we observe a nonlinear IV curve for a polystyrene sulfonate-doped poly(3,4-ethylenedioxythiophene) (PEDOT:PSS) layer in a solid electrolyte environment.The nonlinear behavior originates from the above-mentioned EEC of the electrolyte with the OMIECelectrode overlap.A negative drain-source voltage drives both holes and cations toward the drain electrode.While holes sink into the drain electrode accounting for the drain current, cations capacitively accumulate at the interface, thus forming an electrochemical double layer.Consequently, charge neutrality across the electrolyte requires the accumulation of anions close to the source electrode.The OMIEC, susceptible to doping by anions, eventually becomes more conductive.Accordingly, the IV curve exhibits a super-linear increase in drain current as a function of the drain voltage.
We prove the change in the PEDOT:PSS doping state, induced by the applied drain-source voltage, optically.As such, we exploit the electrochromic effect of PEDOT:PSS, which is dark blue when lightly doped and transparent when strongly doped.At V ds = 0 V, the PEDOT:PSS channel is dark blue, that is, lightly doped.When we apply a drain-source voltage up to V ds = −2 V, the channel sequentially turns transparent, evidencing the change in the doping state toward strongly doped PEDOT:PSS (see Figure S1, Supporting Information).This impact of the drain-source voltage on the channel doping state as a consequence of EEC was likewise proven by Kim et al. using in situ spectroscopy during the operation of a similar device where they found an increase in the polaron absorption with increasing drain-source voltage. [26]o show the capacitive origin of this effect, we measured the time constant of the current modulation that should not exist in the case of pure resistive contributions.We apply rectangular voltage pulses at the drain electrode while keeping the source electrode on ground.We measure the respective current that flows through the device (Figure S2, Supporting Information) as a voltage drop across a 200 Ω resistor and find that the transient of this two-terminal device behaves like a capacitor that is charged through a resistor.The charging time constant obtained by fitting the transient response is 137 ± 11 ms, which refers to the RC time constant of the electrochemical double-layer capacitance charged through the electrolyte resistance.This transient value is typical for ion-doped OMIEC films with comparable OMIEC dimensions. [27]n top of that, the presence of EEC in two-terminal devices was already highlighted in several works. [26,28,29]In these works, it was praised because it transforms the expected linear current-voltage (IV) curve of an OMIEC resistor in an electrolytic environment into a diode-like IV curve.While electrochemical diode-like devices benefit from the OMIEC-drain overlap providing a gateway for the drain voltage to alter the channel doping state, its detrimental effect on a three-terminal device was never discussed.

EEC Effect in OECTs
Unlike diode-like devices, the ideal transistor, which is a threeterminal device, relies solely on the horizontal gate field to inject doping charges into the channel.In fact, the triode equations for FETs as well as the Bernards model for OECTs [8] do not account for the lateral drain-source field to influence the number of charge carriers in the channel.However, the drain-source voltage may influence the channel in traditional FETs under specific circumstances, especially at very short channel lengths.For example, drain-induced barrier lowering (DIBL) describes the effect of the drain-source field on the charge injection barrier at the source.An elevated drain voltage lowers the barrier and thus enhances charge injection.Eventually, the threshold voltage rolls off, that is, the threshold voltage decreases with increasing drain voltage.Furthermore, DIBL causes the loss of current saturation in the output curve of the transistor with increasing drainsource voltage.
The EEC, inevitably present in OECTs, should lead to a similar observation due to the lateral drain-source field inducing an ionic capacitive coupling between the electrodes.Nonetheless, such effects have not been reported so far.Indeed, we find that there are no EEC-induced effects in Ag/AgCl-gated OECTs (sketched in Figure 2a): Those devices, exhibiting a non-polarizable gate, operate with a constant threshold voltage (Figure 2b) and excellent output saturation (Figure 2c).Hence, the drain-source voltage does not alter the doping state of the channel.This is an interesting finding as it indicates that the ever-present EEC is overshadowed by an ideal non-polarizable gate electrode (and we will explain the origin of this finding in a later part of this paper).The use of such an electrode, often in the form of external Ag/AgCl pellets, however, does not capture the scenario of real-life circuit integration, where the three electrodes constituting a transistor should be patterned on the substrate.Furthermore, Ag/AgCl gates come about with high leakage currents (microamperes, see Figure 2b or Ref. [30]), and they are consumed during device operation, imposing the difficulty to prepare printed gate electrodes with sufficient long-term stability. [31]he integration of the gate electrode in electrochemical devices is often done by structuring a capacitive gate adjacent to the channel, [9,12,[16][17][18][32][33][34] that is, a side-gate configuration. We sho an OECT with such an architecture in Figure S3 (Supporting Information), and it will be the basis of our investigation in this work.These devices possess a side gate that is covered with PE-DOT:PSS (same thickness as for the channel, which is 110 nm for all our devices) to enlarge the gate capacitance, and its area is much larger than the channel area (see micrograph in Figure S3, Supporting Information).Compared to the channel capacitance, the larger gate capacitance accounts for efficient gating.Thus, our PEDOT:PSS transistor switches off below 1 V with the initial threshold voltage similar to PEDOT:PSS devices with an Ag/AgCl gate electrode in aqueous electrolytes.
In such devices comprising an integrated gate electrodeschematically sketched in Figure 2d-we observe both threshold (and turn-off) voltage roll-off (Figure 2e) and loss in output saturation (Figure 2f).In fact, similar to the DIBL in short-channel FETs, the threshold/turn-off voltage roll-off depends linearly on the drain voltage V ds which is discernible in the transfer curve in Figure 2e.In the output characteristics (Figure 2f), the EEC reveals itself in a loss of the saturation regime.In detail, the transistor pinches off, but it loses the output saturation at elevated drain-source voltages, that is, the drain current starts increasing again in the saturation regime.This increase in drain current occurs in a superlinear manner, indicating the induced doping by the drain-source voltage.Hence, unlike the external Ag/AgCl pellet, the integrated gate electrode cannot hide the EEC in OECTs.
This phenomenon can be understood by the capacitive contribution of the drain/electrolyte interface acting as a second capacitive gate electrode.Hence, the drain-source voltage contributes to the effective gate voltage.[37][38] In fact, dual-gate OECTs allow to adjust the threshold voltage by applying a potential at a second gate. [35]This scenario is very similar to the findings in our integrated OECTs, where the drain-source voltage contributes to the gating potential and thus alters the threshold voltage and affects the output saturation.
Since the EEC occurs when using capacitive gate electrodes, we systematically studied the impact of the gate's capacitance on the EEC.Therefore, we fabricated OECTs with various gate sizes while keeping the channel size constant (L = 5 μm, W = 3 μm); a small gate with an area of 47 μm 2 , a medium gate (538 μm 2 ), and a large gate (10600 μm 2 ) while the PEDOT:PSS layer had a thickness of 110 nm for all devices (see Figure S4a, Supporting Information).Hence, the channel capacitance corresponds to 0.2 nF, and the gate capacitances to 0.5, 5.9, and 116.6 nF, respectively.We plot the respective transfer curves in Figure S4b (Supporting Information).As the gate capacitance increases for larger gate electrodes, the on-current goes up, and the turn-off voltage reduces.Such a capacitance-dependent change in the transfer characteristics is expected, [6] and it is the basis of OECT-based biosensing, for example, in metabolite sensors. [39]Subsequently, we investigated the EEC-induced shift in the threshold/turn-off voltage in Figure S4c-e (Supporting Information) for devices with a small, medium, and large gate, respectively.All devices show a significant shift with increasing V ds , ranging from 854 (small gate) to 735 (medium gate) to 657 mV V -1 (large gate).With increasing gate capacitance, the threshold/turn-off voltage shift reduces slightly.Nevertheless, even the large gate OECT, comprising a gate-to-channel ratio of over 700, suffers from the EECinduced shift; that is, the EEC cannot be diminished by further increasing the gate size.
Furthermore, we investigated OECTs that employ different thicknesses of the PEDOT:PSS gate layer, since the PEDOT:PSS' capacitance scales linearly with its thickness.Figure S5a (Supporting Information) compares the transfer curves of OECTs with a gate thickness of 530 and 110 nm, respectively, while the channel PEDOT:PSS remains at a thickness of 110 nm for both devices.The turn-off voltage reduces slightly from 0.8 to 0.7 V for the increased gate thickness.The EEC-induced shift in the threshold/turn-off voltage, shown in Figure S5b,c (Supporting Information), is similar for both devices (897 and 845 mV V -1 ).These observations prove that the EEC is inherently present when using a capacitive side-gate structure in OECTs, and it cannot be eradicated by exaggerating the gate size/thickness in comparison to the channel size.
An infinitely large gate capacitance should, however, act similarly to an Ag/AgCl gate and thus eradicate the EEC.This contradiction might be explained by the phenomenon of current crowding, which is common in field-effect transistors. [40,41]The current crowding leads to the fact that the capacitance of a side gate does not linearly scale with its size.More specifically, charge injection, that is, the establishment of the electrochemical double layer, might not occur homogeneously in the entire contact area of the gate electrode but is rather reduced to a characteristic contact length L T .It is given by L T = √  c ∕(Wr SE ), [41,42] where W is the width of the gate and  c and r SE are the specific contact impedance (in Ωcm 2 ) and the solid electrolyte resistance per unit gate distance (in Ω cm -1 ), respectively.For  c ≫ Wr SE , the entire gate area contributes to the charge injection into the electrolyte.For  c ≪ Wr SE , L T is smaller than the geometrical gate length, and hence only the part of the gate which is closest to the channel can contribute to the capacitance of the gate.In our devices, the specific contact impedance ( c = 3 Ωcm 2 at 50 Hz; C*=100 F cm −3 , d=110 nm) is low in comparison to the electrolyte resistance-width-product (W • r SE = 50 μm• 160 MΩ cm -1 = 800 kΩ).In this example, the characteristic contact length L T calculates to 19 μm.Hence, the effective gate area reduces to WL T , which explains that increasing the gate size further and further does not result in a larger and larger gate capacitance.In order to account for this complex situation, in the model that we develop in the following, we will include the gate capacitance as a free parameter from which one might extract the gate's effective capacitance value in the side-gate configuration.
The EEC is induced by the capacitive OMIEC/drain overlap, and thus, it can depend on the ratio between such an overlap size and the channel size.This ratio becomes unfavorable for small-channel OECTs where the channel size approaches the fabrication resolution.In this case, the overlap lengths on the source and drain electrodes cannot be smaller than the channel itself due to fabrication limitations.Indeed, we observe that the EEC is exacerbated for small-channel OECTs, that is, that the threshold/turn-off voltage roll-off strongly depends on the channel length and their overlap lengths.In our devices, decreasing the channel length tenfold from 30 (overlap length of 10 μ m) to 3 μm (overlap length of 5 μm) leads to a doubling of the threshold/ turn-off voltage roll-off from 414 (millivolt change in turn-off voltage per volt change in V ds ) to 849 mV V -1 (Figure S6, Supporting Information).While the EEC is ubiquitous in integrated OECTs, this observation highlights its special importance for fabricating miniaturized OECT-based ICs.
Another device architecture that exacerbates the EEC in OECTs is the vertical device architecture.The channel length in those devices is usually much smaller than the overlap length of the OMIEC with the electrodes.For example, Lenz et al. reported on vertical OECTs; Their devices show both threshold voltage shift and output saturation loss even though they use a global non-integrated gate electrode. [43]Other groups, such as Yan et al., [44] Travaglini et al., [45] and Jeong et al. [46] observed similar loss in output saturation (Figure S6 (Supporting Information) in Ref. [44]; Figure 2b,d in Refs.[45, 46]) without identifying its origin.In light of these findings, we set out to understand the EEC quantitatively by developing a mathematical framework in the following.

Modeling of the EEC
Although the above-mentioned mechanism of electrochemical contributions can be qualitatively well understood, a systematic quantification and mathematical treatment of the electrode capacitive coupling was never laid out.However, a quantitative model is fundamental to define the important figures of merit of circuit elements.In fact, the lack of understanding of the electrolytic capacitive behavior in both single devices and ICs distinguishes OECTs from more established transistor technologies.In this chapter, we propose a model based on capacitive considerations, which approximates the electrochemical double layer as capacitances.As we will show in detail, our model quantitatively describes the threshold voltage roll-off, fits the output characteristics with good precision, and at the same time, explains why the use of non-polarizable gate electrodes hides the effects of EEC.
Bernard's model [8] provides an equivalent circuit for describing the static behavior of OECTs with ideal non-polarizable gate electrodes.It describes the transistor in light of an electronic circuit between the source and drain and an ionic circuit between the gate and channel.The ionic circuit is characterized by a capacitance C ch , accounting for the electrochemical double layer at the channel, and an electrolyte resistance.In this model, the gate electrode is considered non-polarizable, meaning that the gatesource voltage acts on the channel without losses (except from the electrolyte resistance).
To describe integrated OECTs, we slightly modify Bernard's model from its original form by including a capacitive polarizable gate electrode.It now includes a capacitance between the gate and electrolyte C g , accounting for its electrochemical double layer (see Figure S7, Supporting Information).Note that we do not include the EEC (drain/OMIEC overlap set to zero) for the first approximation but solely a capacitive gate electrode.Furthermore, we only discuss the static device response allowing us to neglect the resistance of the electrolyte.Thus, the electrolyte becomes an equipotential platform and voltage drops only across the capacitances.In static measurements, charge neutrality within the system becomes the driving factor for ion accumulation.The effective gate-source voltage then depends on the ratio between the gate C g and the channel capacitance C ch , sketched in Figure S8a (Supporting Information).As we show in Supporting Information, the drain current in the saturation regime I d, sat alters according to . (1) W, L, and d are the channel dimensions width, length, and thickness; C* is the specific volumetric capacitance of the OMIEC; and V t is the threshold voltage.It turns out that the saturation current depends on V ds -a unique observation for integrated OECTs with its origin in the conductive nature of the electrolyte that connects the source side and drain side of the channel.In fact, the V ds -dependence scales with the fraction of the channel capacitance over the gate capacitance.This finding highlights the importance of a maximized gate capacitance (i.e., C g ≫ C ch ), not only for efficient gating but also in order to retain output saturation.We visualize this result in Figure S8b,c (Supporting Information) where we plot the output characteristics with various C g /C ch -ratios for both an enhancement mode and a depletion mode OECT, respectively.
The equation above will be the starting point for the description of the EEC as follows: We extend the model by two capacitances on both the source C s and drain C d to account for the EEC.This results in the equivalent circuit shown in Figure 2d (bottom).As we thoroughly derive in Supporting Information, the drain current in the saturation region becomes where the sum of all double layer capacitances in the system is We provide a visualization of the model in Figure 3a.The first part of our model equation includes the well-known quadratic dependence of the saturation current on V gs .This part of the model accounts for the electric field between the channel and the gate electrode.It describes the gating effect, and its prefactor C g /C total (marked in red) can be described as the gate strength.The second part of the equation describes the saturation drain current dependence on V ds -the consequence of the EEC.Its prefactor (C ch + 2C d )/C total (depicted in blue) quantifies the EEC strength, that is, how large the impact of the drain-source voltage is on the saturation current.That being the case, a high EEC strength results in poor output saturation.Note that this equation also predicts the shift in the threshold/turn-off voltage with increasing V ds , however, in the following, we shall focus on the output saturation current.
Physically speaking, the capacitive gate electrode provides a limited number of ions to the ionic system.Ions in the channel and in the electrolyte will distribute according to the capacitances of the electrochemical double layers at the source, drain, and channel and their respective potentials.This means, for example, that the drain-source voltage also significantly influences the effective gating voltage, even in the saturation regime.In more detail, the number of ions provided for doping the channel depends on the voltages applied at the gate, drain, and source.
We evaluate the usability of our model by fitting output curves of integrated OECTs.As shown in Figure 3b, the model provides an excellent fit to the measured data.Furthermore, we prove the universality of our model by fitting output characteristics of OECTs with various device dimensions, where we achieve fine results (see Figure S11, Supporting Information).Furthermore, the fit parameters excellently coincide with our real device parameters.For example, the fit shown in Figure 3b predicts values for C ch, fit , C d, fit , C s, fit , and C g, fit of 0.55, 0.28, 0.28, and 3.10 nF, respectively.This is in very good accordance with capacitances The EEC strength (extracted from the output curve fit, that is, a performance parameter) as a function of the normalized drain/OMIEC overlap length (drain/OMIEC overlap length divided by the channel length, that is, a device dimension parameter).The EEC diminishes for a minimized drain overlap length, allowing us to control the EEC.d) Comparison of the output curves of two devices (with the same channel length L=30 and width W=50 μm, and an identical polarizable gate electrode) with a drain/OMIEC overlap length of 6 and 120 μm, respectively.The output saturation is restored for the OECT with the small drain overlap length.
derived from the device's dimensions, that are, C ch, dev =0.55 nF (L=10 μ m, W=5 μ m, d=110 nm, and the volumetric capacitance of PEDOT:PSS that we obtained from impedance measurements is approximately 3 ), and C s, dev =0.28 nF (L o, s =5 μm, W o, s =5 μm, d=110 nm, C*=100 F/cm 3 ).Moreover, we evaluate the EEC in the output curve of devices with various gate sizes.Figure S12a-c shows the output curves for a small gate, medium gate, and large gate OECT, respectively (device dimensions are depicted in Figure S4a, Supporting Information).The larger the gate size, the better the output saturation.In numbers, the EEC reduces from 0.80 for the small gate OECT, to 0.61 for the medium gate OECT, to 0.47 for the large gate OECT.Thus, a large-area side gate improves the output saturation, however, it does not obliterate the EEC entirely, probably due to the abovedescribed current crowding.In fact, we extract the effective sidegate capacitances to be 0.5 nF (0.5 nF from geometrical considerations), 2.0 nF (5.9 nF from geometrical considerations), and 4.0 nF (116.6 nF from geometrical considerations) for the small, medium, and large side gates, respectively.
On top of describing the behavior of integrated OECTs with precise accuracy, our model provides an explanation for the overshadowing of the EEC by non-polarizable gate electrodes such as Ag/AgCl pellets: Ag/AgCl pellets undergo a faradaic reaction with the electrolyte upon application of a gate-source voltage.This means that such an electrode releases an infinite amount of ions into the electrolyte (until the pellet is consumed).In other words, the number of ions necessary to charge the capacitances at the source, drain, and channel is entirely provided by the gate electrode.Its capacitance value C g approaches infinity, and the equivalent circuit reduces to the one shown in Figure 2a (bottom).Hence, using an Ag/AgCl pellet, that is, for C g ≫ C ch , C d , C s , our model approaches the well-known triode equation and EEC is diminished.This prediction is entirely conclusive with our experimental observations, reported in Figure 2c, where perfect saturation is seen in the saturation regime in the output characteristics, that is, no impact of the EEC.
To obtain saturation in the output characteristics, which is the key for many analog and digital circuits (e.g., to maximize the gain of logic inverters or design a constant current source), the EEC must be minimized-a difficult task for integrated OECTs.Especially in miniaturized devices, the required short channel length sets a challenge to align the OMIEC channel with the source and drain contacts.The overlap resolution depends on the OMIEC's structuring method and the accessible equipment but is usually in the micrometer range.As we demonstrated before, such overlap lengths are sufficient to establish a significant double-layer capacitance on the drain electrode that eventually results in a large EEC strength-a parameter we aim to control to achieve good output saturation.
On these premises, we set out to design optimal electrochemical transistors and show that we can control the EEC strength (and thus the output saturation) by optimizing the overlap length on the drain electrode.In Figure 3c, we plot the EEC strength (i.e., a performance parameter) that we get from the fitting of experimental data as a function of the normalized drain overlap length L ov, d /L ch (i.e., a device dimension parameter).We find that a reduced normalized drain overlap length dramatically decreases the EEC strength.This effect has profound implications for the control of the output saturation: As we reduce the drain overlap length to a minimum, we achieve the best saturation.We exemplarily provide proof for this finding in Figure 3d, where we plot the output curve of two devices with a drain overlap length of 6 and 120 μm, respectively (L=30 μm, W=50 μm).The poor saturation in the large-overlap device rigorously turns into a good saturation in the device with a small overlap.

Optimized Integrated OECT-Based Inverters
In light of these findings, we produce unipolar inverters using our optimized design for integrated OECTs.Inverters are fundamental building blocks in any digital circuitry.Their gain is directly proportional to the output resistance of the single device in saturation.This dependency allows us to optimize the gain by minimizing the drain overlap as follows: Our devices are based on PEDOT:PSS, that is, depletion-mode devices, and thus we opt for a 3-resistor inverter structure depicted in Figure 4a.We employ devices with various EEC strengths as drive transistors, all of them shown in Figure S11 (Supporting Information).As such, we obtain proper inversion of the input voltage (Figure 4b).We plot the gain of the inversion, referred to as the steepness of the inverter curve, in Figure 4c.The gain directly depends on the EEC strength, see Figure 4d.This means, that our knowledge of the EEC allows us to control and optimize integrated OECT-based inverters.Facing the trade-off between inverter gain (i.e., circuit performance parameter) and the drain overlap (i.e., device design parameter), the drain overlap should be chosen approximately five times smaller than the channel length.
Note that the gain remains quite low (below 5) even for high output resistances in the input devices.This observation is attributed to the unfavorable inverter topology rather than to the EEC impact. [20,21]Inverters with enhancement-mode OECTs or in particular complementary inverters, exhibit a tremendously higher gain [18,47] and we expect the EEC to have an even greater impact on those devices.Nevertheless, the fact that the EEC of integrated OECTs is directly reflected in the inverter gain lights up the importance of both the awareness of its presence in single devices and the understanding of its importance for OECTbased circuitry.

Conclusion
Electrochemical transistors are gaining enormous attention due to their potential of using them in biological environments with low-voltage operation and efficient ionic-electronic transduction.While this ionic affinity is highly praised for in-vivo applications, biosensing, and neuromorphic computing, its detrimental effect on circuitry is rarely considered, especially in making complex integrated circuits (ICs).As we showed in this work, the fabrication of integrated OECTs reveals a disadvantage in using an electrolyte: The drain potential impacts the doping state of the channel.We reported for the first time that the conductive nature of the electrolyte mediates between the potentials at the gate, source, and drain in OECTs through the electrochemical electrode coupling (EEC).We verified the existence of the EEC, a feature already used to produce electrochemical diodes, but with little understanding of its physics and implications for transistors.
Many groups evaluate their research on fairly large OECTs with a channel length of hundreds of micrometers and/or with a non-polarizable Ag/AgCl-gate, a situation unsuited for recording and analyzing real-time bio-signals or doing computation.Integrating OECTs into real-world ICs requires structuring the gate electrode on the same substrate as the channel.We demonstrated that such integrated devices, especially combined with the miniaturization of the channel for enhanced device speed, come about with the EEC inherently impacting the device's operation.As such, the EEC causes a threshold voltage roll-off and a loss in output saturation.We substantiated this finding with data and showed that miniaturization of the channel length close to the fabrication resolution amplifies the detrimental effects of the EEC.While the EEC is inherently present in integrated OECTs, our data confirmed that using an Ag/AgCl pellet as the gate electrode prevails the EEC, leading to ideal transistor characteristics.
To quantitatively understand the EEC's implications on the OECT operation, we set out to develop a mathematical framework: Our capacitive model provides a simple but powerful description of the EEC and provides excellent fit results of output curves from devices with various device dimensions.The model takes into account the channel area, the gate area, and the overlap lengths of the OMIEC on both the source and the drain electrode.Moreover, our model explains how the use of Ag/AgCl pellets as gate electrodes overshadows the EEC in non-integrated devices.
Finally, we used this knowledge to fabricate OECTs with minimized drain overlaps, which allowed us to reduce the EEC to a minimum, restoring output saturation successfully.We demonstrated the significance of this procedure by fabricating a small piece of integrated circuitry: We produced inverters based on OECTs of various channel/drain length overlap ratios.By enhancing its inversion gain with simple geometrical adjustments, we exemplified that our knowledge of the EEC allows us to significantly improve the inverter performance.
Limitations of this model can emerge from its underlying assumption that the OMIEC/electrolyte interface is considered purely capacitive while its voltage dependence is neglected.The full picture can be grasped by extending the model by means of thermodynamic laws that include enthalpic and entropic considerations, as we have published before for Ag/AgCl gated OECTs. [48]However, this would go beyond the scope of this work, and the beauty of the capacitive model is its simplicity.In fact, it introduces a simple yet powerful tool to understand a major electrochemical effect in integrated OECTs that has momentous significance for their operation in ICs.As the field of OECT re-search moves toward circuit integration, EEC cannot be ignored, and many research groups will face its impact on circuit performance.This work is a first step toward understanding and controlling EEC for integrated OECTs, and provides a guideline for future work to improve OECT performance for ICs as the field of OECT-based ICs is just emerging.
Electrical Characterization: Transistor characteristics were recorded in a N 2 -filled glovebox using two Keithley 236 SMUs controlled by the software SweepMe! (sweep-me.net).Transfer characteristics were measured by sweeping the gate voltage, keeping the source electrode grounded and the drain electrode fixed at a constant potential.Output characteristics are measured by sweeping the drain voltage, keeping the source electrode grounded and the gate electrode fixed at a constant potential.Transient measurements were conducted with an HP 8114A pulse generator and an HMO3004 oscilloscope (Rohde & Schwarz).While keeping the drain electrode fixed at a constant potential and the source electrode on ground, the gate voltage was altered by the signal generator.The input signal at the gate electrode followed a rectangular pulse with an amplitude of 2 V, an offset of -1 V, and a frequency of 1 Hz.The output voltage was recorded across a 200 Ω resistor.Impedance measurements were carried out with a Metrohm Autolab PGSTAT302N potentiostat/galvanostat (Metrohm AG).Source and drain were short-circuited and measurement was run in potentiostatic mode with a root mean square amplitude of 0.01 V. Equivalent circuit modeling of the impedance data was performed with the software ZView.

Figure 1 .
Figure 1.Electrochemical electrode coupling (EEC).In integrated OECTs, the potential at the drain initiates an ion distribution between the drain and source electrode that results in the EEC.The transistor consequently shows a threshold voltage roll-off in the transfer characteristics and a loss of saturation in the output curve.

Figure 2 .
Figure 2. EEC in OECTs with a non-polarizable gate electrode (top row) and a polarizable gate electrode (bottom row).a) OECT sketch with a nonpolarizable Ag/AgCl pellet electrode with its respective circuit model with EEC, and the corresponding b) transfer characteristics and c) output curves.d) OECT sketch with a micro-integrated polarizable OMIEC gate.The EEC manifests itself in such devices e) in a shift of threshold/turn-on voltage in the transfer characteristics and f) in a loss of the saturation regime in the output curves.The devices in the bottom and top rows have the same channel dimensions (W=50 μm ,L=30 μm) and overlap length on source and drain (L o =10 μm).The device in the top row employs a liquid electrolyte and the Ag/AgCl pellet gate electrode, whereas the device in the bottom row has an integrated gate and a patterned solid electrolyte.

Figure 3 .
Figure 3. Modeling and optimizing EEC in OECTs.a) The capacitive model of the EEC in OECTs with an integrated gate electrode.The red arrow indicates the ion movement between the gate and channel that accounts for the gating effect.The respective gate strength in the model is highlighted in red.The blue arrow denotes the ion movement due to the EEC.The associated EEC strength in the model is marked in blue.b) Output characteristics of an integrated OECT (L=10 μm, W=5 μm, L o =5 μm).The data (circles) is fitted with our model equation (black line) with excellent precision.c)The EEC strength (extracted from the output curve fit, that is, a performance parameter) as a function of the normalized drain/OMIEC overlap length (drain/OMIEC overlap length divided by the channel length, that is, a device dimension parameter).The EEC diminishes for a minimized drain overlap length, allowing us to control the EEC.d) Comparison of the output curves of two devices (with the same channel length L=30 and width W=50 μm, and an identical polarizable gate electrode) with a drain/OMIEC overlap length of 6 and 120 μm, respectively.The output saturation is restored for the OECT with the small drain overlap length.

Figure 4 .
Figure 4. EEC in electrochemical inverter circuits.a) The inverter structure for depletion mode OECTs.We hold V dd at 1.2 V and scan V in from 0 to 0.6 V. b) Inverter output for devices with various EEC strengths, that is, with varying saturation in their output curves, and c) the respective inverter gain.See the output curves of the employed devices in Figure S11 (Supporting Information).d) Inversion gain as a function of the EEC strength in the input device.This shows that controlling the EEC strength in integrated OECTs allows for optimizing the inverter gain.