Heterogeneous Functional Dielectric Patterns for Charge‐Carrier Modulation in Ultraflexible Organic Integrated Circuits

Flexible electronics have gained considerable attention for application in wearable devices. Organic transistors are potential candidates to develop flexible integrated circuits (ICs). A primary technique for maximizing their reliability, gain, and operation speed is the modulation of charge‐carrier behavior in the respective transistors fabricated on the same substrate. In this work, heterogeneous functional dielectric patterns (HFDP) of ultrathin polymer gate dielectrics of poly((±)endo,exo‐bicyclo[2.2.1]hept‐ene‐2,3‐dicarboxylic acid, diphenylester) (PNDPE) are introduced. The HFDP that are obtained via the photo‐Fries rearrangement by ultraviolet radiation in the homogeneous PNDPE provide a functional area for charge‐carrier modulation. This leads to programmable threshold voltage control over a wide range (−1.5 to +0.2 V) in the transistors with a high patterning resolution, at 2 V operational voltage. The transistors also exhibit high operational stability over 140 days and under the bias‐stress duration of 1800 s. With the HFDP, the performance metrics of ICs, for example, the noise margin and gain of the zero‐VGS load inverters and the oscillation frequency of ring oscillators are improved to 80%, 1200, and 2.5 kHz, respectively, which are the highest among the previously reported zero‐VGS‐based organic circuits. The HFDP can be applied to much complex and ultraflexible ICs.


Introduction
Flexible electronics have gained considerable attention in the development of next-generation electronic devices for wearable or implantable healthcare monitoring, [1][2][3][4][5][6][7][8] and memory or energy storage, [9,10] which are accompanied by the exponentially increasing demands of the Internet of Things technology. Flexible devices exhibit multifunctionality and their applicability speed, the modulation of the behavior of charge carriers in the respective transistors on the same substrate is desired because it improves the degree of freedom of the circuit design. This can be achieved by providing functional area patterns for charge-carrier modulation. In the previous studies, the V th of the transistors has been controlled by introducing additional gate structures, [19,20] the self-assembled monolayer or oxygenplasma treatment, [21][22][23][24][25][26] and functional dielectric doping. [27,28] However, these techniques are often hindered by the complicated fabrication process or low patterning resolution during the formation of the charge-carrier modulation field. A simple and high-resolution patterning process is essential because ICs typically have hundreds of logic gates and transistors.
Photoinduced surface modulation is a promising technique that can be used to obtain functional area patterns for chargecarrier modulation. The patterned area is obtained by the ultraviolet (UV) irradiation of photoreactive polymers through a shadow mask, which enables V th control in the respective transistors on the same substrate. The photoinduced surface modulation method provides a simple patterning process because the patterned area is obtained by transforming the homogeneous functional dielectric structures into heterogeneous structures via photochemical reactions through the UV treatment. Furthermore, this method potentially improves the patterning resolution to be as small as a few hundreds of nanometers, which corresponds to the half-wavelength of UV radiation. Only a few studies have reported techniques that modulate the charge carriers via photoinduced surface modulation; [35,36] moreover, the efficacy of these techniques are hindered by hysteresis characteristics, high operational voltage, and complicated modulation processes.
This paper presents heterogeneous functional dielectric patterns (HFDP) using poly((±)endo,exo-bicyclo[2.2.1]hept-ene-2,3-dicarboxylic acid, diphenylester) (PNDPE) as the polymer gate dielectrics. PNDPE layers have already been used in previous studies as the gate dielectric in p-and n-channel based OTFTs. [16,37,38] However, in these studies, either rigid glass substrates or very thick PNDPE layers as much as a few µm were used; in addition, ICs were not fabricated. This study demonstrates the HFDP for V th control in OTFTs on the same substrate for high-performance ICs with the use of ultrathin PNDPE gate dielectrics. PNDPE transforms its chemical structure from an aromatic ester to ortho-hydroxyketones through the photo-Fries rearrangement. [37][38][39][40][41][42] In PNDPE gate dielectrics, the charge-carrier modulation is obtained by the heterogeneous molecules of aromatic ester and ortho-hydroxyketones that act as the functional patterns. This results in the programmable V th control of the respective transistors on the same substrate. Additionally, hysteresis-free transistor characteristics are obtained as this process does not use photoinitiators. Furthermore, PNDPE, owing to the catalytic ring-opening metathesis polymerization, forms dense, uniform, and ultrathin gate dielectrics. As a result, low operational voltage and high transconductance are achieved. The PNDPE-based transistors are further implemented in ultraflexible ICs to maximize their performance.
In this work, HFDP are obtained with a high resolution of less than 18 µm. The V th of the PNDPE-based transistors is precisely and programmably controlled over a wide range, from −1.5 to +0.2 V at an operational voltage of 2 V, by varying the dose of the UV treatment. This indicates that both the enhancement and depletion transistors are selectively fabricated on the same substrate, which is crucial for tuning the ICs. Furthermore, dense, uniform, and ultrathin PNDPE gate dielectrics of 14 nm supported by a 6 nm thick AlO x layer are achieved with this process. To demonstrate that the HFDP maximize the performance of ICs, 21 zero-V GS load inverters and a ring oscillator including 48 transistors are fabricated, in which the V th of the respective transistors is spatially controlled with the UV treatment. Consequently, noise margin, amplification gain, and propagation delay of the zero-V GS load inverters are improved to 80%, 1200, and 200 µs, respectively. Additionally, the oscillation frequency of the ring oscillator circuit is a maximum of 2.5 kHz, at a supply voltage of 2-4 V. These performances are the highest in the previously reported zero-V GS -based organic circuits. The HFDP demonstrated in this study can be applied to more complex and ultraflexible ICs for signal processing. Figure 1a shows the chemical structure and the photoreaction of PNDPE. The preparation of PNDPE was found out to be sustainably scalable, wherein multigram quantities with 73% yield and adequate atom economy can be synthesized at the laboratory level. The synthesis of PNDPE is based on the information presented in a previous report. [42] PNDPE contains an aromatic ester group which reacts with UV light through the photo-Fries rearrangement or radical coupling. The chemical structure of 20% of the total amount of PNDPE is rearranged into orthohydroxyketones and other products such as phenol, while the remaining 80% undergoes radical coupling for cross-linking. [42] These ortho-hydroxyketones and phenol contribute to the V th shift of the transistors. [37] The PNDPE-based bottom-gate, and top-contact OTFTs are fabricated as shown in the right part of Figure 1b. A 1 µm thick ultraflexible parylene substrate is used in this study. The processes are described in detail in the experimental section and Figure S1, Supporting Information. PNDPE is dissolved in anisole as shown in the inset of Figure 1b. Since anisole, being a low-viscosity solvent, is suitable for printing processes, for example, ink-jet printing, a sustainable fabrication process is expected owing to the minimum wastage of the material. In addition, its solution is visibly transparent because its absorption occurs in the UV range. [41,42] This transparency is potentially useful in the application of imperceptible electronics. [43] In this study, the PNDPE solution is spin-coated to form ultrathin gate dielectrics, in which the thickness is 13.6 ± 0.5 nm (the number of sample: N = 9) on an aluminum gate electrode, which is anodized to form an AlO x layer (thickness: 6 nm). The thickness of each layer was determined through the capacitance measurement (more details are mentioned in Section 4). The PNDPE gate dielectrics are then treated with UV lamp under N 2 gas, as shown in the left part of Figure 1b. As shown in Figure S2, Supporting Information, the capacitance slightly increases with the UV irradiation (0.60 J cm −2 ) because the dielectric constant of PNDPE changes with the chemical structure. [38] Subsequently, dinaphtho[2,3-b:29,39-f]thieno [3,2-b] thiophene (DNTT) and the gold source and drain electrodes are thermally evaporated through a shadow mask. An optical image of the fabricated transistors is shown in Figure 1c, in which the channel length (L) and the channel width (W) of transistors are L = 50 µm and W = 500 µm, respectively.

Results and Discussion
The electric characteristics of the pristine and UV-treated transistors are measured to validate the charge-carrier modulation, that is, the V th shift, through UV treatment. The electric measurements are performed under ambient and dark  conditions, unless otherwise noted. The transfer curves of the ten transistors in Figure 1d indicate that the V th of the transistors is shifted under the UV treatment with negligible hysteresis and low characteristic variation. Additionally, a high on-off ratio of over 10 5 is obtained independent of the UV treatment. The output curves in Figure S3, Supporting Information, also indicate negligible hysteresis, independent of the UV treatment. An ohmic contact is obtained with both the pristine and UV-treated transistors. In this study, V th is calculated using the extrapolation method in the saturated region from the square root drain current ( DS I ) plots (dashed lines in Figure 1e). Here, the calculated V th does not exhibit a significant error, considering that the reliability factor is ≈80% (the calculation of the reliability factor has been mentioned in Section 4). As shown in Figure 1f, the gate current (I GS ) is maintained in the order of pA, with and without UV illumination. Since I GS is attributed to the displacement current and leakage current, the contributions of these currents to I GS were investigated as shown in Figure S4, Supporting Information. The contribution of the displacement current can be estimated by increasing the measurement delay time. We estimated the displacement current at V GS = −2 V, and it is ±2 pA in the pristine and ±30 pA in the UV-treated transistors. Furthermore, since the leakage current significantly increases at V GS = +2 and −4 V, the leakage current is estimated at most ≈15 pA in the pristine and ≈300 pA in the UV-treated transistor. Here we note that the estimated leakage currents include displacement current, but its contribution is up to 15% from the above estimations. Also, although the increase in I GS implies that the UV illumination slightly degrades the dielectric properties, it does not significantly affect the transistor operation. The steep displacement current, which is the indication of turn-on voltage V on , is observed at V GS = +1.0 and −1.1 V, with and without UV treatment, respectively. Additionally, V th shifts from negative to positive, as indicated by the dashed lines in Figure 1e. Therefore, both the depletion and enhancement transistors are obtained by using charge-carrier modulation, originating from the photo-Fries rearrangement in the PNDPE gate dielectrics. In the practical IC fabrication, the preparation of both types of transistors is desirable on the same substrate, that is, the enhancement transistors is crucial in switching, and the depletion transistors is useful for analog and digital circuits. [44] One of the main advantages of this technique is that it enables the formation of patterns for charge-carrier modulation with high patterning resolution. Fourier transform infrared spectroscopy (FT-IR) imaging is performed to analyze the resolution of the HFDP. Figure 2a shows the optical image of a shadow mask patterned in the form of the logo of Osaka University used for the UV patterning process. Figure 2b,c shows the corresponding FT-IR images of the PNDPE films that are constructed at the absorbance at 1750 and 1630 cm −1 , which originate from the vibrations of the typical CO stretch of the ester units and the ortho-hydroxyketones, respectively. [  decrease in the ester units and the formation of ortho-hydroxyketones under UV treatment (0.8 J cm −2 ) are observed in the FT-IR images. The contrast in the intensity between the pristine and UV-treated areas is distinct, and the signal intensities of both the areas are uniform, which qualitatively indicates that each area is stoichiometrically uniform. The decrease in the ester units and the formation of the ortho-hydroxyketones are also verified by the FT-IR spectra, as shown in Figure 2d, where ≈30% of the aromatic ester is transformed into ortho-hydroxyketones or has experienced radical coupling considering the decreased absorbance peak at 1750 cm −1 from 0.032 to 0.022. Only a fraction of the PNDPE films react with the UV radiation at the dose of 0.8 J cm −2 because this peak almost disappears owing to the nearly complete photo-Fries rearrangement or the coupling. [41,42] The absorption peak at 1197 cm −1 is also typical of ester units, and the peaks at 1491 and 1592 cm −1 are typical of aliphatic groups, which are also decreased by rearrangement or radical coupling. The patterning resolution is analyzed using the expanded FT-IR image, as described in Figure 2e. The expanded images are constructed at 1750 cm −1 for better contrast. Figure 2f shows the line profile of the absorbance along the black line in Figure 2e. The fitted line is drawn from the slope of the intensity change and the patterning resolution is calculated by measuring the distance from the maximum to minimum intensity. Consequently, the patterning resolution is estimated to be 18 µm. Since the spatial resolution of the measurement method is limited to a value as low as ≈6 µm, the resolution of the HFDP can be assumed to be less than 18 µm. It should be noted that the resolution is limited, in particular, by the thickness (20 µm) of the metal shadow mask. The patterning resolution can be further improved by using collimated UV light, a photomask, or by introducing electron beam lithography. The maximum patterning resolution is expected to be in the sub-micrometer or even nanometer regime. [37] Another advantage is that the V th is programmably controlled by varying the UV dose during the fabrication process. The transfer curves of 10 transistors are measured with different doses and the V th is then calculated from the DS I plots. Figure 3a shows the dependence of V th on the treatment time (dose), and Figure 3b shows the typical transfer curves for the respective doses. The reliability factors are more than 75% for all the transistors at different doses, as shown in Figure S5, Supporting Information. V th is precisely and programmably controlled over a wide range, from −1.5 to +0.2 V at V DS = −2 V with a low standard deviation within the range of 10-70 mV. The low variation of the pristine and UV-treated transistors is also confirmed from the histogram of V th as shown in Figure  S6, Supporting Information. The V th control over the wide voltage range further implies that both enhancement and depletion transistors with low-voltage operation can be fabricated using charge-carrier modulation via the photo-Fries rearrangement with the PNDPE gate dielectrics. Here, it can be noted that the V th shift is saturated at a dose of 0.8 J cm −2 , while the decrease in the CO bond is only 30% at the same dose, as shown in Figures 2d and 3a. Since the carrier transport is more affected by the interface than the bulk of the gate dielectrics, this suggests that the photo-Fries rearrangement of the surface of PNDPE gate dielectrics is saturated at this dose, and the untreated PNDPE is present in the bulk of the gate dielectrics.
The stable operation of ICs under low-voltage conditions is the most crucial characteristic for practical IC applications. Returning the V th to its original value during long-term usage is not desirable for practical applications. Since PNDPE reacts with UV light even after the fabrication, V th can possibly shift upon exposure to white light, which is used on a daily basis. The transistors exposed to a white light-emitting diode (LED) were stored over a period of 143 days and the unintended V th change (δV th ) was measured to determine the effect of the exposure of the transistors to the white LED. Figure 3c presents the result of the LED exposure test obtained by plotting the relation between δV th and the term under exposure to the white LED. The spectrum of the LED is shown in Figure S7, Supporting Information. δV th = 0, as indicated by the dashed lines in Figure 3c, is defined as the average V th of the first 10 days because it fluctuates slightly under the different measurement conditions, for example, room temperature and humidity. The δV th values after 143 days were 300, 200, and 60 mV at 0, 0.25, and 0.60 J cm −2 , respectively. The UV-treated transistors do not change the V th even under LED illumination, although a slight increase in the V th is observed in the pristine transistors, which can be attributed to their reaction with the UV contained in the LED. The shelf-life stability of the transistors, that is, the ones stored under dark conditions, is also measured as shown in Figure S8, Supporting Information, which indicates the stability of the V th of the transistors, both with and without UV treatment over 143 days, although there seemed to be a slight V th change for the samples with a UV-dose of 0.6 J cm −2 . Therefore, semipermanent V th control is achieved by using the PNDPE-based transistors. This is attributed to the irreversible charge-carrier modulation via the photo-Fries rearrangement, which is completely different from memory devices such as the floating gate structures which temporally shift V th through charge injections in the additional gate structures. [45] The bias-stress stability of the pristine and UV-treated transistors is also analyzed. Figure 3d shows the correlation between the stress duration and I DS , which is normalized at the initial measured time. Transistors with parylene (thickness: 25 nm) and SiO 2 (thickness: 300 nm) gate dielectrics are also measured for comparison. The applied gate electric field is comparable with all gate dielectrics (PNDPE: 2.1 MV cm −1 , Parylene: 1.9 MV cm −1 , SiO 2 : 2.0 MV cm −1 ) to eliminate the effect of the thickness difference. High stability of the normalized I DS = 90% is observed after 1800 s in the PNDPE-based transistors independent of the dose, while normalized I DS = 50% and 180% are observed in case of SiO 2 -and parylene-based transistors, respectively.
Further details of the bias-stress stability can be discussed from the deep trap density of state (DOS) at the interface. The increase in the deep trap DOS deteriorates the bias-stress stability by decreasing the normalized I DS because once the holes are deeply trapped at the donor states, they are not easily released and do not contribute to the transport. Bare SiO 2based transistors have been widely demonstrated to exhibit deteriorated bias-stress stability, which is also observed in this experiment. In the case of parylene-based transistors, the biasstress stability is deteriorated by increasing the normalized I DS , which can be attributed to the gradual increase in the acceptorlike traps at the interface under a continuous bias. [46,47] Since the UV-treated PNDPE-based transistors slightly increase the normalized I DS , it is assumed that the UV-treated PNDPE gate dielectrics initially generate acceptor-like traps under the bias. Then the effect of donor-like traps appears to be predominant under the long bias.
In this way, the characteristics of the transistor can be controlled by charge-carrier modulation, which includes the effect of trapping. Thus, the trap DOS is analyzed on the basis of temperature-dependent characteristics of the transistors measured by the four-probe method. Figure 3e shows the optical image of a transistor for four-probe measurements, and Figure S9, Supporting Information, shows the resulting temperaturedependent transfer curves. The Arrhenius plots are obtained from the transfer curves, as shown in Figure S10, Supporting Information. Figure 3f shows the trap DOS versus energy above the valence band (VB) calculated from the temperaturedependent transfer curves. The trap DOS in the deep region (>0.15 eV) increases with UV treatment. The increase in the trap DOS with UV treatment, accompanied by a positive V th shift, indicates the generation of acceptor-like traps. [47][48][49][50] The calculated V th shift (ΔV th ) from the trap DOS is +1.7 V, which is consistent with the measured V th shift, as shown in Figure 3a (more details mentioned in Discussion S1, Supporting Information), indicating that the charge-carrier modulation in this study originates from the controlling acceptor-like traps at the interface under UV treatment. In other words, the UV illumination of PNDPE gate dielectrics produces the acceptorlike traps for the generation of additional hole carriers in the organic semiconductors, as shown in Figure 3g. A high on-off ratio is obtained since the charge carriers are modulated only in the vicinity of the interface, which is completely different from the bulk doping of the organic semiconductors.
The ultrathin PNDPE gate dielectrics obtained in this study originate from the dense and uniform film formation. The atomic force microscopy (AFM) images of the PNDPE gate dielectrics are shown in Figure 3h and Figure S11a, Supporting Information. There are no major defects or pinholes in spite of the solution process, which is attributed to its preferable polydispersity index of ≈1. [41] PNDPE is synthesized with a single degree of polymerization owing to the ring-opening metathesis polymerization, and its films do not require other kinds of polymers such as photoinitiators to produce the HFDP. Therefore, ultrathin gate dielectrics of 14 nm are achieved without any major defects or pinholes with the support of a 6 nm thick AlO x layer. The root mean square (RMS) thickness of 1.96 nm in the pristine and 2.20 nm in the UV-treated (0.6 J cm −2 ) PNDPE films are attributed to the underlying AlO x layer, whereby its RMS is 4.2 nm, as shown in Figure S12, Supporting Information. The leveling of the PNDPE film by the spin-coat decreases the surface roughness to ≈2 nm. The RMS of the intrinsic PNDPE gate dielectric is less than 1 nm. [37] The slight increase in the RMS upon UV treatment can be attributed to the residual oxygen in the N 2 gas condition, which results in degradation of the charge-carrier mobility, as shown in Figure  S13, Supporting Information. The crystal size of DNTT is also analyzed by the AFM measurements, as shown in Figure 3i and Figure S11b, Supporting Information. The crystal size does not significantly change under the UV treatment. This is attributed to the nearly constant total surface energy and RMS of PNDPE gate dielectrics due to UV illumination. Figure S14, Supporting Information, shows the contact angle measurement of the pristine and UV-treated PNDPE gate dielectrics. The surface energy was calculated from the contact angle using the method of Owens and Wendt, and the calculated results are shown in Table S1, Supporting Information. The total surface energy did not depend on the UV-dose, and the polar component increased by UV illumination, the tendency of which is consistent with our previous study. [37] Since the total surface energy is a dominant factor for crystal growth, [51] the surface properties of PNDPE with and without UV illumination do not change the crystal growth of DNTT. In addition, the surface roughness changes the crystal growth of the organic semiconductors, [52,53] wherein a study showed that the grain size of DNTT changed along with the RMS from 0.9 nm to 1.8 and 2.7 nm; [53] however, the RMS measured in this study is only from 1.96 to 2.20 nm. Therefore, we infer that the UV illumination does not significantly change the crystal growth of DNTT, and that the increase in the trap DOS is irrelevant to the morphological properties of the DNTT crystals.
Since the PNDPE gate dielectrics and the parylene substrate are ultraflexible, the transistors exhibit high mechanical flexibility. The transfer curves of the PNDPE-based transistors are measured when the devices are bent with different bending radii. The transistors are encapsulated by 1 µm thick parylene to be placed in the neutral strain position, as shown in Figure 4a, to suppress the strain-induced changes in the transistor characteristics. [54] The bending test is performed by placing the transistors on the cylinders to measure the transfer curves during the bending process. Figure 4b,c present the photograph of a device including twenty transistors on a flat surface and on a bent surface along a cylinder of radius 0.8 mm. The transistors bent by the underlying cylinder are shown in the inset of Figure 4c and the optical image in Figure 4d. Figure 4e depicts the transfer curves of the pristine and UV-treated transistors when the bending radius is infinity (on a flat surface) and 0.8 mm, respectively. 5 of the 20 transistors are measured during the bending test, in which it is observed that the transfer curves do not vary significantly between the two radii. To further analyze the mechanical flexibility, |I GS | and |I DS | are measured by varying the bending radius up to 0.3 mm, which is summarized in Figure 4f. The values of |I GS | and |I DS | are almost identical for all the bending radii, where |I GS | is maintained lower than 6 and 40 pA in the pristine and UV-treated transistors at a bending radius of 0.3 mm. The change in value of |I DS | at the bending radius from infinity to 0.3 mm is only ≈10%. Therefore, high mechanical ultraflexibility is achieved by both the pristine and UV-treated transistors. This is partially attributed to the amorphous film formation of the AlO x layer as well as the ultrathin AlO x and PNDPE gate dielectrics. In our previous paper, in which the AlO x layer was fabricated by the same anodic oxidation method as that in this study, we reported that the dielectric property of the AlO x layer was maintained even at a bending radius of up to 5 µm. [55] To demonstrate the potential of the HFDP, the PNDPE-based transistors are implemented in ultraflexible ICs. The zero-V GS load inverters and a ring oscillator including 48 transistors are fabricated on the same substrate in an area of 3 × 4 cm 2 , where the V th of the respective transistors are spatially controlled by the HFDP, as shown in Figure 5a,b. The zero-V GS load inverters are promising candidates for flexible organic ICs because they exhibit multi-functionalities such as high amplification gain in analog circuits and reliable operation in logic circuits by only tuning the V th of the transistors, and hence have been widely used as the basic building blocks in the ICs. [19,56] It is desirable to implement both the depletion and enhancement transistors in the zero-V GS load inverters for reliable and high-speed operation. In this study, the load transistor is treated with UV radiation to form a depletion transistor, and the drive transistor is pristine to form an enhancement transistor using a shadow mask, as shown in the inset of Figure 5a. Although a larger width:length (WL) ratio of transistors (L = 14 µm; W = 24 mm) was applied in the circuit application for larger transconductance, nearly the same turn-on voltage was obtained for different WL ratio of transistors. Figure S15, Supporting Information, shows the comparison of transfer characteristics at different WL ratios, for example, L = 50 µm; W = 500 µm and L = 14 µm; W = 24 mm. We assumed that the constancy in the turn-on voltage even for large-sized transistor is attributed to the uniform PNDPE gate dielectric, at least within the millimeter scale.
The high operational reliability of the zero-V GS load inverters is first demonstrated with the HFDP. Figure 5c   results, as shown in Figure S16, Supporting Information. The trip point can be understood by the resistive division between the drive and load transistors. The impedance in the load transistors decreases with the UV treatment because the UVtreated transistors show depletion characteristics and exhibit higher current when compared to the enhancement transistors at V GS = 0. Therefore, the UV treatment of the load transistors shifts the trip point to a lower value. The operational reliability of the respective inverters is estimated using the noise margin, which is defined as "the maximum allowable spurious signal to give correct operation in digital circuits." [57] The noise margin is calculated by using the maximum equal criteria method, as shown in Figure S17, Supporting Information. [57,58] Figure 5d shows the noise margin versus the dose of the UV treatment, and the inset shows the schematic circuit diagram of the zero-V GS load inverter. The pristine inverters exhibit a low noise margin of 40%, and the UV treatment improves their noise margin by up to 80%. This value is comparable to that of the previously reported organic complementary inverters. [11] Furthermore, the amplification gain and operation speed are programmably tuned in this study. Figure 5e shows the typical static gain of the respective inverters at different doses.  The maximum static gain of 1200 is observed for the pristine inverters, although they exhibit ultraslow operation. The UVtreated inverters also exhibit a high static gain of up to 600. This can be attributed to the small sub-threshold slope of ≈150 mV and the high transconductance originating from the ultrathin PNDPE gate dielectrics. Here, it is worth noting that the transconductance is further enhanced by implementing the large WL ratio of transistors (L = 14 µm; W = 24 mm). The frequency characteristics are also analyzed by using the AC measurements, as shown in Figure 5f. Here, an input sine wave is inverted to generate the amplified output signal, as shown in Figure S18, Supporting Information. The UV treatment improved the operation speed, which was a trade-off relation to the gain. This is theoretically consistent in the common source circuit operation, in which the operation speed and gain are the functions of the impedance and transconductance of the load transistor, respectively. The gain-bandwidth products (GBWP) in the respective inverters are calculated to evaluate the tradeoffs between the gain and the operation speed. Consequently, the GBWP of up to 2.5 kHz is obtained by the UV treatment of 0.6 J cm −2 . The GBWP of the other UV-doses (0.07 and 0.20 J cm −2 ) inverters are 500 and 900 Hz, respectively. The slight mobility degradation owing to the UV treatment is not a significant drawback because the performance of ICs can be compensated by V th (or I DS at a certain V GS ). In practical applications, high-gain or high-speed circuit cells are spatially and arbitrarily implemented in the ICs by utilizing the HFDP.
The operation speed is further analyzed by measuring the signal delay, which is essential in digital circuits. Figure 5g shows the input and output waveforms obtained from the respective inverters. The input signal is a full-swing pulse wave. In the UV-treated inverters, the inverted output signals are also observed as full-swing pulse waves. The expanded output signals in Figure 5h show that the signal propagation delays, that is, the time from the high output state to low output state, are 6.5 ms, 1.4 ms, and 400 µs at 0.07, 0.20, and 0.60 J cm −2 , respectively. The inverters with more UV-dose exhibit smaller signal delay, which is consistent with the common source circuit operation. The UV illumination decreases the resistance of load transistors, that is, I DS at V GS = 0 increases with UV illumination because of the V th shift. The overshoot from 4 up to 4.5 V, can be attributed to the discharge of the parasitic capacitance formed between the source and the gate electrodes. The pristine inverters exhibit an almost constant output voltage owing to their ultraslow operation. The output voltage is expected to drop to 0 V after a prolonged measurement.
Finally, this study demonstrates the high-speed operation of the zero-V GS load inverters by implementing them in ring oscillator circuits. Figure 5i shows an optical image of a 3-stage ring oscillator circuit. Figure 5j and Figure S19a,b, Supporting Information, show the output waveforms at different doses. The waveforms were extracted via an external inorganic buffer to obtain high input impedance and minimize the parasitic capacitance of the buffer, as shown in the inset in Figure 5k. The oscillation frequencies are 70, 530, and 2.5 kHz, respectively, at UV-doses of 0.07, 0.20, and 0.60 J cm −2 , respectively, which is depicted in Figure 5k. This result is supported by the signal delay measurement shown in Figure 5g. Since the ring oscillator circuit consists of three zero-V GS load inverters, in which the delay time is smaller for more UV-dose, the oscillation frequency is higher for the ring oscillators with more UVdoses. Since a ring oscillator circuit consisting of the zero-V GS load inverters does not significantly increase the oscillation frequency corresponding to the supply voltage (V dd ) as long as the drive transistor works in the saturation regime, the fabricated ring oscillator is operated at V dd = 2 V, without changing its oscillation frequency for all UV-doses. The waveform of the ring oscillator (UV-dose: 0.20 J cm −2 ) is shown in Figure S19c, Supporting Information, as an example. The performances of the zero-V GS load inverters and ring oscillators are summarized and compared with those of the previous studies in Table S2, Supporting Information, in which the highest performances obtained in this study are compared with those of the previously reported zero-V GS -based organic circuits.

Conclusion
This study demonstrated the formation of the HFDP with the use of PNDPE as an ultrathin polymer gate dielectric to modulate the behavior of the charge carriers. The HFDP are obtained with a high-resolution of less than 18 µm. With the charge-carrier modulation via the photo-Fries rearrangement in the PNDPE gate dielectrics, the V th of the PNDPE-based transistors were programmably controlled over a wide range from −1.5 to +0.2 V at an operational voltage of 2 V, indicating that both the enhancement and depletion transistors are arbitrarily fabricated. The modulated V th remained unchanged over a period of 140 days during the LED exposure test and under a bias duration of 1800 s. The charge-carrier modulation was achieved by controlling the acceptor-like traps. The PNDPE forms dense and uniform gate dielectrics due to the catalytic ring-opening metathesis polymerization, resulting in ultrathin PNDPE films of a thickness of 14 nm. The transistor also exhibited high mechanical flexibility, in which the characteristics did not significantly vary even at a bending radius of 0.3 mm. The performance metrics of the ICs, for example, the zero-V GS load inverters and the ring oscillator circuits, were maximized with the HFDP. Consequently, the noise margin, gain, and GBWP of the zero-V GS load inverters were improved by up to 80%, 1200, and 2.5 kHz, respectively. Additionally, the oscillation frequency of a ring oscillator circuit was a maximum of 2.5 kHz at a supply voltage of 2-4 V. All of these performance metrics are the highest among the previously reported zero-V GS load-based organic circuits. The HFDP introduced in this study facilitate the application of more complex, ultraflexible, and wearable ICs for a wide range of applications, including the monitoring of human and structural healthcare.

Experimental Section
Materials: Unless otherwise noted, all the commercial reagents and solvents were used as received. Parylene (diX-SR) was provided by Daisan Kasei (Tokyo, Japan). DNTT was purchased from Nippon Chemical Industrial Co., Ltd (Tokyo, Japan). PNDPE was synthesized according to the details provided in a previous report [42] and dissolved in anisole by sonication for several hours at a concentration of 10 mg mL −1 . The PNDPE solution was stored in the dark for a few days and then filtered through the radius pores of 45 µm.
Device Fabrication: A 100 nm-thick Al gate electrode was thermally evaporated through a shadow mask onto a 1 µm thick parylene substrate supported on a fluorinated glass film that was fabricated by the spincoating of Cytop. The Al gate electrode was then anodized to form 6 nm thick AlO x using citric acid (500 mL, 1 mmol) as the weak acid solution and Pt electrode as the cathode. The AlO x layer was then treated with oxygen plasma at 100 W for 30 s to clean the AlO x layer. The PNDPE was then spin-coated at 500 rpm for 5 s and 3000 rpm for the subsequent 20 s to form the gate dielectrics. The PNDPE films were baked at 60 °C for 1.5 h to reduce the residual solvent. A handy-type Hg lamp (λ = 254 nm, P = 0.2 mW cm −2 at the sample surface) was used to treat the PNDPE films. Finally, the DNTT and Au source and drain electrodes were evaporated at an evaporation rate of 0.03 and 0.3 nm s −1 , respectively. The transistors were peeled off for the mechanical flexibility measurement. The transistors were passivated by 1 µm thick parylene films through the chemical vapor deposition in bias-stress, shelf-life, and flexibility measurements. The channel length (L) and width (W) of the transistors were 50 and 500 µm, respectively. The L and W of the transistors for the four-probe method were 1.5 mm and 500 µm, respectively, and the distance between the additional two probes was 450 µm. Zero-V GS load inverters were used with the ratio of a driver and a load transistor of 1:3, where L and W are 14 µm and 8 (24) mm, respectively. The short channel effects were not observed in this study.
Measurements and Analysis: The capacitance and the thickness of the PNDPE gate dielectrics were evaluated by the capacitance measurements with an LCR meter (E4980A, Keysight Technologies, Inc., Santa Rosa, California, USA). First, the thickness of an AlO x layer was estimated by means of capacitance measurements, where the relative permittivity of AlO x was defined as 9. Then the total capacitance of the PNDPE and AlO x layer was measured and the thickness of the PNDPE layer was extracted as a function of the relative permittivity of PNDPE, which was defined as 2.3 in the pristine. Since the relative permittivity is gradually shifted to 3.0 by the UV illumination, the thickness was estimated from the pristine PNDPE gate dielectrics. [38] Given that the thickness of 14 nm is an estimation based on the capacitance measurement, further quantification, for example, transmission electron microscopy, is desirable to clearly evaluate the thickness of the PNDPE gate dielectrics. The transistor characteristics were measured using a semiconductor parameter analyzer (B1500A, Keysight Technologies, Inc., Santa Rosa, CA, USA). The reliability factors were calculated in reference to the previous report. [59] The slope of the fitted lines, that is, the transconductance, for calculating the reliability factors, was determined from an average of respective 7 points before and after the point that exhibits maximum mobility. The FT-IR images were obtained by using a commercial infrared microscope (Hyperion 3000, Bruker Corp., Billerica, MA, USA) under purged N 2 conditions. The resolution of the focal-plane array was 2 or 16 µm, and the spectral resolution was 4 cm −1 . A 25 nm PNDPE film was used as a sample formed on a BaF 2 substrate coated with a 15 nm thick parylene film. The effect of absorption of the substrate was negated by measuring the FT-IR spectra of the BaF 2 and the coated parylene substrate. The illumination tests of the OTFTs with a white LED were carried out under vacuum conditions for ≈7-8 h. The spectra of the LED used can be found in Figure S7, Supporting Information. The temperature measurements were performed using a low-temperature unit (PEO-101-16, Pascal Co., Ltd., Osaka, Japan). The trap DOS was calculated using the fitting equation that was installed with the statistical analysis software (OriginPro, OriginLab Corp., Northampton, MA, USA). The method proposed by Fortunato et al. was used to calculate the trap DOS because it concurs well with the computer simulation model, and more precise consideration was achieved when compared to other calculation methods. [60,61] The contact angle measurement was performed by a FACE Measurement and Analytical System (FAMAS, Kyowa Interface Science Co., Ltd, Saitama, Japan). The PNDPE gate dielectrics were formed on the anodized AlO x layer. The dropped volumes of the water and ethylene glycol were 4 µL.

Supporting Information
Supporting Information is available from the Wiley Online Library or from the author.