Electrically Reconfigurable Organic Logic Gates: A Promising Perspective on a Dual‐Gate Antiambipolar Transistor

Electrically reconfigurable organic logic circuits are promising candidates for realizing new computation architectures, such as artificial intelligence and neuromorphic devices. In this study, multiple logic gate operations are attained based on a dual‐gate organic antiambipolar transistor (DG‐OAAT). The transistor exhibits a Λ‐shaped transfer curve, namely, a negative differential transconductance at room temperature. It is important to note that the peak voltage of the drain current is precisely tuned by three input signals: bottom‐gate, top‐gate, and drain voltages. This distinctive feature enables multiple logic gate operations with “only a single DG‐OAAT,” which are not obtainable in conventional transistors. Five logic gate operations, which correspond to AND, OR, NAND, NOR, and XOR, are demonstrated by adjusting the bottom‐gate and top‐gate voltages. Moreover, varying the drain voltage makes it possible to reversibly switch two logic gates, e.g., NAND/NOR and OR/XOR. In addition, the DG‐OAATs show a high degree of stability and reliability. The logic gate operations are observed even months later. The hysteresis in the transfer curves is also negligible. Thus, the device concept is promising for realizing multifunctional logic circuits with a simple transistor configuration. Hence, these findings are expected to surpass the current limitations in complementary metal−oxide−semiconductor devices.


Introduction
State-of-the-art computing systems, including artificial intelligence systems and neuromorphic computers, are highly required for the forthcoming Internet of Things society due to by adjusting the drain voltages. Additionally, Martins et al. implemented OR and AND logic gates by selecting the proper input voltages in the same transistor configuration. [29] However, the drain current of these transistors increases in a monotonic manner. As a result, the reconfigurable logic gate operations have been limited to OR/AND, AND/NAND, or NOR/NAND combinations. [28][29][30][31] In this study, we propose a new reconfigurable logic circuit based on a single dual-gate organic antiambipolar transistor (DG-OAAT). An antiambipolar transistor (AAT) is a type of heterojunction transistor and is an essential component in the proposed circuit. [32][33][34][35][36][37][38] The transistor has a partially overlapped region of p-type and n-type semiconductors (pn junction) in the transistor channel. Therefore, it can induce a negative differential transconductance (NDT) even at room temperature. Namely, a sharp increase and then decrease in the drain current (that is, Λ-shaped drain current) can be visible despite the increase in the gate voltage. Due to this attractive feature, multivalued logic circuits (MVLs), such as ternary and quaternary inverters, have recently been realized, and their development is another significant strategy for improving the data processing capability of the currently used logic circuits. [39][40][41][42][43][44][45] In contrast to the abovementioned efforts on MVLs, our approach is to apply AATs to electrically reconfigurable logic circuits. A dual-gate configuration enables the control of the used Λ-shaped drain current by three input signals: bottom-gate, top-gate, and drain voltages. Using this distinctive feature, multiple logic gate operations could be achieved using only a single transistor. First, we exhibited five logic gate operations-AND, OR, NAND, NOR, and XOR-by adjusting the bottom-gate and top-gate voltages. Moreover, the drain voltage induced electrical switching between two logic gates, e.g., NAND/NOR and OR/ XOR.
Such logic gate operations are not obtainable in conventional transistors due to the monotonic increase in drain currents, which is a unique feature of our proposed DG-OAAT circuit. Therefore, we believe that our concept provides a promising perspective for attaining large-scale integrated organic electronic circuits. Figure 1a,b shows the device structure and an optical microscopy image of the DG-OAAT. A highly doped p-type Si (100) substrate (<0.01 Ω cm) was used as the common bottom-gate (BG) electrode. A patterned Au film was used as the top-gate (TG) electrode. In addition, hafnium oxide and fluoropolymer (CYTOP) were used as the standard BG-and TG-insulators, respectively. The Experimental Section describes the formation process in detail. For the transistor channels, α-sexithiophene (α-6T) and N,N′-dioctyl-3,4,9,10-perylenedicarboximide (PTCDI-C8) were employed as p-type and n-type semiconductors, respectively. The film thicknesses were optimized to be 15 and 8 nm for the α-6T and PTCDI-C8 films, respectively, so as to enhance the tunability of TG and BG electrodes for both channel layers. Atomic force microscopy measurements were performed; the results confirmed that both channels and the partially overlapped (PN stacked) region have smooth surface morphologies, as shown in Figure S1 in the Supporting Information. The channel width of the DG-OAAT was 360 ± 20 µm. The typical channel length of the DG-OAAT was 150 µm (100 and 120 µm for the α-6T and PTCDI-C8 channels, respectively, including the overlapped area).

Single-Gate Operations with a Dual-Gate Organic Antiambipolar Transistor
First, we evaluated the basic single-gate operations of the DG-OAAT under BG or TG voltages. All the measurements were performed at room temperature under atmospheric conditions. Figure 1c shows a typical drain current (I D )-BG voltage (V G:bottom ) curve and the differential transconductance curve of the transistor in the case of p-type operation. The drain voltage (V D ) was fixed at −10 V, and the TG electrode was electrically floated. The BG transistor exhibited a Λ-shaped I D . Namely, I D rapidly increased at V G:bottom (= V on ) = −3.2 V and then decreased with increasing V G:bottom . Consequently, I D was completely suppressed at V G:bottom (= V off ) = −5.7 V. The peak drain current (I peak:bottom ) reached −21.5 nA at a peak voltage (V peak:bottom ) of −4.6 V. The peak width (ΔV), which is defined as ΔV = V on −V off , was estimated to be 2.5 V. The corresponding NDT was visible, and the maximum value of NDT, g max , was obtained as −41.3 nS at V G:bottom = −4.7 V. In addition, the hysteresis in both curves was negligible in 77% devices ( Figure S2, Supporting Information), which reveals that carrier trapping sites located at the interfaces of the BG insulating layer and the organic channels were marginal owing to CYTOP coating.
Surprisingly, similar I D and NDT behaviors appeared even in the case of TG operation, although a broadening in the peak width (ΔV = 8.9 V) of I D was observed ( Figure 1d). Moreover, in this case, the hysteresis was marginal in both curves, even though the observation yield of the hysteresis-free transfer curves (17%) was lower than that in BG operation (77%) ( Figure S3, Supporting Information). In addition, the same peak current (I peak:top ) (−21.9 nA) was obtained at V peak:top = −4.3 V, and g max was calculated to be −12.5 nS at V G:top = −4.9 V. These parameters are comparable with those obtained in the case of BG operation, which is assumed to be because of the smooth surface morphologies of the α-6T and PTCDI-C8 channels ( Figure S1, Supporting Information).
Notably, the transfer curves obtained during the BG and TG operations were stable; no change in I peak values was observed even after 3 months. These results show the high stability of the DG-OAATs ( Figure S4, Supporting Information).
Based on our previous studies and the other recent works, [35][36][37][45][46][47] the Λ-shaped I D is interpreted by a similar analogy to that of the shoot-through current in a CMOS inverter. The equivalent circuits are depicted in Figure 1e. The DG-AAT can be regarded as a series circuit of p-type and n-type transistors, where the BG or TG works as a common gate electrode. Namely, the Λ-shaped I D can be explained as the overlapped current of the two transfer curves of the α-6T and PTCDI-C8 transistors using the following equations [47] 2 [ ] www.advmat.de www.advancedsciencenews.com where L p and L n are the channel lengths of the α-6T and PTCDI-C8 films, respectively, W is the common channel width, and C i is the capacitance of the insulator per unit area (125 and 64 nFcm −2 for the BG-and TG-insulators, respectively). μ p and V th,p are the hole carrier mobility and the threshold voltage of the α-6T transistor, respectively. μ n and V th,n represent the electron carrier mobility and the threshold voltage of the PTCDI-C8 transistor, respectively. Importantly, V on in the AATs corresponds to the threshold voltage (V th,p ) of the α-6T transistor. Meanwhile, V off is related to V th of the PTCDI-C8 transistor (V D + V th,n ).
We estimated the carrier mobilities (μ p and μ n ) and threshold voltages (V th,p and V th,n ) of the OAATs (13 devices formed on the same substrate) and compared them to those obtained from α-6T and PTCDI-C8 transistors. The representative I D -V G curves of α-6T and PTCDI-C8 transistors ( Figure S5, Supporting Information). The extracted parameters are summarized in Table 1. The carrier mobilities (μ p and μ n ) and the threshold voltages (V th,p and V th,n ) of OAATs in BG operations closely coincide with those of the α-6T and PTCDI-C8 transistors. The result provides clear evidence that the Λ-shaped I D in OAATs is explained as the overlapped current of the two transfer curves of the α-6T and PTCDI-C8 transistors with enhancement modes. However, the transistor parameters estimated for TG operation were not quantitatively consistent with those found in the constituent transistors. The hole and www.advmat.de www.advancedsciencenews.com electron mobilities (μ p and μ n ) of OAATs were lower than those of α-6T and PTCDI-C8 transistors. In contrast, the threshold voltages (V th,p and V th,n ) of OAATs were reduced compared with those of both transistors. These discrepancies between TG and BG operations are caused by the complicated channel structure of OAATs. The staggered PN region would hinder carrier transport in TG operations for both carriers. In addition, the structure could induce inhomogeneous gate electric fields, resulting in variations of threshold voltages.
Based on the above discussion, we briefly discuss the conductive mechanism of the transistor. When V G is below V on (Figure 1e-i), the PTCDI-C8 channel is on state, while the α-6T channel is off state. As a result, the total I D does not flow in the transistor. In the middle V G range (V on < V G < V off ) (Figure 1e-ii), the total I D flows because both transistors are active. For the further increment of V G (V off < V G ) (Figure 1e-iii), I D is suppressed again because the PTCDI-C8 channel becomes off state, even though the α-6T transistor is active. As a result, the appropriate energy-level offset of p-and n-type materials is required to induce the Λ-shaped transfer curve. In this regard, the material combination of α-6T and PTCDI-C8 films is promising.

Dual-Gate Operations with a Dual-Gate Organic Antiambipolar Transistor
We then exhibited the dual-gate (DG) controllability of the drain currents in DG-OAATs.
www.advmat.de www.advancedsciencenews.com V G:top was applied ranging from 1 to −11 V. Meanwhile, V off was linearly varied from −6.6 to −5.1 V in the same voltage range. These variations of V on and V off well agree with those of the V th of the respective channels (V th:bottom_α-6T and V th:bottom_PTCDI-C8 ) ( Figure S6, Supporting Information). These results indicate that the shift in V peak:bottom was caused by the changes in V on and V off in the case of V G:top .
The 3D and 2D I D mappings were demonstrated as functions of V G:bottom and V G:top , respectively, as shown in Figure 2c,d, to evaluate the detailed variations in V peak:bottom and I peak:bottom . The Λ-shaped I D was found to be obviously shifted by V G:top (Figure 2c). In addition, V peak:bottom linearly changed from −5.7 to −4.2 V in the V G:top range of 1 to −11 V (Figure 2d). The maximum I peak:bottom was found to be −33.8 nA at V G:bottom = −4.9 V and V G:top = −4.8 V. In addition, the change in I peak:bottom was less than 30% under 10-cycles V G:top sweep from 0 to −10 V ( Figure S7, Supporting Information).
These results clarify that the transistor parameters in the case of BG operation, V peak:bottom , V on , V off , and I peak:bottom can be tuned by V G:top .

Multiple Two-Input Logic Gate Operations based on a Dual-Gate Organic Antiambipolar Transistor
Based on the DG operation in the DG-OAAT, we demonstrated five two-input logic gate operations-AND, OR, NAND, NOR, and XOR-using only a single transistor. Here, V G:bottom and V G:top were used as two-input signals in the logic gates, which are denoted as V IN1 and V IN2 . The obtained I D was monitored as an output signal (I out ).   (1, 1). However, I out showed a low sate, "0," for the other combinations of input signals. In this manner, OR, NAND, NOR, and XOR were exhibited (Figure 3g-j). These results indicate that five logic gate operations, namely AND, OR, NAND, NOR, and XOR, can be achieved in only one transistor by adjusting V IN1 and V IN2 , which is in contrast to the current CMOS-based logic gates (e.g., 4 and 12 transistors are necessary for the NAND and XOR gates, respectively). Our finding is thus expected to attain multifunctional logic circuits by the integration of multiple logic gate functions into a single transistor.
Adv. Mater. 2022, 34,   www.advmat.de www.advancedsciencenews.com Similar logic gate operations have been achieved using single-electron transistors (SET) with multigate configurations. [48][49][50] In these cases, the Λ-shaped I D was obtained by the Coulomb oscillation in accordance with the gate voltage. Maeda et al. exhibited six logic gate operations using a DG-SET. [48] In addition to the abovementioned five logic gates, the XNOR gate operation was realized by making active use of periodic peak I D . Takahashi et al. reported an XOR gate by a multigate SET in the same manner. [49] However, these device operations have been limited in cryogenic temperatures (≈40 K) because of the nature of Coulomb blockade behaviors. In contrast, our transistor enables multiple logic gate operations at room temperature, which is a large benefit with regard to using AATs for reconfigurable logic gates.

V D -Induced Switching of Two Logic Gates
In organic AATs, the Λ-shaped I D is interpreted by the same mechanism as that of the shoot-through current of CMOS inverters. This means that the peak width (ΔV) can be systematically tuned by V D , even though the V th values in the constitutive transistors are identical for the V D changes. We made use of this feature for the electrical switching of two logic gates, leading to the integration of additional reconfigurable logic functions. Figure 4a shows I D -V G:bottom curves with different V D , where V G:top was fixed at 0 V. V on was found to be −3.4 V, and this value is completely constant, irrespective of V D . This is because V on is equal to the V th of α-6T (V th:α-6T ) ( Figure S8a, Supporting Information). In contrast, V off clearly shifted from −6.5 to −8.2 V in the V D range from −10 to −12 V, even though the V th of PTCDI-C8 (V th:PTCDI-C8 ) is constant and independent on V D ( Figure S8b, Supporting Information). The reason is that V off agrees with the difference of V D and V th of PTCDI-C8, i.e., V D +V th:PTCDI-C8 . Accordingly, V off and ΔV can be controlled by V D , even though no changes were observed in V th in both the channel layers.
By taking advantage of the V D tunability of ΔV, we demonstrated the electrical switching of two logic gates by only changing V D . Figure  . Notably, all of these logic gate operations can be achieved even after 5 months, which shows the extremely high stability and reliability of our devices ( Figure S9, Supporting Information).

Conclusion
We have achieved reconfigurable logic gate operations using a single DG-OAAT by controlling the following three input parameters: V IN1 , V IN2 , and V D . By selecting suitable V IN1 and V IN2 , it was possible to demonstrate five logic gate operations: AND, OR, NAND, NOR, and XOR. Moreover, the slight variation (8%) in V D made it possible to electrically switch two logic gates, such as NAND/NOR and OR/XOR. Such logic gate operations are not possible with conventional transistors with a monotonic increase in the drain currents, which is a unique feature of our logic circuits based on DG-OAATs. Additionally, all of these logic gate operations were achieved even after 5   months, showing the high stability of our devices. Therefore, we consider that the multifunctional logic circuits based on DG-AATs contribute to the drastic reduction of the number of transistors in current integrated circuits and that they can improve the capability of data processing. Thus, our device concept provides a promising way for realizing multifunctional logic circuits with a simple circuit design.

Experimental Section
Formation of DG-AATs: DG-AATs with α-6T and PTCDI-C8 layers were produced using vacuum-deposition techniques. A highly doped p-type Si (100) substrate (<0.01 Ω cm), which was employed as a common BG electrode in all the transistors, was chemically cleaned using Shiraki's method, followed by the removal of a native oxide in a 5% HF solution. Subsequently, using an atomic layer deposition (ALD) system, a 30 nm-thick HfO 2 film was deposited on the Si substrate as a BG insulating layer at a temperature of 175 °C, where tetrakis(dimethylamino)hafnium (TDMAHf) and water were used as hafnium and oxygen sources. Then, a 15 nm-thick fluorocarbon polymer (CYTOP) (AGC chemicals, CTL-809M and SOLV-180) was spin-coated to passivate the carrier trap sites on the HfO 2 surface and facilitate the charge transport of the organic channels. Afterward, α-6T (15 nm) and PTCDI-C8 (8 nm) films were grown as p-and n-type organic channels using a thermal vacuum deposition technique at a background pressure of 10 −7 Pa. It is worth noting that the two organic layers were partially overlapped in the transistor channel to form a heterointerface, which is the origin of Λ shapes in AATs. For the source and drain electrodes, 30 nm-thick Au films were then deposited using a thermal vacuum deposition system.
For the TG configuration, a CYTOP (20-30 nm) film was spincoated on the top of the organic channels, followed by the deposition of an HfO 2 (40 nm) layer as a TG insulator using the ALD method. It should be noted that the deposition temperature of the HfO 2 layer was reduced to 120 °C to hinder the aggregation of the organic layers during the ALD process. Consequently, an Au TG electrode was patterned for each transistor via thermal vacuum deposition to complete DG-AAT.
The typical width and length of DG-AAT were 360 ± 20 and 150 µm, respectively.
Transistor Measurements: The transistor measurements of DG-AATs and the logic gate operations were performed using source measurement units (Keysight Technologies, B2912A and B2912B). For the capacitance-voltage measurements, a semiconductor device analyzer (Agilent, B1500A) was used to evaluate the capacitances of the TG and BG insulators. All the measurements were performed using a 4-probe system at room temperature under atmospheric conditions.

Supporting Information
Supporting Information is available from the Wiley Online Library or from the author.