Revival of Ferroelectric Memories Based on Emerging Fluorite‐Structured Ferroelectrics

Over the last few decades, the research on ferroelectric memories has been limited due to their dimensional scalability and incompatibility with complementary metal‐oxide‐semiconductor (CMOS) technology. The discovery of ferroelectricity in fluorite‐structured oxides revived interest in the research on ferroelectric memories, by inducing nanoscale nonvolatility in state‐of‐the‐art gate insulators by minute doping and thermal treatment. The potential of this approach has been demonstrated by the fabrication of sub‐30 nm electronic devices. Nonetheless, to realize practical applications, various technical limitations, such as insufficient reliability including endurance, retention, and imprint, as well as large device‐to‐device‐variation, require urgent solutions. Furthermore, such limitations should be considered based on targeting devices as well as applications. Various types of ferroelectric memories including ferroelectric random‐access‐memory, ferroelectric field‐effect‐transistor, and ferroelectric tunnel junction should be considered for classical nonvolatile memories as well as emerging neuromorphic computing and processing‐in‐memory. Therefore, from the viewpoint of materials science, this review covers the recent research focusing on ferroelectric memories from the history of conventional approaches to future prospects.


Introduction
Ferroelectricity with two or more spontaneous polarization states has been suggested as an ideal approach for memory devices in digital computing.In particular, over the past few decades, ferroelectric memories have been seriously considered ZrO 2 , which is frequently considered the "twin oxide" of HfO 2 .Thus, nonvolatility can be induced in conventional MOSFETs and DRAMs by substituting the gate and cell capacitor dielectrics with fluorite-structured ferroelectrics.Numerous FeFETs with fluorite-structured ferroelectrics have been developed since the first report in 2011. [3]Furthermore, the 1T1C FeRAM arrays have been recently demonstrated by Sony. [4]In addition to these variations from conventional devices, a rapidly increasing number of FTJs with fluorite-structured ferroelectrics have been reported since their first demonstration in 2016. [5]n the semiconductor industry, materials innovation has always been essential for resolving seemingly unsolvable problems.However, promising results at the laboratory level do not guarantee industrial success.The fluorite-structured ferroelectrics also face various problems including 1) insufficient reliability including endurance, retention, and imprint; and 2) difficulties in fabricating homogeneous and uniform films with a strong preferred orientation as well as a suppressed nonferroelectric phase formation. [1,6]6b,7] The fluorite-structured ferroelectrics have been suggested for synaptic devices or artificial neurons in neuromorphic computing or processing-in-memory applications, which are considered as promising future computing paradigms. [8]By utilizing partially switched polarization states, multiple weights can be updated by optimized electric pulses. [9]Moreover, in nanoscale FeFETs, neuron-like integrate-and-fire behavior could be mimicked within a simple structure. [10]The recent progress in this field has gained increasing interest; however, material-related issues, including: 1) difficulties in achieving linear weight update with identical pulse train, 2) difficulties in achieving symmetric potentiation/depression, and 3) reliability of partially switched states, have also been observed within the newly developed devices.
Herein, recent research on fluorite-structured ferroelectrics as well as the history of ferroelectric memories based on conventional materials are reviewed from the viewpoint of material-device integration.In Section 2, the history of conventional ferroelectric memories is briefly discussed, with a focus on material-related issues.In Sections 3 and 4, recent studies on fluorite-structured ferroelectrics and devices based on these materials are reviewed.In Section 5, current material issues in ferroelectric memories are discussed, and perspectives on future research strategies for ferroelectric memories are provided.

History of Conventional Ferroelectric Memories
The electric polarization of ferroelectrics is spontaneous and can be reversed by an applied electric field.These defining properties make ferroelectrics ideally suited for memory technology.However, after ferroelectric memory was first proposed in the early 1950s, [11] research progress remained slow until the later 1980s, when major breakthroughs in materials and design principles allowed commercially viable ferroelectric memories to be demonstrated using CMOS processes. [12]Owing to these developments, ferroelectrics attracted renewed interest in the semiconductor device community.Consequently, ferroelectric memories have been successfully commercialized for a range of products, despite being limited to low-density applications.In this section, we provide a brief history of ferroelectric memory devices, with an emphasis on key challenges and breakthroughs.We focus on the two device architectures that were most actively studied prior to the discovery of fluorite ferroelectrics, namely, 1T1C FeRAMs and FeFETs.
1T1C FeRAMs are the most prevalent form of ferroelectric memory.The memory cell in a 1T1C FeRAM consists of one access transistor and one ferroelectric capacitor.Binary information ("1" and "0") is stored in the ferroelectric capacitor using its up/down polarization states, and the transistor allows random access for the read and write operations.Although FeRAMs are nonvolatile, the read operation in 1T1C FeRAMs is destructive.The stored value by reading process is obtained by detecting whether the polarization within the ferroelectric capacitor is reversed by the read pulse through the plate line.This process requires subsequent rewriting of the cell to recover its original information.The basic architecture and working principles of FeRAM are thus strongly reminiscent of the 1T1C-type DRAMs, which are the main memory used in modern computers.12d] An ideal memory should have a high density like DRAM, perform quickly enough to handle the speed of static RAM(SRAM), and retain information without a power supply (i.e., nonvolatility) like flash memory.The aim was-and still is-to build a universal memory that could cover the entire memory hierarchy. [13]In the later 1980s, owing to progress in the fabrication of ferroelectric lead zirconate titanate (PZT) [14] and its successful integration into the 1T1C architectures, [12a,b] ferroelectric memory became a leading candidate for achieving this ultimate goal. [15]12b,d] After the market debut of 1T1C FeRAMs, device design was significantly improved toward the realization of high-density applications. [15,16]For example, early FeRAM products employed two 1T1C memory cells to represent a single bit, leading to a 2 transistor-2 capacitor (2T2C) cell. [12]For stable memory operation, the 2T2C architecture utilizes a complementary 1T1C cell as a reference.However, because their size is approximately twice than that of the original 1T1C architecture, 2T2C cells are only suitable for low-density memories.In the 1990s, many efforts were devoted to realizing a robust FeRAMs with a single 1T1C cell per bit, [17] which were eventually adopted in advanced FeRAM products.Simultaneously, continuous innovations were made in the structure and integration technology of FeRAMs.The main challenge involved building a small cell structure while maintaining a reliable cell signal.The first proposal was a planar (or offset) cell structure. [18]Although easy to process at a low cost, this cell structure occupies a large cell area because the ferroelectric capacitor is formed in a separate place that is offset from the transistor.The introduction of a stacked cell structure using capacitor-over-bitline technology, [19] in which the capacitor is located above the transistor, resulted in a significant reduction in FeRAM cell size. [15]Further FeRAM miniaturization was achieved using chain-cell structure technology. [20]However, the scaling of FeRAMs has lagged far behind that of other primary memories, such as DRAMs.State-of-the-art DRAMs now utilize a sub-20 nm CMOS process, whereas FeRAMs have remained at the 130 nm process for more than 15 years. [21]Consequently, 1T1C FeRAMs are targeted at niche, low-density applications.This scaling gap has mainly been attributed to the limitations of current ferroelectric materials.
From a materials perspective, the most widely used ferroelectric material in 1T1C FeRAMs is PZT, which is an archetypal perovskite oxide.Although ferroelectric PZT was first developed in 1952, [22] its industrial use in FeRAM devices was not possible until the advent of sol-gel [14c] and sputter deposition [14a,b] methods, which were adopted in the early products of Krysalis [12a,e] and Ramtron [12b,d] in the late 1980s.18a] The dominant failure mechanism in early FeRAM products was poor cycling endurance due to the degradation of remanent polarization (P r ) under repeated ferroelectric switching, known as the polarization fatigue.Layered perovskites, such as strontium bismuth tantalite (SBT) [23] and bismuth lanthanum titanate (BLT), [24] were introduced as alternatives to PZT because of their nearly fatigue-free characteristics, even on top of conventional Pt electrodes.8a,25] The fatigue issue of PZT was eventually resolved by using conductive oxide electrodes, such as IrO 2 [26]   and RuO 2 , [27] in which the oxygen vacancies responsible for polarization fatigue can be effectively compensated.Despite considerable advances in the materials engineering of PZT and related perovskite materials, there are still unresolved limitations that may be intrinsic to perovskite ferroelectrics.First, similar to other conventional perovskite ferroelectrics, PZT suffers from scaling issues.Generally, PZT loses polarization in nanometer-scale thin films owing to the depolarization field (E dep ).Moreover, despite 3D integration being necessary for high-density memory technology with ever-shrinking dimensions, such as DRAMs, this process remains challenging at the industrial level for PZT films.Second, PZT exhibits poor compatibility with Si-based CMOS technology.For instance, difficulties in dealing with unconventional metals, such as Ir, result in complicated fabrication steps and consequently high costs.Therefore, research interest in perovskite-based FeRAMs has significantly decreased over the last two decades.
A more straightforward and scalable approach for utilizing ferroelectric properties in nonvolatile memories is the construction of FeFETs (or ferroelectric gate FETs). [28]A typical FeFET is composed of one transistor with a ferroelectric gate stack structure.As initially proposed in the mid-1950s, [29] this device uses ferroelectric polarization to modulate the conductivity of semiconductors in a FET.In FeFETs, the threshold voltage shifts depending on the polarization state of the ferroelectric film.Therefore, measuring the drain currents at an appropriate gate voltage can lead to two distinct values for each polarization state, which allows binary information written in the cell to be read and distinguished.Compared with 1T1C FeRAMs, the FeFET architecture has two major advantages.First, the reading process is nondestructive because it does not involve polarization switching.This offers unlimited read cycles without fatigue and with lower operating voltages.Second, because a memory cell can be represented by a single transistor, FeFETs are beneficial for high-density memory technology.Nonetheless, despite a long research history and apparent advantages over corresponding 1T1C architectures, the industrial applications of FeFETs have been even more challenging.
The first proof-of-concept demonstration of a memory device based on FeFET was reported by Moll and Tauri in 1963. [30]In early FeFET devices, a thin-film transistor was deposited on a ferroelectric substrate (triglycine sulfate or PZT).However, at that time, stored binary states were highly unstable and such a structure was inappropriate for application in scaled integrated circuits.In 1974, Wu proposed and demonstrated a new type of FeFET that mimicked a well-established MOSFET device. [31]he device was composed of a metal-ferroelectric-semiconductor (MFS) stack, in which a perovskite ferroelectric (bismuth titanate) was deposited on a Si substrate using a sputtering method.Building on this concept, Sugibuchi intentionally grew a SiO 2 layer on Si [32] to fabricate a metal-ferroelectricinsulator-semiconductor (MFIS) stack.The added insulating layer reduced unintentional charge injection from Si to the ferroelectric layer to some extent.However, in MFIS stacks, an enhanced E dep in the ferroelectric layer and the large electric field applied to the SiO 2 layer caused memory retention loss and dielectric breakdown, respectively.In subsequent MFIS stacks, HfO 2 -based high-k insulators [33] were used instead of SiO 2 to reduce the internal fields in both the ferroelectric and dielectric layers.However, MFS and MFIS stacks suffered from not only the poor interfacial qualities associated with ferroelectrics but also the diffusion of Pb and/or Ti atoms (in PZT) to the Si substrate.
IrO 2 electrodes, which resolved the fatigue problem of 1T1C FeRAMs, [26] were introduced into the FeFET architecture in 1995. [34]In the resulting metal-ferroelectric-metal-insulatorsemiconductor (MFMIS) stack, a floating metal electrode was inserted between the ferroelectric and insulator layers.It should be noted that MFS, MFIS, and MFMIS stacks are still the most common building blocks for FeFETs.The MFMIS stack resolved several issues associated with PZT quality and metal diffusion.This structure also enabled the area ratios between the MFM and MIS parts to be individually modified, [35] providing an efficient approach for optimizing the capacitances of the ferroelectric and insulator layers.However, for industrial applications in highly scaled memory devices, the insertion of additional layers composed of unconventional metals is not favorable.Thus, FeFETs could not compete with existing memory devices in terms of scalability and cost effectiveness, and large-scale commercialization has not yet been achieved, with the main obstacle again being the inherent limitations of conventional perovskite-based ferroelectric materials.
Moreover, as miniaturization of the devices is in demand, further reduction of gate length in planar type FeFETs is required, which results in problems such as short-channel effect and narrow channel effect.To solve these problems, emerging structures such as ferroelectric fin field-effect transistor (FinFET), recessed-channel FeFETs (R-FeFET), and gate-all-around (GAA) FeFETs have been proposed and demonstrated. [36]These structures have been previously adopted or being studied for the physical scaling-down of MOSFETs, and have been studied for FeFETs, wherein device structure is in principle equivalent to that of MOSFET.The development of these devices will be discussed in detail in Section 4.1.1.Figure 1 shows the schematic diagrams of emerging structures according to the sequence of their development.However, conventional perovskite-based ferroelectric materials could not be applied to the emerging structures, such as FinFET, R-FeFET, and GAA-FeFET, possibly due to the fact that their physical scaling down was stopped before reaching the technology node limiting the utilization of planar FeFETs.It should be noted that the FinFET technology was first adopted to CMOS at 14 nm process node.

History of Fluorite-Structured Ferroelectrics
Ferroelectricity in Si-doped HfO 2 was discovered in 2006 and reported in 2011 by Boescke et al. with the formation of a polar orthorhombic phase (o-phase, space group: Pca2 1 ). [3]Prior to this work, HfO 2 and ZrO 2 were known as general dielectric materials that exhibited no spontaneous polarization with monoclinic (m-phase, space group: P2 1 /c) or tetragonal (t-phase, space group: P4 2 /nmc) crystallographic phases.According to computer simulations, the o-phase can exhibit a spontaneous polarization of ≈50-55 µC cm −2 . [7]Subsequently, ferroelectricity was reported in HfO 2 doped with various dopants, including Zr, La, Y, Gd, and Sr as well as undoped HfO 2 , and selected results with high P r values are summarized in Table 1. [37]These results were unexpected because HfO 2 had been utilized as a gate oxide in state-of-the-art semiconductor chips since first adopted by Intel in the Penryn processor. [38]It suggests that FeFETs with a feature size equivalent to that of MOSFETs could be achieved, and in 2012, a FeFET with a 28 nm channel length was demonstrated by GlobalFoundries. [39]This finding was particularly notable because the physical scaling down of FeFETs with conventional materials had stopped at the 130 nm technology node. [7]By adding a small amount of dopants and using rapid thermal processing (RTP), a spontaneous polarization of higher than 10 µC cm −2 can be achieved, even in the sub-10 nm thickness regime, which induces nonvolatility in MOSFETs.In addition, ferroelectricity on fluorite-structured film was confirmed at sub-5 nm thicknesses, which is thin enough to utilize tunneling effect for memory device, and an FTJ with Si:HfO 2 was first demonstrated in 2016. [5]

Material Properties of Fluorite-Structured Ferroelectrics and Their Suitability for Ferroelectric Memories
Fluorite-structured ferroelectrics have attracted increasing interest in both academia and industry because their material properties differ from those of conventional ferroelectric materials.This section gives a brief overview of the properties of fluorite-structured ferroelectrics from the viewpoint of material-device integration, which was discussed more extensively in our previous review. [7]he crystal structures and properties of perovskite and fluorite-structured ferroelectrics are compared in  conventional ferroelectric materials, it is challenging to retain ferroelectricity within the sub-50 nm regime with industryfriendly processes. [43]Decreasing leakage current is an important requirement for the reliable operation of charge-based ferroelectric memories such as FeRAM and FeFET.It becomes even more important with the physical scaling down of the devices as the thickness of films decreases.Since the bandgap of fluorite-structured ferroelectrics (generally ≈5.0-5.5 eV) is larger than that of perovskite-structured ferroelectric (gener-ally 3-4 eV), fluorite-structured ferroelectrics would more effectively decrease the leakage current by thermionic emission or tunneling at the equivalent physical thickness. [44]Moreover, the coercive field (E c ) of ≈0.1 MV cm −1 in conventional ferroelectrics does not allow a sufficient memory window in FeFETs.6b,8a] However, for the fluorite-structured ferroelectrics, the physical scaling aspects are completely different.Even in the first report, Table 2. Comparison of crystal structures and properties of perovskite and fluorite-structured ferroelectrics. [44,56].2b, the P r value can reach as high as 1.9 µC cm −2 , which is one order of magnitude lower than that of 10 nm-thick films.There have also been several reports on ferroelectricity in the sub-5 nm thickness regime, as summarized in Figure 2c and Table 3.The P r values of fluorite-structured ferroelectrics vary with film thickness (Figure 2c).When the film thickness increases from 15 to 20 nm, the m-phase fraction generally increases with a decrease in the P r value.When the film thickness is below 5-7 nm, the P r value decreases with an increase in the relative fraction of the t-phase.Moreover, the E dep arising from imperfect compensation of the polarization charge reduces the P r value, leading to general scaling behavior, with the ferroelectricity weakening as the physical dimensions decrease.By contrast, Cheema et al. [45d] predicted that an inverse scaling effect (i.e., enhanced ferroelectricity in thinner films) occurs in ultra-scaled (1.5 nm) HZO films.45d] According to recent reports on FeFETs based on fluoritestructured ferroelectrics, a sizable memory window of ≈1.0 V can be achieved owing to a characteristically high E c (>1 MV cm −1 ).Additionally, the leakage current can be sufficiently suppressed because the bandgap is >5.0 eV. [44]With physical scaling down, the E c values of ferroelectric materials increase according to the well-known Kay-Dunn relation. [46]However, in the case of fluorite-structured ferroelectrics, the effect of the film thickness remains under debate.Some research groups have reported that the E c values follow the general Kay-Dunn relation, [47] whereas others have reported that the increase in E c values with decreasing thickness is mitigated relative to that in conventional ferroelectrics. [48]Figure 2d shows the changes in the E c values of ferroelectric fluorite-structured thin films with varying film thicknesses.
Established ALD processes provide atomic-scale thickness control and enable the production of 3D ferroelectric capacitors. [49]Furthermore, the feasibility of a vertical array of FTJs has been demonstrated, although the array size has yet to be increased for practical applications. [50]Moreover, Sony has demonstrated a 1T1C FeRAM using ALD. [51]In addition, HfO 2 ferroelectrics have been found to be well-matched with industryfriendly metallic or semiconducting materials such as TiN, TaN, W, and Si, unlike the specific electrode materials, such as Pt, Ir, IrO 2 , and SrRuO 3 , required for conventional ferroelectrics. [26,52]otably, HfO 2 and Al:HfO 2 have been utilized as interfacial   [45] The left inset figure shows the magnified image with interplanar distances, while the right inset shows the scheme for the crystallographic structure of ferroelectric orthorhombic phase.b) The polarization-electric field curves of Pt/HZO (1.5 nm)/NSTO capacitor measured at a frequency of 500 kHz.Summary of changes in c) remanent polarization (P r ) [45,54] and (d) coercive field (E c ) [48,55] values with varying thickness in literature.a,b) Reproduced with permission. [45]Copyright 2021, IEEE.
33a,53] Owing to this compatibility with industry-friendly materials and processes, emerging structures such as ferroelectric FinFETs, R-FeFET, and GAA FeFETs have been demonstrated.
Unlike conventional ferroelectrics with a stable polar phase, the ferroelectric o-phase in fluorite-structured ferroelectrics is metastable.Thus, it is difficult to completely suppress the formation of nonferroelectric secondary phases.This metastability causes difficulties in achieving spatially uniform and invariable properties without the so-called "wake-up effect" (a phenomenon in which P r value increases while undergoing repetitive electric field cycling) during repetitive polarization switching.The formation of a stable monoclinic phase can be suppressed by optimizing the doping concentration and RTP conditions; however, it is more difficult to suppress the formation of the t-phase, which is known to be the origin of the wake-up effect. [63]t was recently suggested that ferroelectric phase formation in fluorite-structured oxide thin films occurs via a two-step process: 1) formation of a precursor t-phase at elevated temperatures and 2) transformation to the ferroelectric o-phase during cooling. [64]During this process, the t-phase might be retained if the time for o-phase formation is insufficient; therefore, additional low-temperature annealing can decrease the fraction of the t-phase. [65]Another way suggested by Joh et al. is to utilize deep-ultraviolet (DUV) irradiation, in which the DUV densifies the film and initiates nucleation of t-phase at lower temperature by photochemical cleavage of resulting organic residues. [66]he DUV irradiation lowers the crystallization temperature for the t-phase formation during RTP and finally facilitates the transformation from the t-phase to the o-phase during the cooling step of the RTP. [66]The relative fractions of the various phases in fluorite-structured ferroelectrics can also be affected by impurities originating from the metal-organic precursors used for ALD, resulting in a switching time distribution during nucleation-limited polarization switching. [67]6b,7] Fluorite-structured ferroelectric thin films fabricated by ALD are generally polycrystalline with a weak preferred orientation.Consequently, characteristic parameters, such as P r and E c , can have grain-to-grain variations.Furthermore, the defective grain boundary region affects the ferroelectricity and switching speed of fluorite-structured ferroelectrics.Therefore, it is difficult to induce spatially uniform ferroelectric properties in fluoritestructured oxide thin films.Despite the importance of spatially uniform properties in ultra-large-scale integrated circuits with ferroelectric memory, highly textured polycrystalline fluoritestructured oxide thin films have rarely been studied.Epitaxial thin films have been reported; however, specific deposition techniques, such as pulsed laser deposition (PLD), and molecular beam epitaxy (MBE), are required to grow epitaxial films.Further, these processes are not suitable for CMOS technology with the state-of-the-art node, unlike ALD, physical vapor deposition (PVD), or metal-organic chemical deposition (MOCVD).Recently, there have been promising reports on polycrystalline films with preferred orientations.Schenk et al. [69] examined the texture of doped HfO 2 thin films.The 10 nm-thick Si:HfO 2 film exhibited a weak (111) preferred orientation, whereas the 10 nm-thick La:HfO 2 film exhibited a weak (002) preferred a) Confirmed ferroelectricity by piezoresponse using piezoresponse force microscopy (PFM).The accurate composition was not presented.
orientation, as shown by the pole figure in Figure 3a. [69]lthough the effect of the dopant species on the preferred orientation is not completely understood, the enhanced ferroelectricity in the La:HfO 2 thin film can be understood based on differences in texture. [70]Notably, a recent report by Lee et al. [45b] on the (112) texture observed in Hf 0.5 Zr 0.5 O 2 films suggested that a highly textured polycrystalline film is formed within ultrathin films.Figure 3b shows the pole figure of the (112)  planes in 2 nm-thick Hf 0.5 Zr 0.5 O 2 thin films, which is completely different from the weak preferred orientations observed in the ≈10 nm thickness regime.Further studies are required to expand the thickness regime for the fiber texture observed in sub-3 nm films.45b] As shown by the high-resolution scanning transmission electron microscopy (STEM) image obtained using aberration-correction techniques (Figure 3c), [71] the m-phase (M2), t-phase (T), and o-phase with different orientations (O3 and O4) coexist in a single grain.The domain boundaries retard the propagation of the domain walls, resulting in decreased domain wall velocity, although the impact of this effect should be much weaker than that of grain boundaries.FeFETs with a sufficiently high switching speed can be achieved when the device fabrication process is optimized, as discussed in detail in Section 4.
Owing to the aforementioned polycrystallinity, weak preferred orientation, intergranular nanoscale polymorphism, and spatial nonuniformity in ferroelectricity can occur.Figure 3d shows the distribution of remanent strain, as analyzed using piezoresponse force microscopy (PFM), whereas Figure 3e shows selected piezoresponse curves for 10 nm-thick Si:HfO 2 films, which demonstrate spatial nonuniformity. [72]The transmission Kikuchi diffraction patterns (Figure 3f ), which have recently been used to examine the texture of ultrathin films, demonstrate the spatial distribution of various orientations. [73]Currently, polycrystalline films with strong preferred orientations cannot be formed using ALD; therefore, practical solutions are urgently required to realize the ultra-large-scale integration of ferroelectric memories based on HfO 2 .(d). f) The transmission Kikuchi diffraction patterns from ferroelectric Si:HfO 2 thin film. [73]a) Reproduced with permission. [69]opyright 2019, Wiley-VCH.b) Reproduced with permission. [45]Copyright 2021, American Chemical Society.c) Reproduced with permission. [71]Copyright 2018, Wiley-VCH.d,e) Reproduced with permission. [72]Copyright 2014, Wiley-VCH.f) Reproduced under the terms of the CC-BY Creative Commons Attribution 4.0 International license (https://creativecommons.org/licenses/by/4.0). [73]Copyright 2021, The Authors, published by AIP Publishing.

Ferroelectric Memories Based on Fluorite-Structured Ferroelectrics
As discussed in the previous section, fluorite-structured ferroelectrics have several advantages over conventional ferroelectrics, although various issues are yet to be solved.In this section, recent studies demonstrating the advantages of these materials or showing feasible solutions for current issues are reviewed.Among the three types of ferroelectric memory devices introduced in this review, 1T1C FeRAMs have an intrinsic issue with cell size.Although 1T1C FeRAMs and DRAMs have equivalent cell structures, the footprint (15-20 F 2 ) of FeRAM cells is larger than that of DRAMs (6-8 F 2 ) because of the plate line requirement.Consequently, when the feature size (F) decreases, the practical cell area of 1T1C FeRAMs is considerably larger than those of other candidates, including FeFETs (4-8 F 2 ) and FTJs (4 F 2 ).Thus, in this section, we focus on FeFETs and FTJs rather than 1T1C FeRAMs.Various targets are available for emerging ferroelectric memories based on fluorite-structured ferroelectrics.Additionally, many approaches for physically scaling down and improving the performance of ferroelectric memory devices have been reported.In the following sections, we review studies on ferroelectric memories for classical computing systems as well as for future computing paradigms.

FeFET
A FeFET (channel width: 80 nm, length: 150 nm) with ferroelectric Si:HfO 2 was first demonstrated in 2011, and its cross-sectional TEM image (top panel) and gate voltage (V g )drain current (I d ) transfer curve (bottom panel) are shown in Figure 4a. [74]In this device, 8.5 nm-thick Si:HfO 2 was utilized as the gate dielectric, and the thickness of interfacial SiO x was ≈1.2 nm.When RTP was conducted at 1000 °C, the memory window was ≈1.0 V, which was expected to decrease to ≈0.65 V after 10 years based on extrapolation of the retention test results. [74]n 2012, a FeFET with a 28 nm channel length was demonstrated, and its cross-sectional TEM image (upper panel) and V g -I d transfer curve (bottom panel) are shown in Figure 4b. [39]In this FeFET,  FinFET, e) a recessed channel FeFET, and f) a gate-all-around FeFET, respectively.a) Reproduced with permission. [74]Copyright 2011, IEEE.b) Reproduced with permission. [39]Copyright 2012, IEEE.c) Reproduced with permission. [108]opyright 2017, IEEE.d) Reproduced with permission. [109]Copyright 2020, IEEE.36c] Copyright 2020, IEEE.36d] Copyright 2021, The Authors, published by IEEE.
the thickness of ferroelectric Si:HfO 2 was thinner than 10 nm, whereas the thickness of the SiO 2 interlayer (IL) was ≈1 nm.The FeFET endured up to 10 4 switching cycles with a memory window of 0.6 V, and extrapolation of the retention test results indicates that the programmed and erased states should be retained for >10 years.Furthermore, a switching speed of 20 ns was achieved.Considering the short research history of fluorite-structured ferroelec-trics, this performance is highly impressive, even with a channel length of 28 nm.Notably, following the first report on Si:HfO 2 in 2011, a 28 nm channel length FeFET was demonstrated within 1 year, [39] whereas the physical scaling of FeRAMs has remained at the 130 nm technology node for a few decades.Numerous FeFETs with fluorite-structured ferroelectric gate oxides have since been reported, and selected results are summarized in Table 4. Extrapolated results.IL: interfacial layer.
Various issues are associated with the scaling down of MOS-FETs due to the imperfect control of channel conductance, which are generally called "short-channel effects". [7]Decreasing the channel length decreases the relative fraction of the practical active region, and it becomes more challenging to completely turn off MOSFETs.Because the fundamental structure of FeFETs is equivalent to that of MOSFETs, various attempts have adopted solutions used previously in MOSFETs.For example, a fully depleted silicon-on-insulator (FDSOI) structure has been adopted, in which a thin Si layer formed on SiO 2 is used as the channel instead of the bulk Si substrate.In the FDSOI structure, the buried oxide layer below the thin Si channel reduces the parasitic capacitance between the source and drain, which is characteristic of bulk Si technology. [107]The buried oxide layer and fully depleted channel constrain electron flow between the source and drain to significantly reduce nonideal leakage currents.Dünkel et al. [108] demonstrated an FDSOI device with ferroelectric Si:HfO 2 that had physical channel lengths of 24 nm for 22 nm technology nodes.The cross-sectional TEM image (upper panel) and V g -I d transfer curve (bottom panel) of these FDSOI devices are shown in Figure 4c.With the 20 nm channel length, a memory window of 1.5 V was achieved with 10 µs program/erase pulses.Although the device endured up to 10 4 cycles, endurance remains an issue.Another issue is device array uniformity, as the standard deviation increases as the physical dimensions of FDSOI devices decreases.The reliability and uniformity issues are discussed in more detail in Section 5.
Diverse important demonstrations or suggestions have been made for the structural engineering of FeFETs with fluorite-structured ferroelectrics, such as ferroelectric FinFETs, R-FeFETs, and GAA FeFETs.The utilization of such 3D engineered devices could improve the controllability of channel conductance in ferroelectric gate dielectrics.Bae et al. [109] reported a FeFET with an SOI fin channel for a 25 nm technology node.The scanning electron microscopy image (upper panel) and V g -I d curve (bottom panel) of this FinFET device are shown in Figure 4d.As an example of FinFET memory (Figure 4e), an ultrafast (800 ps) switching speed with a memory window of 0.8 V was reported in the 25 nm HZO-based ferroelectric FinFET, [109] which extended the possible use of FeFET to GHz speed technology for CPU applications.
Another interesting structure is the R-FeFET, as it is believed that the memory window of FeFETs can be enhanced by adopting a recessed channel.36c] In addition, the subthreshold swing (SS) value can be improved by adopting the R-FeFET structure.Kim et al. [110] also suggested that R-FeFETs can effectively improve the performance of FeFETs based on computer simulations.They showed that the ratio between the dielectric and ferroelectric capacitances in the gate stack is critical for the memory window of the examined MFMIS R-FeFET structure.
Compared with FinFETs and R-FeFETs, the GAA structure is an even more futuristic structure for the sub-5 nm technology node.Lee et al. [36d] demonstrated a GAA double-layer (DL) nanowire FeFET with channel dimensions of 9.5 × 16 nm 2 .Figure 4f shows the cross-sectional TEM image (left panel) and V g -I d transfer curve (right panel) of the GAA nanowire FeFET.TEM imaging confirmed the presence of two gate stacks with a DL structure.The gate stack consisted of Si/SiO 2 (≈2.3 nm)/ TiN (1.5 nm)/HZO (5 nm)/TiN from the Si nanowire channel to the TiN gate.With a channel length of 250 nm and a ferroelectric HZO thickness of 5 nm, NCFET behavior could be achieved with an SS value as a low as 50 meV dec −1 .Although nonvolatile device operation for nonvolatile data storage was not extensively examined in this study, the GAA-FeFET structure could also be applied to nonvolatile FeFETs.36a] One of important research trend in FeFETs based on fluoritestructured ferroelectrics is increasing the endurance through repetitive program/erase cycles.In initial studies, the program/ erase endurance of these FeFETs was severely limited to less than 10 5 cycles.Figure 5a shows the cross-sectional TEM image (upper panel) and changes in the high and low threshold voltages with program/erase cycling (bottom panel) of a FeFET (channel length: 28 nm) with the Si:HfO 2 gate dielectric reported in 2013. [111]The memory window was as high as 0.9 V after 10 4 program/erase cycles but then rapidly decreased to ≈0.2 V upon increasing the number of program/erase cycles to 10 5 .
Gong and Ma [112] suggested that the number of cycles that can be endured by FeFETs with HfO 2 ferroelectrics is limited by charge trapping and interfacial trap generation. [112]They examined the V g -I d curves of degraded FeFETs after endurance tests and also studied the electric field distribution along the gate stack, considering the external field, P r , and dielectric constants.After the endurance test, the difference between the low and high threshold voltages decreased significantly, whereas the SS value significantly increased, indicating charge trapping and interfacial trap generation.Spatial and energetic distributions of the generated traps upon repeated field cycling were revealed by Bae et al. [109] using low frequency noise analysis in HZO-based FinFETs (Figure 5b), further confirming the origin of the limited endurance.Park et al. [7] suggested that the electric field across the SiO 2 IL is high enough to allow charge injection from the Si channel because the dielectric constant of IL (ε IL )value of SiO 2 is ≈7-8× lower than that of ferroelectric (ε F ) value of fluorite-structured ferroelectrics.Thus, a key parameter for the endurance limitation caused by charge trapping is E c × ε F /ε IL , which shows the electric field across the SiO 2 IL when E c is applied across the ferroelectric gate dielectric. [7]his parameter has values of ≈5.1, ≈3.2, and ≈7.7 MV cm −1 for PZT, SBT, and HfO 2 , respectively, which implies that charge injection through the SiO 2 IL and the resulting charge trapping and trap state generation are stronger in HfO 2 than in PZT and SBT.Thus, the engineering approach would be to decrease E c and ε F or to increase ε IL .
Because it is difficult to change the material parameters, E c and ε F, of the fluorite-structured gate oxide, a solution is to replace SiO 2 with dielectrics that have higher ε IL values. [80]igure 5c shows the cross-sectional TEM image of the gate stack (upper panel) and endurance test results for a FeFET with a SiO x N y gate dielectric reported by Ali et al. [80] SiO x N y growth was achieved using a two-step RTP sequence, in which the thin SiO 2 IL was first annealed under ammonia gas ambient followed by another annealing step in an O 2 /N 2 mixture. [80]he ε IL values of Si 3 N 4 and SiO 2 are 7.4 and 3.9, respectively, so the ε IL value of the 1.8 nm-thick SiO x N y layer should be between these two values and thus higher than that of SiO 2 .The memory window of the FeFET with the SiO x N y IL was 1.35 V, which then decreased to 0.6 V after 10 5 program/erase cycles. [80]For the FeFET with the SiO 2 IL, the initial memory window of 0.85 V totally disappeared after 10 5 program/erase cycles. [80]Thus, adopting the SiO x N y IL improved the number of switching cycles by more than two orders of magnitude.In addition to endurance, the retention of the FeFET was also enhanced with an increased memory window.This result demonstrates that the utilization of a high-ε IL IL can effectively enhance endurance by suppressing charge injection.
Figure 5d shows a device schematic (top panel), cross-sectional image of the gate stack (middle panel), and endurance test results (bottom panel) for a FeFET with a 4.5 nm-thick HZO gate dielectric and 1.5 nm SiN x IL.The IL formation step involved the thermal nitridation of the SOI substrate at 850 °C under ammonia gas ambient.The estimated ε IL value was ≈7.4, which is equivalent to that of Si 3 N 4 , suggesting that complete SiO 2 nitridation was achieved.An I on /I off ratio of more than 100 was observed, even after 10 10 program/erase cycles.Compared with the endurance of the FeFET with the Si:HfO 2 gate dielectric (10 4 program/erase cycles, Figure 5a), the endurance of the FeFET with the SiN x IL was enhanced by approximately six orders of magnitude. [113]Therefore, adopting a dielectric with an even higher ε IL could further enhance the endurance.Kim et al. [114] reported improved endurance for a Mo/HZO (10 nm)/TiO 2 (≈2 nm)/SiO x /Si (n+) capacitor, where the TiO 2 IL was formed by oxidizing a sputter-deposited Ti layer.The number of switching cycles reached ≈10 9 , although the endurance test had to be stopped because of frequency limitations arising from the rather large device dimensions.
Other issues that have also been reported are read-after-write delay and retention loss. [102,115]When the reading process is induced immediately after writing pulse, the charges yet to be detrapped can deviate the threshold voltage from the ideally-expected value with resulting in the decrease of MW during the read process. [102]Ni et al. reported that the delay time for the read operation after the write pulse should be 1 µs in positive write pulse and 100 µs in negative write pulse in TiN/HZO (10 nm)/SiO 2 /n-Si gate stack FeFET. [102]he calculated detrapping charge densities were 2.1 × 10 19 cm -3 and 1.9 × 10 18 cm -3 in each write pulse direction, which were quantitatively consistent with defect densities in 10 nm-thick HfO 2 film deposited using ALD. [93]Hoffmann et al. suggested that the readafter-write delay could be resolved by reducing the film thickness of the ferroelectric layer resulting in decreased number of bulk charge trap sites in the film. [115]In the W/HZO (4.5 nm)/SiN x (1.5 nm)/p-Si gate stack FeFET, the read-after-write latency was negligible with sufficient MW even at the 10 ns delay time between the read and write pulses.However, decreasing film thickness could cause an increase in the depolarization field, so the retention of the device was deteriorated.The retention issue in this case could be resolved by modulating the work function of the gate metal or by decreasing P r in the level of reducing built-in field with sustaining sufficient MW. [115] Moreover, restraining the generation of fixed charge in the IL during fabrication should also be guaranteed to have sufficient retention properties. [115] few studies have focused on the high-temperature imprint issue, which is related to the drift of charged defects, such as   [111] Copyright 2013, IEEE.b) Reproduced with permission. [109]Copyright 2020, IEEE.c) Reproduced with permission. [80]Copyright 2018, IEEE.d) Reproduced with permission. [113]Copyright 2021, IEEE.
oxygen vacancies, as discussed in Section 5. [116] Decreasing device-to-device variation (DTDV) is also an important issue for large-scale integrated circuits with FeFETs, as discussed in detail in Section 5.

FTJ and Switchable Diode
Unlike three-terminal FeFETs, FTJs and switchable diodes are two-terminal devices, suggesting that the well-known crossbar array can be applied.In contrast to 1T1C FeRAMs or FeFETs, FTJs utilize charge conduction by tunneling through an ultrathin fer-roelectric layer, and the tunneling electroresistance can be controlled by the polarization state of the ferroelectrics.Although a polarization-controlled tunneling current was discovered in 1971 by Esaki et al., [117] solid-state devices utilizing an FTJ were not demonstrated until 2012. [118]This long delay in the development of solid-state devices has been attributed to difficulties in fabricating high-quality ultrathin films and interfaces.Recent advances in film deposition techniques are now accelerating the development of FTJs, and the discovery of HfO 2 -based ferroelectric should provide materials breakthrough for CMOS-compatible FTJ devices.
TEM image (upper panel), current-voltage curves (middle panel), and retention test results (bottom panel) of an FTJ with a TiN/Si:HfO 2 (4.5 nm)/IL/TiN stack.As shown by the currentvoltage curves, two different conductance states depending on the two polarization states as well as self-rectifying behavior could be observed.The performance of the FTJ, including the I LRS (LRS current)/I HRS (HRS current) ratio or tunneling electroresistance ratio (TER = (R HRS − R LRS )/R LRS ) and retention, was strongly affected by the thickness of the IL.It should be noted that the I LRS /I HRS ratio and TER will be used together, because both the terms are frequently used in previous studies.The IL thickness was decreased below 1 nm to achieve an E dep /E c value lower than 1, which effectively enhanced the I LRS /I HRS ratio and retention properties.As shown by the retention test results, the I LRS /I HRS ratio decreased with increasing retention time, possibly owing to E dep arising from the physical distance between the surface polarization of Si:HfO 2 and the charge carriers in the bottom electrode.This self-rectifying behavior, which is not generally expected for FTJs based on MFM structure, is an important advantage of the Si:HfO 2 -based FTJ in this study.The sneak current is a well-known issue in resistance-based memories utilized in crossbar arrays because it can cause read failure.Thus, an external selector device is typically fabricated to achieve a randomly accessible crossbar array; however, with self-rectifying properties, no external selector device is required.In MFIM and MFIS, the self-rectifying property can appear because the tunneling current mostly manifests through the dielectric layer when the polarization is large enough; however, the ratio of current in low resistance state (LRS) under reading and opposite direction of reading bias should be greater to be applied to large integrated circuits, since as the size of array increases the nonideal contribution from the accumulated sneak current under read process will be augmented.
Following the pioneering work of Fujii et al., [5] numerous FTJs with fluorite-structured ferroelectrics have been reported, as summarized in Table 5. FTJs have many important performance parameters, but for fluorite-structured oxide-based FTJs, achieving high TER, and endurance is the most challenging.In this section, some important progress on these properties in FTJs is briefly introduced.
The high I LRS /I HRS ratio, as well as high I LRS, is critical for the reliable operation of FTJs because during the read process, resistance state would be determined by the current level sensed by the sensing amplifier in the practical FTJ arrays.Moreover, the device with high I LRS /I HRS ratio and high on-current is beneficial for scaling down and low operation voltage.The TER value of more than 10 (I LRS /I HRS ratio more than 11) is enough for an accurate computing process when a selector device with sufficient rectification ratio is utilized. [9]However, in the practical large size crossbar array (CBA), the DTDV can cause reading failure for the cells that strongly deviate from the average properties, requiring a sufficient sensing margin to prevent the reading failure. [119]Therefore, the frequently observed I LRS /I HRS ratio of ≈10 2 in FTJs based on fluoritestructured ferroelectrics (See Table 5.) is not sufficient for the CBA, and requires further studies.Besides, the on-current of FTJs is generally lower compared to those of the other bipolar resistive switching memories, (See Table 5.) implying that gen-erally longer time is required to conduct sufficient charges to be sensed by sense amplifiers. [120]Thus, further studies are urgently required to increase the on-current of FTJs.
The I LRS /I HRS ratio is strongly correlated with the engineering of the potential barrier for electron/hole tunneling. [121]o achieve a high I LRS /I HRS ratio, asymmetric top and bottom contacts are required, and several different stacks can be employed for FTJs with high I LRS /I HRS ratios.First, MFM capacitors with two different metals or MFIM capacitors can be used.Owing to the work function difference between the two metals of the top and bottom electrodes or the existence of an insulating layer, the I LRS /I HRS ratio is higher than those of the symmetric MFM capacitors.Second, MFS or MFIS capacitors with semiconducting materials on one side can be used.Through the changes of the accumulation/depletion states in the semiconducting layer, the tunneling conductance can be effectively controlled by polarization in the ferroelectric layer.These two approaches have also been used in fluorite-structured oxide-based FTJs.The former method is beneficial for achieving a high switching endurance at rather low defect concentrations in the interfacial region.The effect of the SiO 2 IL on the endurance of the FeFETs is discussed in Section 4.1.1.By contrast, the higher I LRS /I HRS ratios can be obtained more easily using the latter method with more asymmetric structure by one semiconductor contact, although it is difficult to achieve high endurance, especially on Si, owing to the SiO 2 IL.
Figure 6b shows schematic electric band diagrams (upper panel) of the high-resistance state (HRS) and LRS, resistanceelectric field curve (middle panel), and endurance test results (bottom panel) for a TiN/TiO 2 /HZO/W stacked FTJ.Various electrode materials were examined, but the W electrode allowed ferroelectricity with a high P r to be achieved with film thicknesses of <5 nm. [122]As shown by the resistance-electric field curve, this FTJ device has a tunneling electroresistance ratio value of 16.Furthermore, the endurance test results revealed that the FTJ could endure up to 10 7 cycles with relatively small changes in the HRS and LRS currents.However, the I LRS /I HRS ratio decreased rapidly when the number of program/erase cycles increased from 10 7 to 10 8 .Moreover, there were negligible changes in the HRS and LRS conductance during the retention test for up to 10 5 s.Thus, the MFIM FTJ is beneficial for achieving sufficient reliability, such as switching endurance and retention, which are important for practical solid-state devices.
Figure 6c shows the device schematic (top panel), current density-write voltage curve (middle panel), and endurance test results (bottom panel) for a W/Hf 0.8 Zr 0.2 O 2 (1 nm)/SiO 2 (1 nm)/ Si capacitor. [123]In this device, a 1 nm-thick Hf 0.8 Zr 0.2 O 2 film grown directly on Si was utilized as a ferroelectric layer.The film thickness of 1 nm corresponds to the thickness of two unit cells of ferroelectric orthorhombic HfO 2 .As shown by the current density-write voltage curve, an I LRS /I HRS ratio as high as ≈100 was achieved, which to the best of our knowledge is one of the highest I LRS /I HRS ratios for fluorite-structured oxide FTJs to date.As shown by the endurance test results, the I LRS /I HRS ratio was as high as ≈10 after 1000 switching cycles but then gradually decreased with further cycling, possibly due to the charge trapping or interfacial trap generation, as reported for the gate stack of FeFETs. [112]Switchable diode devices; b) J LRS : current density of LRS state.
Figure 6d shows the device schematic (top panel), resistance-voltage curve (middle panel), and endurance test results (bottom panel) for a 3D double-layered FTJ with a TiN/HZO (9 nm)/Pt stack reported by Chen et al. [124] Although only two vertical layers were used, the number of layers could be increased by increasing the number of alternating deposition cycles for the metal and insulator. [124]The TER of the 3D FTJ was >10 when the pulse height was >8 V and the program/erase pulse width was fixed at 100 ns. [124]As shown by the resistancevoltage curve, a drastic conductance change occurred at the coercive voltage of the capacitor, indicating that the conductance was controlled by the polarization state of the ferroelectric HZO thin film.As shown by the endurance test results, the changes in the resistance of the HRS and LRS in both the top and bottom cells were negligible.
Another type of 1R FeRAM is a switchable diode with ferroelectric layer (FE diode).Bae et al. first reported FE diode based on 5 nm IGZO with 7 nm HZO ferroelectric layer in 2021. [125]s shown in left panel of Figure 6e, charge carriers of the IGZO layer can be depleted or accumulated depending on the polarization state of ferroelectric layer by which the energy barrier height and resulting electronic conductance could be modulated with enabling a nonvolatile memory function.With the assistance of the oxide semiconductor layer, the ON/OFF ratio in the DC sweep can be achieved as high as 3 × 10 5 as shown in the middle panel of Figure 6e.It should be noted that the current-voltage hysteresis of the FE diode is totally different from that of FTJ as shown in the middle panel of Figure 6e.By the polarization state of ferroelectric layer, the polarity of the diode changes, which is distinguished from self-rectifying FTJ with a fixed polarity of rectifying behavior.Since the operation of the device is based on the polarization reversal, the speed of the resistance switching can be GHz scale as shown in right panel of Figure 6e.They also confirmed robust endurance up to 10 9 cycles.

Future Computing Paradigms
8b,162] The basic operation in bio-inspired computing, such as spiking neural networks, is based on vector-matrix multiplication (VMM) between the voltage input generated by artificial spiking neurons and an adjustable resistors, called synaptic device, wherein the currents are summed according to Kirchhoff's law.In artificial neural networks, such as recurrent neural networks and convolutional neural networks based on deep neural networks, the VMM is operated using activation functions and weighting memories, which work like neurons and synapses, respectively, to mimic the topologies of biological brains.Further details about network structures and algorithms are beyond the scope of this review, and the terminology of synaptic device and potentiation/depression of weighting value, which are typically used for spiking neural networks, are used for all the studied neural systems.
The synaptic device should exhibit adjustable conductance, and the artificial spiking neuron should be able to generate voltage spikes with leaky and accumulative properties.To realize these properties, memristive devices are required, which was first suggested by Chua [163] and experimentally demonstrated by Strukov et al. [164] using resistive random access memory in 2008.The first ferroelectric-based memristor device was the FTJ reported by Chanthbouala et al. [165] in 2012.Subsequently, numerous synaptic and artificial spiking neurons based on FTJ and FeFET structures have been reported, and recent progress and remaining issues for neuromorphic devices based on fluorite-structured ferroelectrics are reviewed here.
First, for synaptic devices, the FTJ structure is feasible for achieving a highly integrated memory density.The conductance modulation of FTJs in neuromorphic computing is analogous to switching the polarization states of ferroelectric with asymmetric structures.However, the conductance states in FTJs for neuromorphic computing should have analog-like variations.Schematic structures and TEM images of a biological synapse and an artificial TiN/HZO (5.5 nm)/TaN (2.5 nm)/W-structured synaptic device are shown in the upper panels of Figure 7a.Given that polycrystalline fluorite-structured ferroelectrics are composed of multiple domains with different E c , [63a,67b,71,166] the fraction of polarization states in such devices can be varied using appropriate external fields.Assuming that the polarization is uniaxial, the ferroelectric layer in the TiN/HZO (5.5 nm)/TaN (2.5 nm)/W FTJ can be considered a bundle of parallel resistors.
To apply the FTJ as a synaptic device, a large TER (or I LRS /I HRS ratio) with linear and symmetric modulation is required to obtain the optimized weight calculated through algorithms. [167]In addition, the retention should be more stable than that for binary computing and the current density should be sufficient for fast sensing. [120]The most common method for increasing the TER (or I LRS /I HRS ratio) of an FTJ is to increase the asymmetry of the energy band structure, which degrades the linearity and retention because of the built-in bias.Guo et al. [156] compared FTJs with MFIM and MFIS structures, in which the TER ratio of MFIS (40) was 48% higher than that of MFIM, but the TER value degraded more rapidly owing to less charge concentration for stabilizing the polarization states, and nonlinearity of conductance modulation was increased.Moreover, the domain wall propagation and polarization switching kinetics of the fluorite-structured ferroelectric determine the fraction of polarization switching that follows an exponential relation with the induced voltage or time, resulting in harsher conditions for tuning the conductance.The middle panel of Figure 7a shows the conductance potentiation of the TiN/HZO (5.5 nm)/TaN (2.5 nm)/W FTJ, where the scheme 1, 2, and 3 are described on the left side.Here, conductance variation by identical pulses results in a rapid increase with a nonlinear shape, and tuning using Scheme 1 gives the most ideal shape.However, changing the voltage pulse shape in the system requires a larger and more complicated circuit design. [168]Berdan et al. [169] recently suggested that the nonlinear variation of conductance can be modified into a linear shape under identical pulse inputs by applying a logarithmic wordline driver.Furthermore, Lee et al. [170] demonstrated that domain wall hopping along the a-axis requires higher energy (≈1.3 eV), which implies that crystallographic orientation control to regulate domain reversal can be utilized for the linear conductance tuning.In addition, the scaling down of the film to obtain a sufficient current density can cause retention degradation, resulting in reliability issues and difficulties with the fabrication of sub-5 nm film that still requires further studies, as discussed in detail in Section 3.
When an FTJ is implemented in the crossbar array for integration, the sneak current can cause serious problems.37d] Simulations showed that a 10% sensing margin could be achieved with rectifying ratio of 1000 in a 4000 square single crossbar array, although higher rectifying ratios are still required for more integrated system.Additionally, decreasing the DTDV is an important issue, as a DTDV of <3% is required for accuracy >90%. [9]The issues associated with decreasing the DTDV are discussed in Section 5.
167a,171] As the weighting from input to output is conducted through the channel conductance modulated by the gate electrode, it is easier to control the thickness of the ferroelectric than in FTJs with larger P r and lower E dep .Xi et al. [172] reported an HZObased ferroelectric Schottky barrier FET (Fe-SBFET) using a NiSi 2 metal source drain and p-Si.This device achieved a TER value of up to 416 with a linear modulation shape, which is much higher than those of FTJs (≈200). [173]The structure of the Fe-SBFET and the conductance modulation scheme are shown on the left side of Figure 7b, whereas the channel charge states and their energy states depending on the pulse inputs on the gate are presented on the right side of Figure 7b.The high TER may originate from the surface charge of the ferroelectric material modulating the Schottky barrier by introducing holes not only in the channel but also at the NiSi 2 /p-Si interface in the vertical direction.
The disadvantages of FET-based synaptic devices are their poor endurance and large feature size as compared to FTJs.As discussed in Section 4.1.1,in Si-based devices, a low-k defective interlayer, such as SiO x N y can be formed, degrading endurance and reliability.It has been suggested that thin-film transistors, high-k interlayers, metal interlayers, and annealing conditions could also relieve these problems. [9,174]In particular, an impressive endurance of ≈10 10 cycles [174a] and a DTDV of 3.9% [9] have been reported in the application for neuromorphic computing device.When scaling down, the number of domains, as well  Cross-sectional TEM image of a device having L = 30 nm and W = 80 nm for the channel length and width, respectively."G", "D", and "S" indicate gate, drain and source terminals, respectively.Middle: pulsing scheme for the accumulation in the OFF state consists of a train of identical pulses having amplitude V P and duration t P. Bottom: I D change from OFF to ON state with pulses V P = 2.2 V, t P = 1 µs.a) Reproduced with permission. [156]Copyright 2021, American Chemical Society.b) Reproducedwith permission. [172]Copyright 2021, The Authors, published by American Chemical Society.c) Reproduced with permission. [175]Copyright 2018, IEEE.d) Reproduced with permission. [10]Copyright 2018, Royal Society of Chemistry.
as the short-channel effect discussed in Section 4.1.1,can be problematic for synaptic devices.Because conductance modulation in ferroelectric-based synaptic devices involves tuning the fraction of domain directions, a large number of domains are required to achieve sufficient conductance states.Mulaosmanovic et al. [167a] reported only 1-3 domains in TiN/Si:HfO 2 / SiON/Si (length: 30 nm, width: 80 nm), but Grimley et al. [71] showed the existence of multidomains in single nanoscale grains.Thus, additional studies should be conducted on the critical size of domain nuclei.R-FeFET, FinFET, and GAA-FeFET structures are also possible solutions to increase channel length in the same feature size as conventional FET structures.Seo et al. [175] fabricated an FinFET (length: 120 nm, width: 50 nm, fin height: 100 nm) with an 8 nm-thick HZO layer, that had a five times larger effective channel width than a planar-type FeFET, and confirmed more than 32 state levels, as shown in Figure 7c.
However, nanoscale FeFETs with a few domains can be utilized for artificial spiking neurons. [10,176]A TEM image of the nano-scaled FeFET fabricated by Mulaosmanovic et al. [10] is shown in the upper panel of Figure 7d.Under input pulses, the threshold voltage switched abruptly with a sudden increase in the channel current (middle panel, Figure 7d).One of the simplest but most effective neuron models is the leaky-integrateand-fire model. [177]In this model, the neuron is a leaky integrator with a threshold value, and once the integrated potential reaches the threshold, the neuron generates a potential spike, called the action potential.Similarly, as shown in the bottom panel of Figure 7d, the nano-scaled FeFET showed the integration phase until the switched domain was nucleated and then fired when a critical number of pulses was reached.The nucleation of a switched domain in a polycrystalline fluoritestructured ferroelectric is a stochastic and abrupt process, whereas subsequent domain wall propagation is accumulativ e. [63a,166b,170,178] In the nano-scaled FeFET, nucleation-limited switching was confirmed based on the Du-Chen model, and the nucleation was stochastically modeled by the Poisson process, [179] which is advantageous for avoiding overfitting and local minimum optimization. [180]Moreover, Mulaosmanovic et al. [10] suggested that E dep induction can be used to implement leaky behavior, and Dutta et al. [176] reported a circuit design for a reset process with adaptive behavior of the output rate under consistent input.
FTJs and FET-based ferroelectric synaptic devices have several advantages as well as remaining issues.FTJs are more suitable for implementation into crossbar arrays at high densities, but issues such as current density, retention, and sneak currents must be resolved.In FET-based devices, endurance and the number of states in scaled-down devices can be problematic.For both device types, linearity, symmetricity, and DTDV could be obstacles to utilization in neuromorphic systems.However, nano-scaled FeFETs can be utilized for artificial spiking neurons.Nonetheless, only a limited number of studies have investigated synaptic devices, probably because of the less importance of high-density integration in replacing conventional CMOS-based circuits in neuromorphic computing compared to that of synaptic device.In addition, fewer materials with suitable properties for artificial spiking neurons have been reported as compared to those with synaptic properties.
Therefore, additional research on spiking-based neural-network systems is essential.

Current Issues in Ferroelectric Memories Based on Fluorite-Structured Ferroelectrics from a Materials Science Viewpoint
As discussed in Section 4, fluorite-structured ferroelectrics have shown promising performance despite the rather short history of research on ferroelectric memories.Nonetheless, various issues remain that require urgent solutions.The most difficult problem to resolve is decreasing the DTDV.Fluoritestructured ferroelectrics grown via ALD are amorphous in their as-deposited state and crystallize during the subsequent RTP.As discussed in Section 4.1, it is challenging to obtain a strong preferred orientation, even when the formation of the nonferroelectric second phase is effectively suppressed.Although a few epitaxial films have been fabricated using PLD or MBE by selecting special substrates, highly textured films directly grown on Si substrates have rarely been reported. [181]Some textured ferroelectric fluorite-structured oxide films have been achieved on Si, [46b,d,182] but they generally have thicknesses of <3 nm, which hinders suppression of the leakage current.Surface engineering of hafnia films, together with an appropriate annealing condition, [183] is also important to control preferred orientation in thin film hafnia (Figure 8a).Moreover, as the crystallization temperature increases with decreasing film thickness, it is difficult to crystallize such ultrathin films. [184]On metal electrodes, the selection of suitable metallic materials can induce texture in fluorite-structured ferroelectrics.In fact, highly textured film growth has been realized on Pt electrodes and the effect of TiN electrodes on the texture of fluorite-structured ferroelectrics has been reported. [52,185]Therefore, it is possible to obtain highly textured films for MFMIS FeFETs or MFIM FTJs by growing the fluorite-structured ferroelectric thin films on metallic materials.However, the local epitaxial relationship between the electrode material and fluorite-structured ferroelectrics would require a lower crystallization temperature or crystallization during the ALD process.Nonetheless, the development of methods for the direct growth of highly textured fluorite-structured ferroelectric thin films on Si substrates remains critical for industrial applications.
Endurance is another issue that must be resolved.As suggested in Section 4.1, inserting a high-ε IL dielectric between the fluorite-structured ferroelectrics and Si could mitigate endurance degradation by charge injection. [80]However, even when this limitation is overcome, the intrinsic endurance of fluoritestructured ferroelectrics remains lower than that of conventional ferroelectrics.The E c /E bd ratio (E bd : Breakdown field) has been proposed as a critical parameter that is strongly correlated with the intrinsic endurance limit by a hard breakdown degradation mechanism. [186]The E c /E bd ratios of fluorite-structured ferroelectrics (20%) are higher than those of PZT (7%) and SBT (10%).Although the endurance of MFM capacitors or FeFETs is already sufficient for storage memory applications, such as flash memory, further improvements are necessary for other memory hierarchies. [187]Moreover, there is generally a trade-off between the endurance and operation speed of ferroelectric memories, which is the so-called endurance-speed dilemma.To date, high endurance has generally been reported with rather low pulse heights, suggesting that the saturated polarization value could not be fully utilized for programming/erasing. [7] However, high-speed results have been reported for high pulse heights.Although decreasing the E c /E bd ratio would provide the ultimate solution to this issue, to the best of our knowledge, there are currently no straightforward methods for achieving this goal.Fabrication of laterally heterogeneous phases of oand t-phases (Figure 8b) could be a viable strategy for reducing E c in fluorite-structured ferroelectrics, because first principles calculations predict that the ferroelectric domain nucleation can be initiated with a significantly low energy barrier at the phase boundaries. [188]It should be noted that decreasing the distributions of E c and E bd is also highly important, although this issue has rarely been discussed.When the standard deviation of E c , σ(E c ), decreases, the electric field required to fully switch fluorite-structured ferroelectrics can be significantly decreased.Furthermore, hard breakdown in fluorite-structured ferroelectrics is also a local failure mechanism, which might occur frequently in regions with high defect concentrations, such as grain boundaries.This issue is particularly important, as ferroelectric fluorite-structured oxide thin films have a columnar structure, in which grain boundaries connect the top and bottom electrodes.
Decreasing the defect concentration in fluorite-structured ferroelectric films is also critical for enhancing uniformity and endurance.Intrinsic defects, such as oxygen vacancies, which have been extensively studied in this field, are considered to contribute to the wake-up effect, fatigue, hard breakdown, and high-temperature imprinting. [116,189]68a,190] Frequently used TiN and Si may partially reduce fluorite-structured ferroelectrics owing to the high formation free energies of TiO 2 and SiO 2 .The utilization of W electrodes could mitigate the wake-up effect in ferroelectric HZO, as suggested by Kim et al., [41] possibly because of the lower formation free energies of WO 3 and WO 2 .However, better electrode materials that can suppress the leakage current with a higher work function should be investigated.

Conclusion and Perspectives
The revival of ferroelectric memories were reviewed, from their history with conventional materials to recent research on emerging fluorite-structured ferroelectrics.As fluorite-structured ferroelectrics are chemically identical to current gate dielectrics, their advantages in terms of scalability, CMOS compatibility, established deposition techniques, and compatibility with industry-friendly materials are widely known in the semiconductor community.Fluorite-structured ferroelectrics differ from conventional perovskite-structured ferroelectrics because of the metastability of the ferroelectric phase, high bandgap, low ε F , and high E c .The E c /E bd ratio of fluorite-structured ferroelectrics is lower than those of PZT and SBT; therefore, solutions are required to enhance endurance, despite the endurance currently being more than sufficient for storage memory applications.Moreover, there is a trade-off between the endurance  [183] Copyright 2021, IEEE.b) Reproduced with permission. [188]Copyright 2021, Elsevier Ltd. and operation speed of ferroelectric memories.To resolve this issue, the average E c value needs to be decreased, whereas the E bd value needs to be increased.Furthermore, decreasing the σ(E c ) and σ(E bd ) values could also effectively address the endurance-speed dilemma.In FeFET gate stacks and FTJ stacks, the (E c × ε F /ε IL ) value indicates the electric field across the IL and the degree of charge injection from the Si channel.Thus, inserting an IL with a high ε IL value may be a feasible alternative to engineering the E c or ε F values.For fluorite-structured ferroelectrics, the main issue with no clear solution is the direct formation of highly textured films on Si substrates.Although a few promising approaches have been reported recently, the obtained films are generally limited to the sub-3 nm thickness regime.Thus, urgent solutions are required to achieve texture control in thicker films for the practical large-scale integration of FeFETs.
Ferroelectric memories based on fluorite-structured ferroelectrics have promising material properties for various practical applications, from nonvolatile memories to artificial neurons or synaptic devices for neuromorphic computing.To target neuromorphic applications, additional device properties such as linearity, symmetry, and reliability of partially switched states (for long-term potentiation/depression) are required.Currently, achieving linearity with identical pulses is considered highly challenging based on the polarization switching mechanism described by Merz's law and the nucleation-limited switching model.However, important advancements have been made toward achieving symmetric potentiation/depression and stable multipolarization states.Despite these unresolved issues, the rapid progress in understanding and improving the material properties of fluorite-structured ferroelectrics within the first 15 years of research is expected to allow the development of nanoscale electronic devices based on fluorite-structured ferroelectrics in the near future.

Figure 2 .
Figure 2. a) Cross-sectional TEM image of 1.5 nm-thick Hf 0.5 Zr 0.5 O 2 (HZO) film grown on Nb:SrTiO 3 (NSTO) bottom electrode.[45]The left inset figure shows the magnified image with interplanar distances, while the right inset shows the scheme for the crystallographic structure of ferroelectric orthorhombic phase.b) The polarization-electric field curves of Pt/HZO (1.5 nm)/NSTO capacitor measured at a frequency of 500 kHz.Summary of changes in c) remanent polarization (P r )[45,54]  and (d) coercive field (E c )[48,55]  values with varying thickness in literature.a,b) Reproduced with permission.[45]Copyright 2021, IEEE.

Figure 5 .
Figure 5. a) A cross-sectional TEM image (top) with a device scheme inset figure and endurance test result (bottom) of 28 nm channel length FeFET.b) Schematic cross-sectional view of a gate stack (top) of HZO FE FinFET with three different trap states: Dit 1 at the channel surface, Dit 2 between FE HZO layer and DE SiO 2 layer, N ot in SiO 2 dielectric and in HZO ferroelectric, and their space-energetic mapping (bottom).c) Cross-sectional TEM image of gate stack (top) and endurance test result (bottom) of FeFET with TiN/Si:HfO 2 /SiO x N y /Si gate stack.d) Device scheme (top), cross-sectional TEM image of the gate stack (middle) and the endurance test result (bottom) of the FeFET with 4.5 nm HZO and SiN x interfacial layer (IL).a) Reproduced with permission.[111]Copyright 2013, IEEE.b) Reproduced with permission.[109]Copyright 2020, IEEE.c) Reproduced with permission.[80]Copyright 2018, IEEE.d) Reproduced with permission.[113]Copyright 2021, IEEE.

Figure 6 .
Figure 6.a) Cross-sectional TEM image (top), current-voltage curve (middle panel), and the retention test result (bottom) of the first FTJ with ferroelectric HfO 2 .b) A schematic band structure for HRS and LRS states (top), resistance-electric field curve (middle), and the endurance test result (bottom) of the first FTJ with MFIM stack with ferroelectric HZO and TiO 2 insulator.c) A device scheme (top), current-density-write voltage (V write ) curve (middle), and the endurance test result (bottom) of MFIS FTJ with 1 nm-thick Hf 0.8 Zr 0.2 O 2 film.d) A device scheme (upper panel), the resistance-voltage curve (middle) and endurance test result (bottom panel) of 3D FTJ with ferroelectric HZO.e) Left: Plausible mechanism related to high I LRS /I HRS ratio of 7 nm HZO/5 nm IGZO, resulting in the suppression of rectified off-state current at low applied positive (a) and negative (b) voltages.Middle: DC I-V curve showing a switchable diode property with a record high I LRS /I HRS ratio of 3 × 10 5 .Right: Color map of I LRS /I HRS ratio with various pulse widths and applied voltages.a) Reproduced with permission.[5]Copyright 2016, IEEE.b) Reproduced with permission.[122]Copyright 2020, Authors, published by AIP Publishing.c) Reproduced with permission.[123]Copyright 2021, Wiley-VCH.d) Reproduced with permission.[124]Copyright 2018, Royal Society of Chemistry.e) Reproduced with permission.[125]Copyright 2021, IEEE.

Figure 7 .
Figure 7. a) Top: Schematic structure of TiN/HZO/TaN/W ferroelectric tunnel junction and TEM image.Middle: Measured conductance as a function of pulse number using Schemes 1, 2, and 3 in case of potentiation.Read voltage is 1 V. Bottom: Measured I-V curves of TiN/HZO/W and TiN/HZO/ TaN/W stack FTJs, showing self-rectifying properties of the TiN/HZO/TaN/W FTJ device.b) Left: Schematic of the Fe-SBFET structure on the silicon on insulator and its conductance variation depending on the number of input pulses.Right: Schematic charge distribution in the Fe-SBFET depending on the number of input pulses and its energy band diagram.c) TiN/HZO (8.5 nm)/SiO 2 /Si structure FinFET scheme with its TEM image.The potentiation and depression property of the FinFET with sweep voltage within 1.2 and 1.5 V for reading is shown on the left side.d) Top: Cross-sectional TEM image of a device having L = 30 nm and W = 80 nm for the channel length and width, respectively."G", "D", and "S" indicate gate, drain and source terminals, respectively.Middle: pulsing scheme for the accumulation in the OFF state consists of a train of identical pulses having amplitude V P and duration t P. Bottom: I D change from OFF to ON state with pulses V P = 2.2 V, t P = 1 µs.a) Reproduced with permission.[156]Copyright 2021, American Chemical Society.b) Reproducedwith permission.[172]Copyright 2021, The Authors, published by American Chemical Society.c) Reproduced with permission.[175]Copyright 2018, IEEE.d) Reproduced with permission.[10]Copyright 2018, Royal Society of Chemistry.

Figure 8 .
Figure 8. a) Preferred orientation diagrams from first principles for single (upper panel) and double (bottom panel) surface treatments as functions of the chemical potential of H 2 O and HF.b) An illustration of a sharp boundary between the o-and t-phase, which enables a low-barrier ferroelectric domain formation.a) Reproduced with permission.[183]Copyright 2021, IEEE.b) Reproduced with permission.[188]Copyright 2021, Elsevier Ltd.

Table 2 .
The main advantages of fluorite-structured ferroelectrics are scalability, CMOS compatibility, and the applicability of wellestablished atomic layer deposition (ALD) techniques.With

Table 1 .
Summary of reports on the fluorite-structured ferroelectrics with high remanent polarization values.

Table 3 .
Summary of previous reports on ferroelectric HfO 2 -based films thinner than 5 nm.

Table 4 .
Summary of performance of FeFETs with Si channel in the literature. a)

Table 5 .
Summary of performance of FTJs and switchable diodes in the literature. a)