Dry Lithography Patterning of Monolayer Flexible Field Effect Transistors by 2D Mica Stamping

Organic field‐effect transistors (OFETs) based on 2D monolayer organic semiconductors (OSC) have demonstrated promising potentials for various applications, such as light emitting diode (LED) display drivers, logic circuits, and wearable electrocardiography (ECG) sensors. To date, the fabrications of this class of highly crystallized 2D organic semiconductors (OSC) are dominated by solution shearing. As these organic active layers are only a few molecular layers thick, their compatibilities with conventional thermal evaporated top electrodes or sophisticated photolithography patterning are very limited, which also restricts their device density. Here, an electrode transfer stamp and a semiconductor patterning stamp are developed to fabricate OFETs with channel lengths down to 3 µm over a large area without using any chemicals or causing any damage to the active layer. 2D 2,9‐didecyldinaphtho[2,3‐b:2′,3′‐f]thieno[3,2‐b]thiophene (C10‐DNTT) monolayer OFETs developed by this new approach shows decent performance properties with a low threshold voltage (VTH) less than 0.5 V, intrinsic mobility higher than 10 cm2 V−1 s−1 and a subthreshold swing (SS) less than 100 mV dec−1. The proposed patterning approach is completely comparable with ultraflexible parylene substrate less than 2 µm thick. By further reducing the channel length down to 2 µm and using the monolayer OFET in an AC/DC rectifying circuit, the measured cutoff frequency is up to 17.3 MHz with an input voltage of 4 V. The newly proposed electrode transfer and patterning stamps have addressed the long‐lasting compatibility problem of depositing electrodes onto 2D organic monolayer and the semiconductor patterning. It opens a new path to reduce the fabrication cost and simplify the manufacturing process of high‐density OFETs for more advanced electronic or biomedical applications.


Introduction
The rapid development of organic field effect transistors (OFETs) has supported new devices in printable and flexible of the highest potential candidates for the next generation of flexible electronics with promising achievements. Previously, Takeya et al. demonstrated OFETs based on wafer-scale fewlayer 3,11-dioctyldinaphtho [2,3-d:2,3-d]benzo [1,2-b:4,5-b]dithiophene (C 8 -DNBDT-NW) single crystals with a contact resistance of 46.9 Ω cm and high-frequency operation above 30 MHz. [23,24] Hu and co-workers have fabricated high-resolution layercontrolled 2D OSC arrays by combining a solution-processed organic semiconductor crystal engineering strategy. The OFETs based on bilayer 2,6-bis(4-hexylphenyl)anthracene (C 6 -DPA) arrays have an average hole mobility of 1.6 cm 2 V −1 s −1 and a yield rate of nearly 100%. [6] Jiang et al. developed the "softtemplate-assisted-assembly method" to prepare centimeterscale monolayer molecular crystal (MMC) arrays with precise regulation over their size and location via a capillary-confinement crystallization process. The field-effect mobility of the array is highly uniform, with a variation of less than 4.4%. [19] To promote the field of 2D OSC growth, Hasegawa et al. introduced a novel concept "geometrical frustration" for the growth of highly stable single molecular bilayers (SMBs), [25] and invented extended meniscus-guided (EMG) coating technique for growing OSC single-crystal films on the highly lyophobic substrate. [26] As a representative derivative of the air-stable dinaphtho[2,3b:2′,3′-f ]thieno [3,2-b]thiophene (DNTT) molecules, 2,9-didecyldinaphtho[2,3-b:2′,3′-f ]thieno [3,2-b]thiophene (C 10 -DNTT) has two alkyl chains to increase its solubility and molecular packing. It is an excellent candidate for solution processable 2D OSC. Previously, our group investigated different processing parameters in the meniscus-guided coating, and the thicknesses, grain boundary density, or crystal orientations of the OSC can be modulated. [27] We also demonstrated monolayer 1L OFETs of the 2,9-dihexylnaphtho [2,3-b]naphtho[2′,3′: 4,5] thieno [2,3-d]thiophene (C 6 -DNTT) could achieve a current density up to 19 µA µm −1 , and a contact resistance as low as 28 Ω⋅cm. Under the high current density operating, thermalinduced degradation has been reported in these 1L OFETs. [28] On the application side, we integrated 2D C 10 -DNTT with hafnium zirconium oxide dielectric to obtain OFETs with subthreshold swing (SS) less than 60 mV dec −1 and inverters with a gain higher than 10 000. These inverters were employed for the high-fidelity electrocardiogram (ECG) sensors, which can help us to identify patients with atrial fibrillation. [17,29] Although the monolayer C 10 -DNTT has shown promising transistor performance, their integration with top contact electrodes and high-resolution OSC patterning remains challenging. Through the cross-sectional transmission electron microscope (TEM), we noticed that the standard thermally deposited top electrodes would cause severe damage to the monolayer OSC. [16] The metal contacts of the reported low contact resistance monolayer C 10 -DNTT OFETs are developed by van der Waals (vdW) gold electrodes. [16,28] To make it suitable for sophisticated flexible circuits or bioelectronics applications, [30,31] pioneer researchers had fabricated device array with multiple electrodes transfer methods. [32,33] More importantly, patterning of OSC over a large area is critical in the practical applications of high-performance OFETs. Patterning of the active layer is essential to avoid device crosstalk, and minimize the leakage current or fringe current, especially under a high device density. [34,35] General lithography like photolithography, the photoresists and UV exposure are usually employed to pattern the active layer with a resolution down to micrometer scale. However, the active layer would have chemical or physical compatibility issues and lead the degradation. [36,37] As organic semiconductors are sensitive to chemicals, orthogonal photoresists have been applied to pattern active layers formed by organic polymers and small molecules. [38][39][40] However, as the upper electrodes of 1L OFETs cannot be deposited by thermal evaporation, the advantages of using photolithography to pattern the devices are heavily restricted. As a result, other approaches like our dry lithography, which can avoid the compatibility problems and maintain high precision on alignment are highly desired to simplify the OFET fabrications and to lower the manufacturing cost.
Herein, we have particularly designed (i) a transfer stamp and (ii) a patterning stamp specifically for the highly crystallized 2D organic monolayer. The electrode transfer stamp consists of polyvinyl alcohol (PVA)/poly(methyl methacrylate) (PMMA)/thermal release tape (TRT), which can precisely transfer prepatterned electrodes onto different target substrates with both global gate and patterned gate. For the OSC patterning, we made use of the transferred electrodes and applied a 2D artificial mica/poly(dimethylsiloxane) (PDMS) stamp to pattern the 1L C 10 -DNTT by direct delamination. The intimate contact between the hydrophilic mica and the C 10 -DNTT can help easily lift off the OSC region which is uncovered by the electrodes; thus, the channel region can be easily developed by this chemical-free dry method. We applied this fabrication technique onto the monolayer C 10 -DNTT on high-k dielectric, the OFETs showed uniform device performances with an average threshold voltage (V TH ) of −0.46, an average subthreshold swing of 95 mV dec −1 and an on-off ratio of nearly 10 8 . The 2 µm channel OFETs operate under the AC-DC rectifier show a high-speed operation with a frequency of up to 17.3 MHz. The proposed electrode transfer and semiconductor patterning approach shed light on the mass production of the next-generation low-power, high-speed, and flexible 2D OFETs over a large area.

The Fabrication Process of the OFET Array
The schematic drawing of the preparation steps of the two transfer stamps is shown in Figure 1. The target substrate for the direct deposition of OSC can be rigid silicon with hafnium oxide (HfO 2 , 20 nm) dielectric deposited by atomic layer deposition or flexible 2 µm parylene with Al gate electrodes and plasma oxidized aluminum oxide (AlO x , 15 nm) dielectric. At the same time, 150 nm Au is deposited on the octyltrichlorosilane (OTS) treated SiO 2 substrate (Figure 1a), followed by spin-coating PVA layer, and the metal transfer stamp was finished by spin-coating another PMMA film on the PVA. After that, thermal release tape (TRT) is used to detach the PMMA/ PVA/Au array from the hosted SiO 2 wafer (Figure 1b,b(I)). Subsequently, the transfer stamp is laminated onto the target monolayer C 10 -DNTT as shown in Figure 1c substrate was heated to release the TRT layer ( Figure 1d). The processing details of the semiconductor growth can be found in Figure S1 in the Supporting Information. Next, the deionized (DI) water at 85 °C was applied to dissolve the PVA layer, and the TRT residue will then be attached to the PMMA and retained on the water surface. A clean surface of OSC with arrays of Au electrodes was obtained (Figure 1e,e(I)).
After the transfer of the electrodes onto the monolayer OSC, the next step would be the dry patterning process. First, we use optical double-sided tape (DST) to peel off the mica sheet from bulk artificial mica and laminate them onto the PDMS (the molecular structure of artificial mica is shown in Figure 1h). After that, the Al array is deposited on mica using the same photolithography mask as the Au electrode array ( Figure 1f(I)). After the PDMS/DST/mica/Al stamp is ready, we align it onto the Au/OSC on the target substrate and apply pressure to ensure direct contact between the hydrophilic mica and the uncovered OSC. The applied pressure is carefully monitored in the homemade translation stage. Since the Au source and drain electrodes are only 5 µm (or below) apart, and the total height of the Al and Au is 200 nm, the mica will not contact the channel region but is suspended as shown in Figure 1f(I). After delaminating the uncovered OSC with the mica/PDMS stamp, the patterning process of the monolayer C 10 -DNTT OFET arrays is completed, and the final structure of the device is shown in Figure 1g. For the OSC stamp patterning technique, previous researchers have demonstrated a perfect technique "push coating", which can produce uniform large-area semiconducting polymer films on the hydrophobic surface. [41] Differently, the mica stamp for OSC patterning happens after the processing of the electrodes, which can avoid the sophisticated alignment steps and maintain high resolution when making down-scaled OFET devices. Moreover, this OSC dry patterning process does not involve any chemical solvent or resist, which makes it a highly potential technique for fabricating OFETs with decent device performance and uniformity.
The mechanism involved in the mica patterning method relies on the competition between the work of adhesion of two interfaces: one is between the mica and C 10 -DNTT and the other between the dielectric layer and C 10 -DNTT. By knowing the surface energy of different layers from the contact-angle measurements, [42][43][44] the work of adhesion between materials 1 and 2, W 1,2 , can be evaluated by where γ is the surface energy, and the superscripts d and p represent dispersion and polar components of the energy, respectively. The values of the dispersion and polar components of these surfaces are obtained based on Fowkes law (Equations (1) and (2), Supporting Information). With deionized (DI) water and Diiodomethane (DM), the contact angles on various surfaces can be measured, and these measurements, along with the surface energies, can be used to arrive at the values of the components of γ 1 and γ 2 .
The contact angle results are illustrated in Figure S3 (Supporting Information), and the evaluations of the surface energy are also discussed in detail in Supporting Information. The work of adhesion between the mica and C 10 -DNTT (W mica, C10-DNTT = 58.3 mJ m −2 ) is higher than the one between the AlO x /C 10 -DNTT or HfO 2 /C 10 -DNTT (W AlOx, C10-DNTT = 55.5 mJ m −2 , W HfO2, C10-DNTT = 55.3 mJ m −2 ), which favors the delamination of the C 10 -DNTT from the dielectric layer. It is worth mentioning that the unaffected region of the C 10 -DNTT is about 5 µm next to the electrode, and it is governed by the total thickness of the Au and Al. If the electrodes are thinner, the mica would be easier to delaminate the OSC near the sharp edge of the metal electrodes. More details about the mica dry lithography process and characterization of different layers can be found in Figure S2 in the Supporting Information.

Figure 2a
shows the schematic image of the OFETs fabricated on glass substrates. The polarized optical microscope (POM) image of OFETs before and after pattern are shown in Figure 2b,c, respectively. The channel length and width of the OFETs are 5 and 300 µm. Figure 2e shows the representative output curves of the OFET. The source-drain current (I DS ) saturates at V DS values close to V G -V TH and no early saturation is detected. Figure 2d shows the transfer curve of the patterned and unpatterned devices at the saturation region (V DS = −3 V), and their threshold voltage (V TH ) and subthreshold swing (SS) are plotted in Figure 2f,g. The transistors have an average threshold voltage (V TH ) of −0.46 V with a variation of 11.6%, and an average subthreshold swing of 95 mV dec −1 with a variation of 7.4%. The monolayer OFETs with the same fabrication process except without the artificial mica stamp patterning are characterized for direct comparison ( Figure S6d, Supporting Information). The on/off ratio of the unpatterned device is only 10 4 , four orders of magnitude lower than the patterned devices as shown in Figure 2d. The leakage current of the unpatterned OFETs shows a significant increase to nearly 10 µA when V G reaches −3 V, six orders higher than the patterned devices, and the output curves cannot passthrough origin ( Figure S6f, Supporting Information). All these noticeable degradations clearly point out the importance of the mica stamp patterning technique.

Contact Resistance Measurements
The width-normalized contact resistance (R C ⋅W) was measured by the transmission line method (TLM) on transistors with channel lengths of 4, 6, 8, 10, and 20 µm as shown in Figure 3a,b (inset in Figure 3a is the schematic image of the cross-sectional view). The POM image of monolayer OFETs with different channel widths is shown in the inset of Figure 3b. The transfer curves of the OFETs with different channel lengths are measured at V DS = −0.01 V, and the R C ⋅W is extracted from the intercept of width-normalized total resistance (R total ⋅W) as a function of L ( Figure 3b). The R C ⋅W value is 201±3 Ω cm at V GS = −3 V (Figure 3c). The width-normalized total resistance is higher than our reported OFET by using a probe for electrode transfer, [21] which can be attributed to the residue of the PVA that goes between the Au and OSC. Figure 3c also shows the intrinsic mobility (µ 0 ) as a function of the gate voltage (V GS − V TH ). The µ 0 remains stable at nearly 10 cm 2 V −1 s −1 when V GS is larger than −1.5 V. Other than the AlO x grown on the glass substrate, we have also performed the same electrode transfer and OSC patterning on another dielectric surface, HfO 2 grown by atomic layer deposition (ALD). The detailed performance of the device can be found in Figure S5 in the Supporting Information.

Flexible OFET Array with 2 µm Parylene as Substrate
After confirming the electrical performance of the OFET array on the rigid substrate, we replaced the substrate by using flexible and biocompatible parylene SR. [45,46] The 2 µm parylene was attached to the sacrificial glass substrate during the fabrication process and detached for the electrical characterization. Figure    device arrays. The POM image of the device array after OSC patterning is shown in Figure 4b, the channel width and length are 5 and 300 µm. The molecular packing mode of the 1L-crystals was studied by the high-resolution AFM (HR-AFM) under the lateral-force mode. Similar to the samples on rigid substrates we examined in Figure S8 (Supporting Information), the long-range ordering of molecules can also be observed (Figure 4c). Herringbone structures were detected in real space periodically, which can be used to estimate three critical inplane lattice parameters, namely a, b, and γ. These values of the 1L-C 10 Figure 4h presents a typical flexible OFET array after peeling off with tweezer. The flexible devices can be conformably transferred onto the head of a LEGO toy (Figure 4i).

Monolayer C 10 -DNTT for Rectifier Application
One of the key motivations for us to develop this semiconductor patterning technique is to simplify the OFET downsizing process and to increase their operating speed for advanced applications such as RFID tags. The high-speed AC-DC rectifier is  paramount in supplying DC voltage to the entire circuit on the tags. [47] Since the rectifying speed must be high enough to respond to the reader, the rectifier requires a high rectifying speed of 13.56 MHz or above. Actually, the high-speed organic rectifiers can be based on vertical organic diodes, in which two kinds of metals with different work functions are fabricated on each side of an organic film have been reported. [48][49][50] This approach has a significant geometrical advantage in obtaining high-speed response; the effective channel approximates the thickness of the organic layers. However, this configuration is also vulnerable to large parasitic capacitance induced by electrode overlap and Joule heating. [51,52] The planar diodeconnected OFETs with patterned gates and reduced electrode overlap (Figure 5a) are also competitive for wireless communication with RF-ID tags. [18,53] This structure can suppress the reverse current of rectifiers because the channel is perfectly in off-state when a large inverse bias is applied. [54] Figure 5a shows OFETs with a channel length of 2 µm and width of 300 µm fabricated on glass substrates, the performance distribution of 16 patterned gate OFETs is shown in Figure S13 in the Supporting Information. The magnified view of one of the 2 µm devices is shown in Figure 5b, which are fabricated for testing of diode-connected rectifiers. The overlap width between the source/drain and gate electrode is 4 µm to suppress the parasitic capacitance. The rectification characteristics of the diodeconnected monolayer OFET were measured using the circuit shown in Figure 5c. The electrical charges that pass through the diode are accumulated in the capacitance, which produces the DC output voltage V OUT . The typical transfer curves of the 2 µm OFET and the OFET-based diode are measured as shown in Figure 5d,e. Figure 5f,g shows the rectifying characteristics at 1 kHz and 25 MHz, when an AC voltage with an amplitude of 4 V is applied. Figure 5h shows the frequency dependence of the V OUT . The maximum rectifying frequency (f rectify ) is defined as the frequency at which V OUT is decreased by a factor of −3 dB. The rectifying frequency is expressed as [18,55] Figure S10 in the Supporting Information. The rectify frequency of 17.3 MHz obtained here is sufficient to support near-field communication of RF-ID tags (13.56 MHz). Compared to previous OFET rectifier works as shown in Figure 5i, our monolayer organic rectifier shows one of the highest reported frequencies under an input voltage of 4 V.

Conclusion
In summary, we demonstrated a feasible large-area electrode transfer and resist-free semiconductor patterning method. With these techniques, we built high-performance OFETs on high-k dielectric layers on different substrates. The mica-assisted patterning technique can eliminate the chemical waste and physical damage on the active layer, which facilitates to the formation of a clean OSC surface and OSC/electrode interface. The monolayer OFETs exhibit a low threshold voltage (V TH ) of less than 0.5 V, a low subthreshold swing (SS) of 95 mV dec −1 , and intrinsic mobility of nearly 10 cm 2 V −1 s −1 at average. These state-of-the-art 2D organic single crystals allow highfrequency operation of a diode-connected monolayer OFET with a channel length of 2 µm, and response at a frequency of 17.3 MHz with an applied AC voltage of 4 V. This frequency can meet the requirements of commonly used frequency in the wireless communication of RF-ID tags. The novel fabrication process opens a new path to make flexible OFET arrays, which is a significant step for the mass production of flexible OFETbased devices.

Experimental Section
Preparation of Dielectrics and Substrates: For the high-κ dielectric, the HfO 2 was grown on p++ silicon (100) wafer by ALD (Cambridge Nanotech Inc.). It was deposited at a temperature of 160 °C and base pressure of 0.3 Pa by using Tetrakis (dimethylamino) hafnium as Hf source. For the growth of AlO x , we first deposited a 20-nm-thick Al gate on the Corning Eagle glass by thermal evaporation (base pressure < 2 × 10 −6 Torr, deposition rate > 30 Å s −1 ), and the thermally evaporated Al layers were patterned by photolithography (AZ2020 and LOR10A are used as photoresists) to form gate electrodes. To enable low-voltage OFET operation, a hybrid gate dielectric is obtained by exposing the aluminum gate electrodes to oxygen plasma (Tailong electronics, 25 sccm oxygen, 10 mTorr, 100 W, 20 min). The parylene was deposited on OTS treated sacrificial substrate (Glass/Si) with a thickness of 2 µm. (Specialty Coating Systems Inc.) Solution Shearing of Monolayer C 10 -DNTT Films: During the solutionshearing process, the substrate and the OTS-(Sigma-Aldrich) treated blade (SiO 2 /Si) were heated up to 63 °C. 40 µL C 10 -DNTT solution (0.2 mg mL −1 in 1,2,3,4-tetrahydronaphthalene, heated to 70 °C to help to dissolve) was injected between the substrate (typical size is 3 cm by 3 cm) and blade (width of 3 cm), where the two had a gap of 100 µm and an angle of 15° in between. A constant shear velocity of 2.3 µm s −1 was controlled by a linear translation stage (ILC 100 CC, New port) for the formation of monolayer crystals. After the deposition, the samples were stored in a vacuum oven (OV-12, Jeio Tech) for at least overnight to remove residual solvent. Before the electrode transfer, the monolayer crystals were heated to 80 °C for 15 min to remove adsorbed moisture and oxygen in glove box (water and oxygen content lower than 1 ppm, MBraun). The deposition of monolayer C 10 -DNTT was carried out in a self-built solution shearing equipment with heaters on both the blade and substrate.
Transfer of Au Electrodes and Alignment: The Au electrodes (150 nm thick) were formed by thermal evaporation on OTS-treated SiO 2 / Si wafers. The rectangular shape of Au stripes with different channel lengths was formed by using parylene as shadow masks; the detailed fabrication process of parylene mask is shown in Figure S7 in the Supporting Information. The resulting Au stripes had a length of ≈300 µm and a width of ≈40 µm. The spin-coated 4 wt% PVA in DI water to laminate the predeposited electrodes on the Si wafer, and 5 wt% PMMA was also spun coated in butyl acetate to hold the TRT residue. The TRT was utilized to detach the Au/PVA/PMMA stack from the Si wafer. After attaching Au electrodes, the testing area of the monolayer crystal was carefully patterned with the techniques shown in Figure 1. The artificial mica bulk was purchased from Taiyuan Fluorophlogopite Mica Company Ltd. After OSC patterning, the completed devices were transferred into the glovebox, heated to 80 °C for 15 min, and stored at room temperature overnight before electrical tests. For the patterned gate device on high-quality glass, the electrode alignment was achieved on the back side of the glass under the transfer stage and microscope.
Preparation of PDMS Stamp and OFET Patterning: A commercially available PDMS sheet (Gel-Pak PF-X4-17 mil.) was positioned on the glass as the stamp base. The mica sheet was mechanically exfoliated from a bulk mica using optical double-sided tape (DST) (Nitto Denko, 32B). 50 nm Al array was directly deposited on mica by thermal evaporation. The mica was used to contact with organic semiconductor (OSC) and detach the OSC from the substrate. The DST was used to stick the mica to the PDMS, and the back side of the PDMS was attached to a glass fixed on the XYZ-manipulation transfer stage. The movement in Z-direction is well controlled to ensure the perfect contact between mica and OSC. After subsequent cooling to room temperature and removal of the load, the separation of the stamp from the film results in removing unwanted regions of the C 10 -DNTT semiconductor.
Characterizations of C 10 -DNTT Film and OTFTs: High-resolution AFM and cross-polarized optical microscopy were used to characterize the and vacuum deposition. References in (i) can be seen in the Supporting Information reference.  monolayer C 10 -DNTT film. For obtaining a high-resolution AFM image, the experiments were conducted on Bruker under the ScanAsyst mode. The channel thickness of the monolayer OFET is characterized by AFM in Figures S11 and S15 (Supporting Information), and analyzed by Nanoscope Analysis 1.5. The Au/C 10 -DNTT/HfO 2 /Si cross-sectional OFET stack was captured by scanning transmission electron microscopy (STEM) in Figure S12 in the Supporting Information. HRAFM results were measured by an Oxford Cypher S AFM under lateral-force mode. Lattice constants were calculated from HRAFM images by Gwyddion. The cross-polarized optical reflection images were performed by the ScanPro spectro-microscope under white light. The XRD analysis of the thin films was obtained using a Rigaku Smart Lab 9 kW with parallel beam input (X-ray Source: Cu Ka; l = 1.54 Å). The out-of-plane result of the C 10 -DNTT film was captured by the 2theta/omega scan mode, and the in-plane result was obtained by the 2theta/chi scan mode. The PL measurement and Raman spectroscopy of the C 10 -DNTT single crystal were characterized by UHTS 300 SMFC VIS.
Electrical Characterization of the OFETs: All measurements were performed in the glovebox environment. To ensure proper electrical contact between the probes and the transferred electrodes, flexible Au wires (15 µm diameter) were attached by conductive Ag paste on the heads of the probes. All electrical measurements were performed in an N 2 -filled glove box. The electrical performance of the OFET arrays was measured with a dual-channel Sourcemeter (Keysight 1500). The threshold voltage (V TH ) and subthreshold swing (SS) are calculated from the forward scan transfer curves. The hysteresis is defined as the V TH difference between the forward and reverse (V G from positive to negative) transfer curves. For the characteristics of diode-connected OFET rectifier, function waveform generators (RIGOL DG4162 and Keysight B1530A Waveform Generator) were used to apply an input AC signal, oscilloscope (Tektronix TDS 2012C) and Keysight 1500 were applied to read the input and output voltages.
Statistical Analysis: The experimental data were present in the form of mean±SD, if applicable. Statistical Analysis was done by OriginPro 2020. For film thickness, surface roughness measurement and HR-AFM lateral force mode, the measurements were carried on 4-5 different positions on at least 3 pieces of samples. For the TLM data fitting, Origin 2020 was used to perform standard least-square linear fittings on the R tot and µ 0 values of the 5 OFETs constructed within one single-crystalline domain of 1L-C 10 -DNTT. For TLM fitting results in Figure 3, the error bars correspond to the standard errors of the R tot and µ 0 values acquired from fitting.

Supporting Information
Supporting Information is available from the Wiley Online Library or from the author.