Junctionless Negative‐Differential‐Resistance Device Using 2D Van‐Der‐Waals Layered Materials for Ternary Parallel Computing

Negative‐differential‐resistance (NDR) devices offer a promising pathway for developing future computing technologies characterized by exceptionally low energy consumption, especially multivalued logic computing. Nevertheless, conventional approaches aimed at attaining the NDR phenomenon involve intricate junction configurations and/or external doping processes in the channel region, impeding the progress of NDR devices to the circuit and system levels. Here, an NDR device is presented that incorporates a channel without junctions. The NDR phenomenon is achieved by introducing a metal‐insulator‐semiconductor capacitor to a portion of the channel area. This approach establishes partial potential barrier and well that effectively restrict the movement of hole and electron carriers within specific voltage ranges. Consequently, this facilitates the implementation of both a ternary inverter and a ternary static‐random‐access‐memory, which are essential components in the development of multivalued logic computing technology.


Introduction
The remarkable increase in data generation in recent times necessitates the development of efficient processing and storage solutions.Up to now, silicon-based CMOS systems have been the primary means of satisfying these requirements. [1]Nevertheless, as the need for faster data processing and greater storage capacity grows, the limitations of CMOS scaling are becoming increasingly apparent in terms of power consumption, computing speed, and device density. [2,3]Furthermore, the binary logic system inherent to CMOS technology restricts the number of logic states achievable per unit device, leading to difficulties in improving device and interconnect density. [4,5][8] However, implementing the MVL system with CMOS transistors is not feasible due to their inherent binary nature, with only "ON" and "OFF" states.Consequently, a simple MVL circuit requires a large number of transistors. [9,10][13] NDR devices come in various forms, including a tunnel diode initially proposed by Esaki [14,15] and a resonant tunneling diode, [16,17] among others. [18,19]In these devices, the NDR region plays a crucial role in enabling the differentiation of three logic states in a ternary logic system: "0," "1," and "2."However, traditional NDR devices necessitate heavily doped semiconductor junctions or complex heterojunction structures that require high-quality interfaces. [20,21]This limitation extends to the increased process complexity, the restricted selection of semiconductor materials, and the formation of undesirable interfacial defects.In light of the challenges faced, researchers have proposed employing heterostructures based on 2D van der Waals (vdW) materials [22][23][24] as a more simplified approach to realizing the NDR phenomenon.This is exemplified by the BP/ReS 2 heterostructure, as suggested by Shim et al. [25] Despite the observation of the NDR phenomenon in the BP/ReS 2 junction, there has been limited progress in advancing research toward the circuit and system level using such vdW heterojunctions.This limitation primarily arises from the scarcity of stable 2D p-type semiconductors, with BP being unstable and highly prone to oxidation. [26,27]dditionally, the technology required for constructing vdW heterostructures is currently underdeveloped and only feasible on a small scale, negatively impacting the reliability and uniformity of heterojunction-based devices. [28,29]ere, we present a novel NDR device that utilizes a junctionless vdW channel, effectively mitigating concerns related to complex junction structures or external doping processes in the channel.Our approach to inducing the NDR phenomenon in a junctionless vdW channel involves the selective suppression of carrier transport between injection and collection electrodes, exclusively in a specific voltage range, which is achieved through the creation of partial potential barrier and well.To implement this strategy, we take the following steps: i) We partially incorporate a metal-insulator-semiconductor (MIS) capacitor beneath a part of the channel region.ii) We integrate the anode electrode with the metal electrode of the MIS capacitor.This integrated electrode results in a heightened hole potential barrier and a deeper electron potential well when applying a positive anode voltage to inject more holes and eject more electrons.This mechanism underlies the NDR effect in our device.We employ Kelvin-probeforce-microscopy (KPFM) analysis to unveil the effective formation of the potential barrier and well, observing that the height and depth increase with the increment in applied voltage.Furthermore, we thoroughly examine our junctionless NDR device concerning both contact and channel conditions.Finally, we theoretically confirm the practicality of our junctionless NDR device toward ternary inverter and ternary static random-access memory (SRAM) circuits.The ternary SRAM circuits are also considered for configuring weight units within a hardware neural network.We evaluate the recognition performance of this ternary hardware neural network and compare it to that achieved by a conventional binary SRAM-based neural network.

Junctionless NDR Device
Figure 1a illustrates the proposed NDR device, which has a junctionless channel structure and includes a partially introduced MIS capacitor beneath the channel layer.This partially formed MIS capacitor is essential to the derivation of the NDR phenomenon.The metal electrode within the MIS capacitor is tied to the anode electrode of the NDR device.When a positive bias is applied to the electrode, a potential barrier is formed for injected carriers in the channel near the MIS capacitor, as depicted in the right panel of Figure 1b.The partial potential barrier near the MIS capacitor can be also modulated by the applied voltage.As a result, the transportation of injected carriers can be suppressed in a specific voltage range, which leads to an abnormal decrease in current, demonstrating the NDR phenomenon.The device is made entirely of 2D van der Waals-layered materials, including WSe 2 and h-BN.We selected WSe 2 with a low pinning factor as the channel layer, making it facilitate to control of the charge injection barrier by choosing various contact metals.This will be discussed in detail in the subsequent sections (refer to Figure 3a-c).To fabricate the device, a metal electrode of the MIS capacitor was formed with a 5 μm width on the SiO 2 /Si substrate, and then h-BN was used as the insulator of the MIS capacitor, and WSe 2 was used as the junctionless channel.The materials were simply stacked onto the metal electrode using a residue-free transfer method that employed adhesion energy engineering. [30,31]Additional details can be found in the Experimental Section; and Figure S1 (Supporting Information).The residue-free transfer method used in the fabrication of the NDR device enables the formation of a residue-free interface between the h-BN and WSe 2 layers, ensuring the operational reliability of the device.After the metal electrode of the MIS capacitor was formed on the SiO 2 /Si substrate and the h-BN and WSe 2 layers were stacked onto it using the residue-free transfer method, anode and cathode electrodes were formed on the WSe 2 channel with a 30 μm distance between them.Here, we confirmed that the MIS capacitor occupies ≈37% (11.2 μm) of the channel region.We further investigated the output characteristics with respect to the lateral size of MIS capacitor, which are provided in Figure S2 (Supporting Information) in detail.Figure 1c shows the optical microscopy and scanning electron microscopy images of the fabricated junctionless NDR device.According to atomic force microscopy (AFM) analysis, the thickness of the h-BN and WSe 2 layers was ≈26.1 nm (40 layers) and 27.8 nm (9 layers), respectively (Figure 1d).In Note S1 (Supporting Information), we have examined how the thickness of each layer affects the character-istics of our NDR device.Cross-sectional transmission electron microscopy (TEM) analysis confirmed the formation of a residuefree interface between the h-BN and WSe 2 layers, as shown in Figure 1e.Additional characterization, including AFM and Raman analyses on the h-BN and WSe 2 layers, is provided in Figure S3 (Supporting Information).
To further study the electrical properties of the junctionless NDR device, we measured its output current-voltage (I-V) characteristics.As illustrated in Figure 1f, the current increases as the applied voltage increases due to the predicted continuous increase in electron injection probability from the cathode electrode to the WSe 2 channel.As the voltage is further increased, an abnormal decrease in current, indicating the NDR phenomenon, is observed.This occurs because, as previously mentioned, the transportation of carriers is expected to be suppressed due to an increase in the height and depth of the partial potential barrier and well for the injected hole and electron carriers as the voltage increases.The peak and valley are defined as the two vertexes in the output voltage-current characteristic curve.As the voltage surpasses the valley point, the current begins to increase again, likely because the carriers overcome the suppression effect by the partial potential barrier and well.The extracted differential resistance values from the device's output characteristics in Figure 1g show an NDR value of up to −131.5 GΩ.The output characteristics of five junctionless NDR devices were measured, and the average values of peak voltage and valley voltage were obtained as 4.35 and 5.96 V, respectively, as shown in the top panel of Figure 1h.Furthermore, the output characteristic of a single junctionless NDR device (device #1) was repeatedly measured, and the NDR phenomenon was observed consistently, as shown in the bottom panel of Figure 1h.This demonstrates the reliability of the junctionless NDR devices.Additionally, a comparison table was prepared (Table 1) to highlight the novel approaches of the proposed junctionless NDR device for deriving the NDR phenomenon.

In-Depth Analysis and Understanding of the Junctionless NDR Device
To gain a thorough understanding of the operational principle of the junctionless NDR device, we conducted a KPFM analysis to confirm the formation of a potential barrier and well near anode, which is the key factor in the occurrence of the NDR phenomenon.Further details can be found in the Experimental Section; and Figure S4 (Supporting Information).As shown in Figure 2a, through the KPFM analysis, we examined the distribution of KPFM potential between the tip and surface of the channel layer of the junctionless NDR device for various biases applied to the tied anode electrodes.When a V anode exceeding 0 V was applied to the anode electrode, energy barrier and well were clearly observed in the junctionless channel layer.As the voltage applied to V anode increased from 0 to 4 V (as seen in Figure 2a,b), the potential barrier height and well depth also increased.The potential barrier height or well depth (Φ barrier or well ) was measured at 1 mV for 0 V, 0.17 V for 1 V, 0.64 V for 2 V, 1.72 V for 3 V, and 2.32 V for 4 V.We also theoretically estimated the height of the potential barrier and the depth of the potential well using the following equation where detailed description on this equation and the estimated height and depth of potential barrier and well are provided in Figure S5 and Table S1 (Supporting Information).Then, using the experimentally and theoretically estimated Φ barrier or well of the junctionless NDR device and other relevant information from the literature [36,37] (as seen in Figure 2c,d,e), we created energy band diagrams to represent the carrier transport in the device with respect to V anode .We divided the operation region of the NDR device into three parts: PDR (positive-differential-resistance) 1, NDR, and PDR 2, based on the observed behavior.In the PDR 1 region, depicted in Figure 2c, the current increases up to 7.61 nA as the V anode gradually increases from 0 V to ≈3.95 V.This is because (1958) [32]   (1960) [ 33]   (1973) [ 13]   (2014) [25]   and [ 34]   (2016 and 2022) [ 29]   (2020) [35]   (2020) This work (2023) the injection of carriers from the electrode to the WSe 2 channel increases.It is noteworthy that the current flowing through the control device without the MIS capacitor (gray-colored curve) is slightly higher than that of the junctionless NDR device (blackcolored curve), indicating that the current flow is partially hindered by the slight formation of the potential barrier and well through the MIS capacitor.As shown in Figure 2d, when the V anode rises further from around 3.95 to around 5.8 V (in the NDR region), the partial barrier height and well depth increase as illustrated in the energy band diagram.Despite the continuous injection of carriers, the partial potential barrier and well significantly impede the transportation of carriers, leading to an abnormal decrease in current from 7.61 nA at a V anode of 3.95 V to 6.31 nA at a V anode of 5.8 V.As the V anode applied to the tied anode electrode increases beyond 5.8 V (PDR2 region shown in Figure 2e), the height of the partial potential barrier and the depth of the partial potential well continue to increase.Concurrently, the Schottky barrier's height near the cathode reduces.Thus, due to an increased injection of electron carriers from the cathode to WSe 2 , it is anticipated that the increased electrons will surpass the deepened partial potential well, leading to an increase in the current.We additionally investigated the transfer characteristics of junctionless NDR device as depicted in Figure 2f-h.We conducted a sweep of the gate voltage (V gate ) from 0 to 15 V, gradually increasing anode voltage from 1 to 10 V. We observed that as the V anode increased to 4 V (Figure 2f), the current values increased in the entire gate bias region.This is due to the increased injection probability of electrons from the cathode to the WSe 2 channel as the V anode increases.Then, we further increased V anode from 5 to 7 V (Figure 2g).For the operating region below V gate of ≈5 V, we observed that the current increased as V anode increased.This can be attributed to the fact that even though the height of the energy barrier and well increases with V gate , it may not be sufficiently high for the injected electrons and holes to be able to transport across the barrier and well.On the other hand, for the operating region above V gate of 5 V, we observed that the current decreased as V anode increased.In this region, the height of energy barrier and well is significantly formed due to high V gate , leading to a decreased probability of both electron and hole transport across the barrier and well.We also observed that the above-mentioned effect was more clearly expressed in the high V gate region (>7 V) when and V anode of 8 V or more was applied (Figure 2h).This analysis of transfer characteristics confirms that the energy barrier and well formed by V gate significantly affects that transport of hole and electrons, suggesting that the energy barrier and well can play a crucial role in the manifestation of the NDR phenomenon.

Characterization of NDR Phenomenon with Respect to Contact and Channel Conditions
Our research delved deeper into the carrier transport in NDR devices, as influenced by diverse conditions in the contact and channel regions.Initially, we examined the effect of substituting Ti with Pt as the contact metal and compared the outcomes between two types of devices, while keeping the properties of the WSe 2 channel consistent.Figure 3a presents that the Pt-contacted device has a monotonically increasing output characteristic without any indication of the NDR phenomenon and a greater current density than the Ti-contacted NDR device.The difference in their output characteristic curves is attributed to the contrasting barrier heights, which are determined by the specific contact metal.To gain a better understanding of these findings, we extracted the barrier heights for holes on the WSe 2 NDR devices with Pt and Ti contacts.The extracted values were 0.25 eV for Pt and 0.53 eV for Ti, as shown in Figure 3b.Considering that the bandgap of bulk WSe 2 is around 1.2 eV, both devices have lower barriers for holes than for electrons.Based on this, we can assume that hole carriers play a more significant role in the overall current flow.Figure 3c illustrates the energy band diagram that describes the transport of carriers in both Pt-contacted and Ti-contacted devices.The Pt-contacted device has a lower barrier height, resulting in a stronger electric field toward the anode and cathode in the equilibrium state.Consequently, when the same anode voltage is applied to both devices, there is a higher energy hump for holes near the anode in the Pt-contacted device.Despite this, the high number of holes injected due to the low hole barrier height allows for the overwhelming flow of holes over the energy hump.This results in a monotonically increasing output characteristic in the Pt-contacted device.Conversely, even though the Ti-contacted device has a lower energy hump for holes, the lower injection of holes provides a small number of holes, and consequently, makes an obstruction in the transportation of carriers by the energy hump to be apparent, inducing the NDR phenomenon.Scaling down the MVL device is feasible through the utilization of advanced lithography technologies.However, beyond mere scaling down, the aforementioned crucial factors must be considered to ensure that the device operates effectively.
After scaling down, it is essential to prevent an excessive injection of carriers from the cathode, while simultaneously maintaining a sufficient potential barrier/well near the anode to suppress carrier transport effectively.Taking these considerations, an appropriate length between the anode and cathode can be estimated.Afterward, we examined the effect of the global back-gate voltage on the conductance of the channel.Figure 3d's top panel illustrates a diagram of the NDR device with a global back gate.The lower panel displays the output characteristic, which demonstrates that when a positive back-gate bias is applied, the NDR characteristic curve exhibits lower current density and smaller peak voltages compared to the original NDR device.Moreover, as the back gate voltage gradually increases from 1.5 to 1.8 V, the NDR peak shifts toward the left and upward.We extracted the values for peak voltage and peak current density from the NDR curves and presented them in Figure 3e.The peak voltage decreases from 0.97, 0.89, 0.74, to 0.65 V as the back-gate bias increases, while the peak current and differential resistance increases from 8.04, 13.1, 19.1, to 24.4 pA.To gain a comprehensive understanding of the acquired outcomes, we primarily examined the modulation of channel potential.This modulation ultimately impacts the alteration in carrier injection probability and the relative height of the energy hump.The band diagram portrayed in Figure 3f illustrates that the application of a positive back gate bias increases barrier height for holes, consequently leading to a decrease in hole injection.Since holes are the primary carriers in the NDR device, the overall current density of the back-gated device is lower compared to that of the NDR device.Despite the significant reduction in the number of holes, the back-gated device still exhibits the NDR phenomenon, which can be attributed to the transportation of electrons.Specifically, the increase in injected electrons at higher back-gate voltage causes the NDR region to appear at lower-voltage and higher-current regions.

Junctionless NDR Device-Based Ternary Logic Circuits and Its Application
Finally, we studied the potential application of the junctionless NDR device toward multivalued logic computing technology.This exploration unfolded as follows: Initially, depicted in Figure 4a, we conceptualized and fabricated a ternary inverter (see also Figures S6 and S7, Supporting Information), a core building component in multivalued logic systems.This ternary inverter comprised two elements: first, the junctionless NDR unit serving as the driver unit, and second, the p-type transistor unit operating as the load unit.A supply voltage (V dd ) was applied to the source electrode of the load unit, while the cathode electrode of the NDR driver unit was grounded (V ss ).The input voltage (V in ) was introduced through the local bottom gate electrode of the load unit, and the resultant output voltage (V out ) was obtained at the anode electrode of the NDR driver unit, which also functioned as the drain electrode of the load unit.A comprehensive electrical characterization of the fabricated load unit is presented in Figure S4 (Supporting Information).Subsequently, we conducted SPICE circuit simulations using experimentally calibrated compact models, as explained below.In the inset graph of Figure 4b, the DC operating point of the ternary inverter is determined through load line analysis.In this analysis, the load unit functions as a pull-up network, working to raise V out to V dd , while the NDR driver unit acts as a pull-down resistor, aiming to lower V out to V ss .The operational characteristics of the ternary inverter can be divided into three distinct regions, denoted as operating regions PDR1, NDR, and PDR2, based on the output voltage (V out ).In region PDR1, the load unit is deactivated (V in = V dd ), and the NDR driver unit takes control, driving the output down to V ss .In the remaining regions, the load unit is active and endeavors to elevate the output voltage to V dd .However, its influence is constrained by the NDR driver unit.In region NDR, the load unit is activated to a limited extent (V in = V dd /2), and the NDR driver unit operates in a specific state denoted as PDR1 in the graph.In this configuration, the load unit succeeds in pulling the output voltage to V dd /2.This analysis illuminates the ternary inverter's behavior under varying voltage conditions (regions PDR1, NDR, and PDR2) dictated by the input voltage (V in ).It shows how the interplay between the load unit and NDR driver unit manages the output voltage (V out ) throughout these operational regions.In region PDR2, the p-type transistor is strongly turned on (V in = V ss ) so that the state of the NDR driver unit is in PDR2 region and the load unit pulls the output to V dd .Based on the load line analysis, as shown in black-colored line of Figure 4b, we obtained three distinct logical states from voltage transfer characteristic.In addition, as provided in Figures S6 and S7 (Supporting Information), we fabricated the ternary inverter circuit and demonstrated its operation.Then, as depicted in the inset circuit schematic and represented by the gray-colored dotted line in Figure 4b, we investigated the potential use of our NDR device toward a ternary SRAM circuit.This involved the interconnection of two ternary inverters and the incorporation of two access transistors, where MoS 2 channel-based n-type transistors were used as access transistors (Figure S4, Supporting Information).We achieved a static noise margin (SNM) of 9.2% of V dd , which ensures the writability and read stability of the ternary SRAM.In Table S2 (Supporting Information), we compared our work with existing ternary logic technologies, in terms of device size, power consumption, delay, and noise margin.We also verified the transient behaviors of both the ternary inverter and SRAM circuits, as depicted in Figure 4c (for ternary inverter) and Figure 4d (for ternary SRAM), respectively.We confirmed the existence of three different output logic states (specifically, '0′ at 0.95 V, '1′ at 5.09 V, and '2′ at 9.83 V) in the transient behavior of the ternary inverter when input voltages of 10, 5, and 0 V were applied, respectively.
Subsequently, we validated the write operation of the ternary SRAM by conducting a transient analysis of the SRAM, as illustrated in Figure 4d.When the voltage on the word line (WL) is set to V dd of 10 V, it activates the access transistors, allowing the ternary SRAM nodes Q and QB (depicted in Figure 4b) to be pro-grammed by driving the desired values onto the trit line (TL) and trit line bar (TLB), respectively.By setting TL and TLB to either V dd of 10 V or V ss of 0 V (for TL) and V ss or V dd (for TLB), we force nodes Q and QB into logic states '2′ or '0′ (for node Q, with voltage levels of 9.07 or 0.52 V) and '0′ or '2′ (for node QB, with voltage levels of 0.52 or 9.07 V), respectively.When both TL and TLB set to V dd /2, the nodes Q and QB are induced to logic state '1′ (5.04 V).When the WL set to V ss , the access transistors deactivate, deriving the ternary SRAM to standby mode.These logic states of ternary SRAM serve as the weight values for hardware neural networks.Following the weight writing process, the initial step in the reading operation entails precharging both the TL and its complement, TLB, to a voltage of V dd /2.Subsequently, to retrieve the stored weight, the word line (WL) is activated.In this case, WL set to V dd /2 instead of V dd to prevent any inadvertent flipping of the stored weight.Additionally, we conducted the multiplyaccumulation (MAC) operation using ternary SRAM weights, as illustrated in Figure 4e.The MAC operation in networks utilizing ternary SRAMs is carried out by constraining the duration of the read operation.This constraint ensures that the value being read from TL or TLB does not fully transition to Q or QB but instead undergoes a change of only ΔV.Consequently, the retrieved value of TL or TLB corresponds to V dd -ΔV at each ternary SRAM.In the scenario where n SRAMs share the same TL and TLB lines, and m SRAMs are specifically chosen (with WL set to V dd /2), the voltage value detected at TL becomes V dd -Σ m ΔV.This is exemplified in Figure 4e, where we successfully confirmed the MAC operation within an array of 5 integrated SRAMs.When varying the selection of m SRAMs from 1 to 5, the measured voltage at TL and TLB is found to be V dd -Σ m ΔV, ranging from 9.27 V (m = 1) to 7.17 V (m = 5) for TL, and from 9.30 V (m = 1) to 7.25 V (m = 5) for TLB, respectively.Next, we explored the applicability of the junctionless NDR device-based ternary SRAM for a ternary parallel computing technology (Figure 4f,g).As depicted in inset of Figure 4f, ternary SRAMs are incorporated as the weight units in the hardware neural network, where the three logical states (V ternary ) of each SRAM was used for deriving values of weight unit (W SRAM ).Following this ternary weight strategy, we set up a hardware neural network comprised of ternary SRAM and conducted both training and inference tasks using the MNIST dataset, as indicated by the wine-colored learning curve in Figure 4f.Furthermore, we built a neural network utilizing conventional binary SRAMs (see Figure S8 for details, Supporting Information) and conducted a comparative analysis against the network employing ternary SRAMs (the indigo-colored learning curve in Figure 4f).This comparison unveiled that the neural network utilizing ternary SRAMs achieved a superior pattern recognition rate, specifically reaching 92.5% under the ternary condition, compared to 89.5% under the binary condition.It is a widely acknowledged fact that as the number of weight states increases, the learning accuracy tends to rise as well.We carried out weight visualization at the 5000th epoch, as depicted in Figure 4g, which is correlated with the recognition rates.As provided in Table S2 (Supporting Information), we compared our ternary SRAM and other nonvolatile memory devices in aspects of application for parallel computing.In addition, as provided in Table S4 (Supporting Information), we carried out benchmarking of performance metrics, including validation accuracy, TOPS/W, and leakage power, to compare our ternary logic technology with existing binary technologies.In this process, we employed the NeuroSim + simulator, incorporating our ternary logic technology into the simulator, and assessed performance utilizing the VGG-8 network architecture alongside the CIFET-10 dataset. [38,39]

Conclusion
In this research, we implemented a NDR device that incorporates a junctionless WSe 2 channel structure.The approach we used to generate the NDR effect in the junctionless channel structure, without resorting to doping process, involved the inhibition of carrier transportation through the creation of partially formed potential barrier and well within the channel layer.To create this partial potential barrier and well, we introduced a MIS capacitor par-tially into the channel layer, subsequently connecting the anode electrode of the device to the metal electrode of the MIS capacitor.When a voltage is applied to the linked anode electrode, the potential barrier and well act to impede the movement of injected hole and electron carriers, thus resulting in the occurrence of the NDR phenomenon under specific bias conditions.We demonstrated that the formation of the partial barrier and well occurs within the channel layer.We also confirmed that as the applied voltage increases, the height of the barrier and the depth of the well also increase, as determined through KPFM analysis.Additionally, we found that the height of the injection barrier is another crucial factor in producing the NDR phenomenon.Specifically, at the WSe 2 -metal junction, it was confirmed that the injection barrier needs to be designed in a way that prevents excessive injection of either electron or hole carriers.This precaution is essential because if carriers are injected excessively, they can overwhelm the potential barrier and well, preventing the occurrence of the NDR phenomenon.Furthermore, we investigated the NDR phenomenon in relation to the conductance of the channel layer, which can be adjusted by applying a global back gate bias (V bg ).We confirmed that an increase in the electron conductance of the channel leads to a decrease in the peak voltage and an increase in the peak current.Finally, we demonstrated the practicality of our junctionless NDR device for multivalued logic computing technology.Through circuit simulations, we established that our device could achieve three distinct logical states: logic '0′ at 0.95 V, logic '1′ at 5.09 V, and logic '2′ at 9.83 V, in a ternary inverter configuration based on our device.Furthermore, by interconnecting two ternary inverters, we constructed a ternary SRAM circuit, which exhibited a SNM of 9.2% and demonstrated reliable write and MAC operations.Subsequently, we designed a hardware neural network using ternary SRAMs as the weight units and achieved a recognition rate of 92.5%.In comparison, a binary SRAM-based neural network showed a recognition rate of 89.5%.These findings are expected to make valuable contributions to the advancement and maturation of ternary logic circuits and the broader field of multivalued logic computing technology.

Experimental Section
Fabrication of Junctionless NDR Devices: For fabricating junctionless NDR device, at first, metal electrode of MIS capacitor with a 10 μm was patterned on the 90 nm thick SiO 2 /heavily doped Si substrate using an optical lithography process, followed by the deposition 5 nm thick Ti and 15 nm thick Au using an electron-beam evaporator.h-BN as insulator of MIS capacitor and junctionless WSe 2 channel layer were mechanically and sequentially transferred onto this metal electrode of MIS capacitor via a residue-free transfer method based on adhesion energy engineering (see also Figure S1, Supporting Information).Using optical lithography process, anode and cathode electrodes with a width of 10 μm were patterned on junctionless WSe 2 channel layer, followed by the deposition of 10 nm thick Ti or Pt and 80 nm thick Au using an electron-beam evaporator.Finally, the outside of the anode and cathode metal regions was removed by a lift-off process.
Fabrication of Junctionless NDR Device-Based Ternary Inverter Circuit: For fabricating ternary inverter circuits, similar with fabricating of NDR device, metal electrode of MIS capacitor, and gate electrode of WSe 2 ptype load transistor was patterned on the 90 nm thick SiO 2 /heavily doped Si substrate using an electron-beam lithography process, followed by the deposition 5 nm thick Ti and 15 nm thick Au using an electron-beam evaporator.h-BNs as insulator of MIS capacitor and gate dielectric of load transistor were mechanically transferred onto those metal electrodes via a residue-free transfer method based on adhesion energy engineering, followed by etching h-BN layers via electron-beam lithography and CF 4 plasma treatment processes to define specific region.Then, WSe 2 channel layer was mechanically transferred onto the h-BN layers using the identical transfer method.The specific regions in the WSe 2 layers were also defined using the same method.Using electron-beam lithography process, anode, cathode, and output electrode of ternary inverter were patterned on WSe 2 channel layer.Finally, 10 nm thick Ti and 80 nm thick Au was deposited using an electron-beam evaporator, and the outside of the defined metal regions was removed by a lift-off process.
Characterization of Junctionless NDR Device: Optical microscopy images of the junctionless NDR device were obtained using an upright metallurgical microscope (Olympus BX53M).The layered atomic structures of WSe 2 /h-BN were investigated using high-resolution transmission electron microscopy (HR-TEM, JEM-ARM200F, JEOL) at an accelerating voltage of 200 kV.Raman analyses were performed using a WITec micro-Raman spectrometer system with a frequency-doubled neodymiumdoped yttrium aluminum garnet (Nd-YAG) laser beam (532 nm layer excitation).Scanning probe microscopy measurements were performed in the noncontact AFM and KPFM modes using an NX10 system (Park Systems Corp.).AFM and KPFM measurements were performed under dark and ambient conditions using a platinum/iridium (Pt/Ir)coated Si tip.Electrical measurements of the junctionless NDR device were conducted using a Keysight B2912A source-measurement unit (SMU).To determine the Schottky barrier height between Ti or Pt anode/cathode electrode and WSe 2 , a thermionic emission current equation for a Ti-WSe 2 -Ti or Pt-WSe 2 -Pt junction was used as follows where I 0 is the saturation current, A is the effective area, A ** is the Richardson constant, T is the temperature in Kelvin, q is the elementary charge, Φ B is the Schottky barrier height, k B is the Boltzmann constant, V DS is the voltage across the source and drain, and n is the ideality factor.When a reverse bias was applied, the exp( qV DS nk B T ) term was ignorable and the above equation was consequently simplified as follows Moving the T 2 term to the left-hand side of the equation and taking the natural log on both sides, the following equation was obtained ln Schottky barrier heights were extracted by plotting ln( T 2 ) as a function of q k B T and finding the slope of the line.Pattern Recognition Task of Binary and Ternary SRAM-Based Neural Networks: The process involved applying voltage signals (V n ) to each pixel of the images in the MNIST dataset as inputs to the input neuron layer.Subsequently, the SRAM-based weights (W SRAM ) were summed up at the output neurons in the hidden layer using a multiply-accumulate (MAC) operation.This resulted in the generation of output signals (O m = ∑ k n = 1 W SRAM ) at the output neurons in the hidden layer.The output signals were then transformed into input voltages for the output layer, and this entire sequence of operations was repeated iteratively.This iterative process allowed to compute the currents at the output neurons in the output layer.Next, the output value (f m ) was compared, obtained by applying the sigmoid activation function (f(I m ) = 1 1+e −O m ), with each label value (k m ).The delta value ( m ) was calculated, which represents the difference between the output values and the label values for input patterns ( m = k m − f m ).Depending on whether  is greater than zero (potentiation phase) or less than zero (depression phase), the SRAM-based weights (W SRAM ) were adjusted.In the potentiation phase, W SRAM increased, while in the depression phase, it decreased.The number of weights adjusted was determined by the number of logical states in binary and ternary SRAM circuits.This pattern recognition process was implemented using MATLAB.

Figure 1 .
Figure 1.Junctionless NDR device.a,b) Schematic illustration of junctionless NDR device a) and illustration for describing operation principle of the NDR device b).c) Optical microscopy and scanning electron microscopy images of fabricated junctionless NDR device, where scale bars denote 30 (left panel) and 10 (right panel) μm, respectively.d) Thickness profile of WSe 2 and h-BN layers used in junctionless NDR device.e) X-TEM image of WSe 2 /h-BN heterostructure showing a residue-free interface between WSe 2 and h-BN layers.f) Output current-voltage characteristic curve of junctionless NDR device showing NDR phenomenon.g) Differential resistance with respect to the applied voltage.Inset graph shows differential resistance profile of conventional WSe 2 device.h) Peak and valley voltage values extracted from multiple junctionless NDR devices (top panel) and from multiple output characteristics of single junctionless NDR devices (bottom panel).

Figure 2 .
Figure 2. In-depth analysis and understanding of the junctionless NDR device.a) Surface potential distribution verified on the overall channel region when V anode increased 0-4 V. Inset image shows KPFM mapping image with the applied bias and scale bar indicated as 4 V and 5 μm, respectively.b) Extracted height and depth of partial potential barrier and well with respect to the applied bias.c-e) Energy-band diagrams of junctionless NDR device (top panel) and corresponding current-voltage output characteristics (bottom panel) at different voltage regions: i) 0 V < V anode < 3.95 V (PDR1 region), ii) 3.95 V < V anode < 5.8 V (NDR region), and iii) V anode > 5.8 V (PDR2 region).f-h) Transfer characteristics of junctionless NDR device when V anode increases from 1 to 4 V, from 5 to 7 V, and from 8 to 10 V.

Figure 3 .
Figure 3. Characterization of NDR phenomenon with respect to contact and channel conditions.a) Output current-voltage characteristic curves of Pt-contacted (black-colored curve) and Ti-contacted (wine-colored curve) devices.Inset graphs show the extracted differential resistance values, which denotes NDR phenomenon occurred on Ti-contacted NDR device.b) Modified Richardson plots of Pt-contacted (black-colored) and Ti-contacted (winecolored) devices.c) Energy band diagram describing carrier transportation of devices with low (top panel) and high (bottom panel) hole barriers.Inset graphs show the extracted differential resistance values, which denotes NDR phenomenon occurred on Ti-contacted NDR device.d) Schematic of junctionless NDR device with global back gate (top panel), output current-voltage characteristic curves with respect to global back gate bias (bottom left panel), and extracted differential resistance at V bg = 1.8 V (bottom right panel).e) Peak voltage, peak current, and negative-differential-resistance values extracted from the output current-voltage characteristic curves.f) Energy band diagram of junctionless NDR device showing the effect of increasing V bg .

Figure 4 .
Figure 4. Junctionless NDR device-based ternary logic circuits and its application.a) Chematic of ternary inverter composed of junctionless NDR unit as a driver and p-type transistor unit as a load (left panel).Circuit diagram of a ternary inverter (right panel).b) VTC of a ternary inverter, denoting three logical states: 0, 1, and 2. The gray dotted line configures a butterfly curve with the VTC curve.Inset graph and circuit diagram show the load-line analysis of a ternary inverter under various V in conditions (from 0 to 10 V) and ternary SRAM circuits, where two ternary inverters are cross-coupled and two access transistors are integrated, respectively.c-e) Timing diagrams of a ternary inverter c), a write operation of ternary SRAM d), and MAC operation of ternary SRAM e), respectively.f) Learning curves for MNIST handwritten digit patterns of hardware neural network composed of binary (indigo-colored curve and plots) and ternary (wine-colored curve and plots) SRAMs, wherein inset schematic denotes neural network composed of ternary SRAMs.g) Weight mapping images at the 5000th training epoch when SRAM-based weights in hardware neural network are based on binary (left panel; indigo-colored map) and ternary (right panel; wine-colored map) states.

Table 1 .
Comparison of NDR device in terms of structure and mechanism for deriving NDR phenomenon.
Esaki Holonyak et al.Tsu et al.Nourbakhsh et al.Shim and Seo et al.Jung et al.Kudrynskyi et al. Lee et al. [This work]