High‐κ Dielectric (HfO2)/2D Semiconductor (HfSe2) Gate Stack for Low‐Power Steep‐Switching Computing Devices

Herein, a high‐quality gate stack (native HfO2 formed on 2D HfSe2) fabricated via plasma oxidation is reported, realizing an atomically sharp interface with a suppressed interface trap density (Dit ≈ 5 × 1010 cm−2 eV−1). The chemically converted HfO2 exhibits dielectric constant, κ ≈ 23, resulting in low gate leakage current (≈10−3 A cm−2) at equivalent oxide thickness ≈0.5 nm. Density functional calculations indicate that the atomistic mechanism for achieving a high‐quality interface is the possibility of O atoms replacing the Se atoms of the interfacial HfSe2 layer without a substitution energy barrier, allowing layer‐by‐layer oxidation to proceed. The field‐effect‐transistor‐fabricated HfO2/HfSe2 gate stack demonstrates an almost ideal subthreshold slope (SS) of ≈61 mV dec−1 (over four orders of IDS) at room temperature (300 K), along with a high Ion/Ioff ratio of ≈108 and a small hysteresis of ≈10 mV. Furthermore, by utilizing a device architecture with separately controlled HfO2/HfSe2 gate stack and channel structures, an impact ionization field‐effect transistor is fabricated that exhibits n‐type steep‐switching characteristics with a SS value of 3.43 mV dec−1 at room temperature, overcoming the Boltzmann limit. These results provide a significant step toward the realization of post‐Si semiconducting devices for future energy‐efficient data‐centric computing electronics.


Introduction
Since the development of field-effect transistors (FET), the gate-dielectric/semiconductor gate stack structure has served as the fundamental building block responsible for controlling the overall current flow along the conductive channel surface for efficient information processing and computing applications.However, as the geometric scaling of the Si complementary metal-oxide-semiconductor continues, the gate stack loses its controllability, leading to an overall decline in the electronic performance.[3] However, one of the key challenges in realizing 2D semiconductors for future computing devices is the integration of optimized dielectrics with high-quality gate stacks.The efficacy of FETs is heavily affected not only by the material's intrinsic properties but also by the quality of the dielectric/channel interface and dielectric characteristics. [4]Especially, the high- dielectric integration on 2D semiconductor is of utmost importance as it allows for greater scalability of the device by achieving a thin equivalent oxide thickness (EOT) and improves gate controllability, which is essential for future energy-efficient data-centric computing electronics.
In recent years, significant efforts have been made to develop 2D-vdW-semiconductor-based gate-dielectric stacks.These advances can be categorized by the formation methods, such as direct deposition, transfer, and native oxide formation.The most commonly used approach for forming gate dielectric stacks is atomic layer deposition (ALD), which involves the direct deposition of a dielectric over a channel.However, unlike conventional Si technology, ALD usually results in nonuniform nucleation and island formation on 2D semiconductors, leading to a porous dielectric layer that is prone to current leakage, particularly when the EOT is low. [5,6]The introduction of a buffer layer, such as perylene tetracarboxylic dianhydride, has been suggested to overcome these issues. [7]However, achieving an effective EOT scaling in the presence of a buffer layer remains a significant challenge.The wafer-scale epitaxial growth of CaF 2 using molecular beam epitaxy (MBE) has been reported. [8]The high crystalline quality and pinhole-free layer with a moderate dielectric constant ( ≈ 8.4), along with enabling the MBE growth of various 2D semiconductors on CaF 2 , make it possible to apply flexible heteroepitaxial structures in various fields.However, there are still significant challenges to overcome, particularly in the manufacturable fabrication of top-gated FET with MBE and the suppression of the interface trap density between the dielectric and channel layers.[11] However, owing to its relatively low dielectric constant ( ≈ 3.7) and insufficient bandgap (≈6 eV), h-BN is not desirable for low-power electronics.Recently, a high- single crystalline layered dielectric, Bi 2 SeO 5 ( ≈ 16.5) with a breakdown field of ≈10 MV cm −1 , was reported on a Bi 2 O 2 Se channel. [12]owever, the transfer method was used to integrate the dielectric, which fundamentally cannot ensure a high-quality interface between the channel and the dielectric because unavoidable defects can be introduced during the fabrication process.To mitigate the deleterious effect of defectivity on device performance, several annealing techniques, including rapid thermal annealing, have been used; [13,14] however, the remaining high density dangling bonds still act as a major bottleneck and adversely affect device performance.More recently, several proposals have been made to overcome the poor interface quality of transfer methods using fully oxidized dielectrics (ZrO 2 [15] and HfO 2 ) [16] converted from 2D semiconductor materials (ZrS 2 and HfS 2 ) via oxidation.Luo et al. fabricated a high-quality interface by transferring HfS 2 onto MoS 2 followed by ozone-treated oxidation to form HfO x . [17]he physisorption interface derived from the enlarged vdW gap between HfO x /MoS 2 during ozone treatment guaranteed a highquality interface, showing a low subthreshold slope (SS) value (≈63.1 mV dec −1 ) and low hysteresis (≈10 mV).Nevertheless, achieving satisfactory EOT scaling seems difficult because of the inevitably present 0.53 nm vdW gap, which is unacceptable for technology requirements. [18]Despite these efforts, the primary challenge of the transfer method is its lack of scalability for waferscale integrated chip manufacturing, which remains a major impediment to its widespread adoption in the semiconductor industry.
Native oxide formation, a method of chemically converting a 2D vdW semiconductor channel into a dielectric layer, is a potential solution for overcoming the limitations of the aforementioned methods.Historical success of Si semiconductor technology for the past decades has been partly attributed to the SiO 2 formation on the Si channel surface, even in the current high- dielectric adaptation.Thus, the potential of high- dielectrics that are inherent to 2D vdW semiconductors must be investigated.In recent years, several studies have been conducted on native oxides utilizing HfSe 2 , [19] ZrSe 2 , [20] TaS 2 , [21] and HfS 2 [22] via various oxidation methods, such as ambient, thermal, and plasma treatments, which have provided valuable insights into interfacial engineering.However, the reported native oxides exhibited poor dielectric properties, which limit their application as passivation layers.Moreover, distinct defect bands originating from nonstoichiometric amorphous structures that limit the overall device performance remain a challenge. [23]Recently, a single-crystalline 2D dielectric/semiconductor structure (epitaxial high- single crystalline Bi 2 SeO 5 /Bi 2 O 2 Se) was reported, demonstrating low gate leakage current and high field effect mobility, and scaled EOT of less than 0.5 nm. [24]Moreover, wafer-scale epitaxy of vertically standing 2D fin-oxide heterostructure arrays has high potential for application in future 3D architecture designs. [25]However, the interface quality of the Bi 2 SeO 5 /Bi 2 O 2 Se gate stack was not confirmed, and it exhibited poor SS characteristics.Moreover, the large leakage current and narrow bandgap of Bi 2 SeO 5 (≈3.9 eV) are likely to lead to the relatively small I on /I off ratio, thereby limiting the future scaling potential of this specific material system.
In this paper, we report on a native HfO 2 /HfSe 2 gate stack with a high-quality interface fabricated via layer-by-layer plasma oxidation.The interface quality between native HfO 2 and HfSe 2 was investigated by measuring the interface trap density, D it ≈ 5 × 10 10 cm −2 eV −1 through multifrequency capacitance-voltage (C-V) analysis method.A theoretical study using density functional theory (DFT) explains the formation of a high-quality interface.During the oxidation of HfSe 2 at the interface, the Se atoms stood on top of the Hf atoms of the 2D layer, sustaining the planar structure.The chemically converted HfO 2 exhibited a high dielectric constant, ≈23, which enabled a low gate leakage current (≈10 −3 A cm −2 ) at a scaled EOT of ≈0.5 nm.Fabricated HfO 2 /HfSe 2 -based FET demonstrated almost ideal SS ≈ 61 mV dec −1 (over 4 orders of I DS ) at room temperature (300 K) owing to the low D it value, along with high I on /I off ratio ≈10 8 and small hysteresis ≈ 10 mV.Furthermore, we fabricated HfO 2 /HfSe 2 -based impact-ionization FET (I 2 -FET) with a separately controlled channel structure, [26,27] demonstrating the steep-switching characteristics of SS ≈ 3.43 mV dec −1 at room temperature, overcoming the Boltzmann limit.Our results provide a promising approach for the development of low-power devices with high-quality gate stacks for future post-silicon semiconductor devices.

HfO 2 /HfSe 2 Gate Stack Formed via Layer-by-Layer Plasma Oxidation
To achieve a high-quality high- dielectric/2D-semiconductor gate stack, O 2 plasma oxidation was conducted on multilayer HfSe 2 films.Figure 1a shows a schematic illustration of the HfO 2 /HfSe 2 gate stack formation and the device structures studied in this work.Detailed plasma oxidation process conditions can be found in the Experimental Section and Figure S1 (Supporting Information).During the plasma oxidation process, the top surface of HfSe 2 is oxidized by the chemical conversion of Se to O, and further diffusion of O atoms into HfSe 2 enables the conversion of unconverted HfSe 2 into HfO 2 layer formation on the unconverted HfSe 2 (see the "DFT Calculation" subsection in the Experimental Section below).Thus, the thicknesses of the HfO 2 layers were controlled by adjusting the plasma oxidation time.For instance, by increasing the process time starting with the 25 nm HfSe 2 film, the converted HfO 2 layer thickness was increased and finally fully oxidized after 5 min (Figure S2a,c, Supporting Information).The overall oxidation rate was estimated to be ≈2.1 nm min −1 (Figure S2d, Supporting Information).The right panel of Figure 1b shows a cross-sectional transmission electron microscope (TEM) image of the HfO 2 /HfSe 2 heterostructure after 5 min of plasma oxidation with 40 nm HfSe 2 (see Figure S4 in the Supporting Information for related data including atomic force microscope, electron energy loss spectroscopy, and selected area electron diffraction patterns of HfO 2 /HfSe 2 heterostructure).No noticeable defects were observed at the interface.Especially, the atomically sharp interface between HfO 2 and HfSe 2 (Figure 1d) suggests that HfO 2 formation is limited to the top of the unconverted HfSe 2 , which is consistent with the DFT calculation results presented below that reveal the layer-by-layer oxidation of HfSe 2 .Similar results were consistently obtained from three additional samples fabricated with the same process (Figure S5, Supporting Information).The fast Fourier transform patterns (left panel of Figure 1b) exhibited amorphous/crystallized structures of HfO 2 /HfSe 2 layers, respectively.The unconverted HfSe 2 interplane distance of (001) was estimated to be ≈0.614nm, which is consistent with the reported value [28] and retains the original crystalline structure, as confirmed by the Raman spectrum in Figure S2b (Supporting Information).The energy dispersive spectrometer (EDS) mapping shows the elemental distributions of Hf, O, and Se in the corresponding area (Figure 1c).Xray photoelectron spectroscopy (XPS) measurements of the converted HfO 2 and unconverted HfSe 2 (Figure 1e) were conducted.The observed Hf 4f peak at 16.01 eV and the O 1s peak at 532.4 eV are in good agreement with a typical HfO 2 film. [29,30]n addition, XPS depth profiling characterizations (see detailed experimental results and analyses in Figure S6 in the Supporting Information) also suggest that the thickness of the HfO 2 layer can be controlled by the adjusting plasma process time following the extracted oxidation rate (Figure S2d, Supporting Information).

Mechanistic Study of the Layer-by-Layer Oxidation of HfSe 2
The mechanism of HfSe 2 oxidation in the formation of a highquality HfO 2 /HfSe 2 interface was investigated using DFT calculations for an interface model made of a slab of monoclinic HfO 2 crystals in contact with a HfSe 2 monolayer (see Figure S9 in the Supporting Information).The HfO 2 slab was modeled as a three-Hf-layer monoclinic HfO 2 crystal with an O-terminated (001) surface, which represents the dominant surface during HfO 2 growth. [31]For the construction of an interface model, a (4 × 2) supercell of the HfO 2 slab was scaled to match the (3 × 3) supercell of HfSe 2 .Oxygen vacancy (V O ) defects within the HfO 2 layer are expected to form a channel that will allow the supply (extraction) of O (Se) atoms into (out of) the deep HfO 2 /HfSe 2 inter-face region, [32][33][34] and introducing one V O in each oxygen layer of our HfO 2 supercell model (composed of 16 O atoms) results in a Hf:O atomic ratio of 1:1.88, which is close to the experimental estimation (see Figures S7 and S8 in the Supporting Information).Because we are mainly interested in the oxidation of HfSe 2 , we incorporated only one V O at the interfacial HfO 2 layer.Additional computational details are presented in Figure S9 (Supporting Information).Remarkably, when an O atom was placed on the HfSe 2 surface, we found that it replaces the Se atom without a substitution energy barrier and forms covalent bonds with three neighboring Hf atoms.The extracted Se atom was then drawn to the V O site of the HfO 2 surface, as shown in Figure 2a (see also Figure S10a in the Supporting Information).It should be emphasized that this phenomenon is unique to the HfSe 2 case, and, e.g., in the HfS 2 counterpart, [22] the S atom is perturbed by the penetrating O atom but is not completely detached and remains bonded to the incoming O and two Hf atoms (see Figure S11a in the Supporting Information).These different trends are in line with the binding energy of O 2 (g) to a Se atom (4.02 eV), which is much smaller than that between O 2 and a S atom (6.34 eV).When additional O atoms are inserted at the interface, the substitution of a Se atom by an O atom can be repeated as shown in Figure 2b (see also Figure S10b in the Supporting Information).We expect that this O insertion/Se extraction at the HfSe 2 surface will proceed simultaneously as long as the O concentration is low, as shown in Figure 2c left schematic and Figure 2d (see also Figure S12a in the Supporting Information).Before diffusing through the V O channel in HfO 2 , the extracted Se atoms are expected to remain mobile at the interface between HfO 2 and the partly oxidized HfSe 2 layer and prevent the merging of the two surfaces, promoting the layer-by-layer oxidation.By contrast, we found that such layer-by-layer oxidation cannot proceed when the O concentration is high to the level that enforces O atoms should be deposited on the fully oxidized HfSe 2 surface (where each Hf atom is already triply bridged to O atoms).39][40][41][42] of the HfO 2 surface (Figure 2c, right schematic and Figure 2e); see also Figure S13 (Supporting Information), locally leading to the breakdown of the layer-by-layer oxidation.

Interface Quality of HfO 2 /HfSe 2 Structure
The interface quality between the chemically converted HfO 2 and HfSe 2 was investigated by measuring a HfO 2 /HfSe 2 -based MOS capacitor (MOSCAP), which was fabricated with the Au (30 nm)/HfO 2 (10 nm)/HfSe 2 (15 nm) structure (inset in Figure 3a).The measured C-V curves of the fabricated MOSCAP are shown in Figure 3a.The behavior of the accumulated capacitance with increasing gate voltage indicates that HfSe 2 is an n-type semiconductor.The negligible frequency dispersion (1 kHz-1 MHz) in both the depletion and accumulation regions suggests the presence of a low level of traps.The conduction method [35,36] was used to evaluate the interface trap density (D it ), which critically determined the device performance of the HfO 2 /HfSe 2 gate stack.D it was calculated, based on the angular frequency (w = 2f) normalized parallel conductance (Figure 3b) using the following equation where (G p /) peak is the maximum value of the normalized conductance peak, q is the elementary charge, and A is the area of MOSCAP.An extremely low interface trap density D it ≈ 5 × 10 10 cm −2 eV −1 was obtained from three devices fabricated with the same process, as shown in Figure 3c.Dielectric constant () of the HfO 2 in this MOSCAP was estimated by C = A 0 /d, where C is the measured capacitance,  0 is the vacuum permittivity,  is the relative permittivity (i.e., dielectric constant ), A is the area of the capacitor, and d is the thickness of the HfO 2 .Κ remains at 23 in all frequency ranges (Figure 3d), indicating that the chemically converted HfO 2 is a stable high- dielectric for low-power and high-frequency electronics (see Figure S18c in the Supporting Information for thickness-independent high-).The EOT was extracted to be 1.6 nm from this  value.][39][40][41][42] The lower D it level at the scaled EOT of our device can be attributed to the superior interface quality of the HfO 2 /HfSe 2 structure formed by the chemical conversion process without passivation or the introduction of impurities at the interface.This was achieved under low/moderate plasma power conditions (Figure S23, Supporting Information), and it was found that a high power could induce larger impurities and uneven interfaces.This is consistent with the DFT results showing that the precondition for achieving clean surfaces through layer-by-layer oxidation is a low local O density (Figure 2).The HfO 2 thicknessdependent leakage current and dielectric breakdown characteristics are shown in Figure S18a,b (Supporting Information)).The breakdown field (E BD ) of the converted HfO 2 was in the range of 6-10 MV cm −1 .

HfO 2 /HfSe 2 MOSFET and Electrical Characteristics
Figure 4a shows a schematic of the top-gated Metal-Oxide-Semiconductor Field-Effect-Transistor (MOSFET) fabricated using the HfO 2 /HfSe 2 structure with 10 nm converted HfO 2 (EOT = 1.6 nm).The channel length and width are 10 and 3 μm, respectively.The detailed fabrication process is shown in Figure S1 (Supporting Information).The output (I DS -V DS ) characteristics and optical microscope (OM) images are shown in Figure S15 (Supporting Information).As shown in Figure 4b, the HfO 2 /HfSe 2 MOSFET demonstrates an almost ideal SS of 61 mV dev −1 (over four orders of I DS ) at room temperature (300 K), which is close to the Boltzmann limit.Similar results were obtained for the other 12 devices fabricated using the same fabrication process (Figure S16, Supporting Information), confirming the reproducibility of our devices.A high I on /I off ratio of ≈10 8 was also achieved from the HfO 2 /HfSe 2 MOSFET, with low gate leakage current of ≈10 −6 A cm −2 .Similar results (atomic interface structure and I DS -V GS transfer characteristic with a SS 4order of 63 mV dec −1 ) were obtained for the thinner HfSe 2 channel (3 nm), as shown in Figure S17 (Supporting Information).Such excellent device performance can be mainly attributed to the excellent interface quality of the HfO 2 /HfSe 2 structure, that is, the native oxide (HfO 2 ) formed seamlessly on the 2D semiconductor (HfSe 2 ) without introducing defect sites.As shown in Figure 4c, a small hysteresis (10 mV) is observed during the reversible +/− gate voltage sweep with sweeping rates of 0.025-0.1 V s −1 , indicating suppressed trap sites.43][44][45][46][47] Table S1 (Supporting Information) summarizes the detailed comparison of the reported high- dielectric/2D semiconductor gate stacks with those in this study.As indicated with the dotted guideline for low-power application requirement, [18] our HfO 2 /HfSe 2 structure demonstrated suppressed gate leakage current over the scaled EOT range of 0.5-2.6 nm. Figure 4d shows the temperature-dependent transfer characteristics.The corresponding SS values at various temperatures of the fabricated MOSFET are shown in Figure 4e.
The measured SS values are nearly ideal for all temperatures, with a linear relationship between SS and temperature, which is determined by SS = (k B T/q)ln10(1 + q 2 D it /C ox ), where q is the electronic charge, k B is the Boltzmann constant, T is the temperature in Kelvin, C ox is the oxide capacitance, and D it = 5 × 10 10 cm −2 eV −1 .Future semiconductor switching devices will require fast and steep switching, low power consumption, and high-speed carrier transport.In Figure 4f, these crucial requirements are compared for recently reported 2D-semiconduting devices integrated with various HfO 2 /gate dielectrics in terms of SS, I on /I off ratio, and carrier mobility. [7,13,16,22,40,42]The proposed HfO 2 /HfSe 2 structure demonstrated a lower SS, higher I on /I off ratio than previously reported results and improved carrier mobility.We investigated the variations in SS and gate leakage current characteristics with different EOT and D it values through device simulations (see Table S2 and Figures S21 and S22 in the Supporting Information).In addition, we examined the current and capacitance characteristics of the ultraclean interface device (see Table S3 in the Supporting Information for the resistivecapacitive (RC) component).Figure 4h illustrates the intrinsic RC delay characteristics with respect to D it and V DD , where the off current was fixed at 10 pA, which is suitable for low-power applications.A significant increase in circuit delay is expected within the reported range of D it .Notably, the D it improvement achieved in this study, particularly when V DD was reduced to 0.5 V for lowpower applications, enables circuit delay improvements ranging from a minimum of 10% to several hundred percent.
[59][60][61] We fabricated HfO 2 /HfSe 2 -based I 2 -FET with a separately controlled channel structure, as shown in Figure 5a.A top-gate electrode was partially formed above the HfO 2 so that the HfSe 2 channel was divided into a gated-region (L gated ) controlled by the gate electrode and a short ungated-region (L ungated ≈110 nm) that was not covered by the gate dielectric (see Figure S24 in the Supporting Information for OM/scanning electron micro-scope (SEM) image of the device).The gated-region is a conducting region that determines the on-state carrier transport, and the ungated-region is a steep-switching region where the transition from the off-to on-state via impact ionization takes place.Impact ionization occurs when band bending within the ungated-region exceeds its critical electric field (E CR ), as shown in the band diagram in the lower panel of Figure 5a.At a low gate voltage, the entire channel functions as an effective channel, allowing typical carrier transport with an applied drain bias.However, when the  [27,59,62,63] h) Results of V BR , V TH , and on/off ratio as a function of ungated-region length.The results suggest that ultralow power applications are possible with sufficient scaling.
gate voltage is increased, a chemical potential () is induced in the gated-region, resulting in more concentrated band bending and carrier multiplication via impact ionization in the ungatedregion.This phenomenon leads to an abrupt increase in the channel current, ultimately achieving steep-switching characteristics.As can be seen in Figure 5b, we achieved a steep-switching transfer characteristic (SS = 3.43 mV dec −1 ) at room temperature (300 K). Figure 5d illustrates the impact ionization rate and generated electron-hole density in the ungated-region of the I 2 -FET, as observed through device simulation (see Figure S29 in the Supporting Information for the device simulator setup).The peak impact ionization rate was found near the drain end, with the carrier density of the minority carrier, holes, surpassing that of the majority carrier, electrons.Depending on the electric-field profile within the I 2 -FET, the generated holes move toward the drain, resulting in a significant increase in the current and turning on the device.Figure 5c shows the channel current as a function of the drain bias (V DS ) at a fixed threshold gate voltage (V GS ).Further scaling of the operating biases is intermutually associated with device parameters such as the ungated-region length and gate-dielectric thickness.Figure 5e shows V BR (the required V DS at which impact ionization occurred) as a function of both the HfO 2 thickness and the ungated-region length.The corelated overall conditions for V GS and V DS to obtain a steep switching in the I 2 -FET can be understood in the form of a contour plot (Figure 5f).Detailed relevant electrical characteristics and explanations can be found in the Figures S26-S28 (Supporting Information).Figure 5g shows the injection efficiency, which is the ratio of the gate leakage current to the drain current (I GS /I DS ), of the HfO 2 /HfSe 2 I 2 -FET and compares it with the results from various reported I 2 -FETs.Hot-carrier-induced device degradation can be suppressed by minimizing the efficiency of injecting carriers into the dielectric layer as opposed to allowing them to flow along the channel.The proposed HfO 2 /HfSe 2 I 2 -FET demonstrated a lower injection efficiency than n-impact-ionization MOSFET (IMOS) and p-IMOS devices with a Si channel [27,62] and a recently reported 2D-material-based I 2 -FET, [59,63] which can be attributed to the improved interface quality between the HfSe 2 channel and its native oxide (HfO 2 ) gate dielectric.Figure 5h shows the results obtained through device simulation, showing that a further reduction in the ungated-region length enables additional decreases in V BR and V TH (Figure S30, Supporting Information).As the ungated length was scaled down, the impact ionization efficiency continued to increase.At L ungated = 50 nm, sufficient impact ionization occurs even at a low voltage (V BR = 0.47 V).This, in turn, leads to a decrease in the supply voltage while maintaining a high on/off ratio, resulting in improved power consumption and device reliability.

Conclusion
We report the experimental realization of a high-quality metaloxide-semiconductor structure through the conversion of HfSe 2 into HfO 2 via controllable plasma oxidation.The atomistic mechanism for achieving a high-quality interface was clarified through a theoretical study using density functional theory.The fabricated HfO 2 /HfSe 2 gate stack exhibited atomically sharp high-quality interface with suppressed D it ≈ 5 × 10 10 cm −2 eV −1 measured by multifrequency C-V analysis.Theoretical studies explained that the clean HfO/HfSe 2 interface was achieved through the layer-bylayer oxidation enabled by the barrierless substitution of Se with O.The FETs fabricated with the HfO 2 /HfSe 2 gate stack demonstrated an almost ideal SS of ≈61 mV dec −1 (over four orders of I DS ) at room temperature (300 K), an I on /I off ratio of ≈10 8 , and a small hysteresis of ≈10 mV.Moreover, the HfO 2 /HfSe 2 -based I 2 -FET with the separately controlled channel structure demonstrated steep-switching characteristics of SS ≈ 3.43 mV dec −1 at room temperature, overcoming the Boltzmann limit.We believe that our results provide a promising approach for developing low-power devices with high-quality interfaces for future energyefficient computing devices.

Experimental Section
Fabrication of the HfO 2 /HfSe 2 Gate Stack: Exfoliation and transfer processes were carried out in a controlled environment of a glove box to prevent external perturbations (where both O 2 and H 2 O concentrations were below 0.1 ppm).The thickness of the material was first identified using an optical microscope and then accurately determined using an atomic force microscope.O 2 plasma oxidation was performed under fixed conditions (a power of 10 W, flow rate of 5 sccm, and pressure of 470 mTorr) for HfO 2 formation as a high- gate dielectric.The double-electron resistor layers were spin-coated with polymethyl methacrylate at 2000 rpm for 5 s and 4000 rpm for 35 s.Each layer was baked at 180 °C for 2 min on a hot plate.Electron-beam lithography and electron-beam deposition were used to form source/drain and top-gate electrodes with Au in a high-vacuum chamber (5 × 10 −7 Torr).
Fabrication of MOS Capacitor: Mechanically exfoliated multilayer HfSe 2 flakes from a bulk crystal were dry-transferred onto a 10 nm bottom ground electrode using polydimethylsiloxane. O 2 plasma oxidation was then performed for 5 min to produce a 10 nm HfO 2 layer on top of the HfSe 2 channel.Then, a 30 nm Au electrode was deposited on the HfO 2 /HfSe 2 heterostructure as the top electrode.
Fabrication of MOSFET/I 2 -FET: Multilayer HfSe 2 flakes were exfoliated using Scotch tape and dry-transferred onto 10 nm bottom source/drain electrodes.The O 2 plasma time (MOSFET: 5 min, I 2 FET: 4 min) was used to produce 10 and 8.4 nm HfO 2 layers, respectively.A 50 nm Au layer was deposited on the HfO 2 /HfSe 2 heterostructure as the top gate electrode.The difference was that in the FET, a full cover top gatedregion was formed on the HfO 2 /HfSe 2 heterostructure, but an ungatedregion (≈110 nm) not covered by the top gate was formed on the I 2 -FET.
Characterization: OM (Olympus, BX51M) and field emission scanning electron microscpoe (JEOL, JSM7500F) were used to observe the sizes and colors of the prepared samples and fabricated devices.Raman spectroscopy at an excitation wavelength of 523 nm was used to characterize the converted HfO 2 /HfSe 2 heterostructure.The thickness of the flakes was determined using an atomic force microscope (Park Systems Corp., NX-10) in the noncontact mode with PPP-NCHR probe tips (nanosensors).The electrical properties of HfO 2 /HfSe 2 -based electronics (MOSCAP, MOSFET, and I 2 -FET) were measured using a Keithley 4200 parameter.
Device Simulation: Device analysis was performed using Synopsys Sentaurus (Synopsys Inc., Mountain View, CA, USA), a 3D technology computer-aided design software package.To develop the channel material HfSe 2 , the DFT simulation results were used to determine its energyband characteristics, and the permittivity properties were determined by referencing the measured results. [64,65]The electrical transport was analyzed through a drift-diffusion model, and the mobility model included a high-field saturation model, thin layer model, and an Enormal model that considered the interfacial surface roughness scattering.Furthermore, to describe the tunneling behavior at the HfO 2 /HfSe 2 interface, a nonlocal tunneling model was employed that encompassed both inelastic phononassisted and elastic processes as well as tunneling effects due to traps.To describe the impact ionization phenomena and gate oxide leakage current, the University of Bologna model was used among the avalanche and nonlocal tunneling models, respectively.
DFT Calculation: DFT calculations were performed using the vienna Ab initio simulation package with the projected augmented wave method. [66]Many-electron exchange-correlation interactions were treated within the Perdew-Burke-Ernzerhof form of generalized gradient approximation. [67]To correctly incorporate the weak long-range dispersion interactions, Grimme's DFT-D3 method was applied. [68]The kinetic energy cutoff for the plane wave basis was set at 400 eV, and the 2 × 4 × 1 Monkhorst-Pack k-point samplings were used in the structural relaxation for interface slab structures.The atomic structures were optimized until the total energy and the Hellmann-Feynman forces on each atom reached the 10 −4 eV and 0.01 eV Å −1 levels, respectively.

Figure 1 .
Figure 1.Formation and structure of the HfO 2 /HfSe 2 gate stack: a) schematic of high-quality gate stack fabrication process using O 2 plasma oxidation.b) Fast fourier transform patterns (left panel) and scanning transmission electron microscopy (STEM) image (right panel) of the HfO 2 /HfSe 2 heterostructure.c) EDS mapping showing elemental distribution of HfO 2 /HfSe 2 .d) High resolution STEM image exhibiting atomically sharp interface.e) X-ray photoelectron spectroscopy (XPS) analysis of converted HfO 2 (upper panel) and HfSe 2 (lower panel).

Figure 2 .
Figure 2. Oxidation mechanism of HfSe 2 at the interface of HfO 2 /HfSe 2 : the optimized structures are shown for the cases when a) one and b) three O atoms are inserted near the oxygen vacancy (V O ) site.c) As shown in the left panel of scheme, each O atom replaces a Se atom, which is then displaced onto the top of Hf atom.The arrow in (b) denotes that during the substitution reaction, Se atoms accumulated at the interface will diffuse to V O sites and then will be extracted to the outside through the V O channel.To examine the oxygen concentration effect, we considered the case with seven O atoms.These O atoms then substituted seven Se atoms [scheme (c) left panel], which were subsequently removed assuming that the Se atoms have been extracted to the outside.d) For the low O density condition modeled by inserting two O atoms out of the oxidized region, the substitution reaction proceeds as shown in ①. e) For the high concentration condition modeled by two O atoms placed within the oxidized region, however, we observe that the HfSe 2 layer is pulled to the HfO 2 surface, resulting in the merged HfO 2 /HfSe 2 interface as shown in ②.This situation is schematically depicted in the right panel of (c) (color scheme: Hf, gray; Se, green; O, red).

Figure 5 .
Figure 5. Impact ionization transistor (I 2 -FET) based on the HfO 2 /HfSe 2 structures: a) schematic of a HfO 2 /HfSe 2 -based I 2 -FET and its energy-band profile with applied V GS > 0 and V DS < 0. b) I DS -V GS characteristics at room temperature and a magnified view of the subthreshold region.The on/off current ratio exceeds 10 8 and the SS is 3.43 mV dec −1 .c) I DS -V DS characteristic exhibiting abrupt current rise over V BR of −1 V. d) A diagram illustrating the impact ionization phenomenon in the ungated-region of the I 2 -FET.A sufficient number of (e-h) pairs are generated due to significant impact ionization.e) 3D plot of V BR values of this I 2 -FET device, which exhibits further scaling by simply reducing either the native oxide thickness or the ungated-region length.f) Contour plot representing the channel current (I DS ) as a function of various V DS and V GS .Steep-switching behavior is observed along the yellow dashed line, indicating V BR .g) Calculated gate injection efficiency for various I 2 -FETs with different EOTs compared with conventional IMOS.[27,59,62,63] h) Results of V BR , V TH , and on/off ratio as a function of ungated-region length.The results suggest that ultralow power applications are possible with sufficient scaling.