N‐Type Single Walled Carbon Nanotube Thin Film Transistors Using Green Tri‐Layer Polymer Dielectric

The proliferation of disposable, wearable, and implantable printable electronics requires the development of high‐performance biodegradable, and sustainable electronic components. Often green materials don't have the necessary properties for high‐performance electronics, therefore obtaining the ideal properties requires a combination of multiple green materials. A tri‐layer dielectric is reported using poly(lactic acid) (PLA), poly(vinyl alcohol)/cellulose nanocrystals (PVAc), and toluene diisocyanate terminated poly(caprolactone) (TPCL), which is integrated into semiconducting single‐walled carbon nanotube (sc‐SWCNT) based thin film transistors (TFTs) in a top gate bottom contact architecture. The PVA provides a high dielectric constant due to the hydroxy groups, the cellulose is used to optimize the viscosity, the TPCL layer provides a robust hydrophobic surface, and the PLA eliminates the interfacial charge traps present in the PVAc and improves the adhesion between PVAc and the substrate. This leads to a decrease in leakage currents and reduces the polarity at the dielectric/semiconductor interface. The TFTs fabricated using tri‐layer dielectrics led to air‐stable n‐type devices with higher overall performance when compared against the PVAc/TPCL bilayer devices.


N-Type Single Walled Carbon Nanotube Thin Film Transistors Using Green Tri-Layer Polymer Dielectric
Mathieu N. Tousignant represent a compromise in performance. Thin film transistors (TFTs) are three electrode logic gate operators including a semiconductive layer with a dielectric layer and are a common example of electronic devices used in flexible electronic and sensing applications. [2][3][4][5] The desired properties of these TFTs are low voltage operation, low leakage currents, and high on-state currents. [6][7][8] Single-walled carbon nanotubes (SWCNTs) are promising semiconductors achieving high mobilities in low-voltage flexible, printed TFTs. [9][10][11][12] High-performance TFTs are obtained through achieving good SWCNT density as well as a selection of dielectrics with high dielectric constants (k) increasing the capacitance density and ultimately the performance of the TFTs. [13] For example, poly(vinyl alcohol) (PVA) is a common environmentally friendly high-k dielectric. [14][15][16] However, often high-k materials are plagued with increased leakage currents and charge trapping at the semiconductor/dielectric interface. [16] When used in the fabrication of SWCNT TFTs, PVA can prevent saturation of the output curves, increase leakage currents and create a polar environment at the SWCNT/PVA interface reducing device performance. [17,18] To circumvent this challenge the dielectric layer can be modified by adding a thin low-k dielectric material on top of the high-k dielectric creating a bilayer dielectric. Low-k dielectric materials are better for the deposition of the semiconducting material and reduce the polarity at the dielectric/semiconductor interface leading to higher operating currents and mobilities. [15,[17][18][19][20][21][22][23][24] Furthermore this bilayer approach can also be used to change the hydrophobicity of the surface, similar to the use of octyl trichlorosilane (OTS), leading to reduced wettability of the solvent and resulting in a better SWCNT network density. [12,25] Studies have also shown that the addition of a third low-k layer can be used to sandwich the high-k dielectric material further improving device performance by reducing leakage currents between the source and the gate. [20,26,27] Within this study, we report the use of an environmentally friendly tri-layer dielectric composed of low-k poly(lactic acid) (PLA) bottom layer, high-k PVA/cellulose nanocrystal blend (PVAc) and low-k toluene diisocyanate terminated polycaprolactone (TPCL) top layer. PLA is a biodegradable polymer that has been used with other green dielectric bilayer systems while PVAc/ TPCL blends have been used as biodegradable solarizing films in The proliferation of disposable, wearable, and implantable printable electronics requires the development of high-performance biodegradable, and sustainable electronic components. Often green materials don't have the necessary properties for high-performance electronics, therefore obtaining the ideal properties requires a combination of multiple green materials. A tri-layer dielectric is reported using poly(lactic acid) (PLA), poly(vinyl alcohol)/cellulose nanocrystals (PVAc), and toluene diisocyanate terminated poly(caprolactone) (TPCL), which is integrated into semiconducting singlewalled carbon nanotube (sc-SWCNT) based thin film transistors (TFTs) in a top gate bottom contact architecture. The PVA provides a high dielectric constant due to the hydroxy groups, the cellulose is used to optimize the viscosity, the TPCL layer provides a robust hydrophobic surface, and the PLA eliminates the interfacial charge traps present in the PVAc and improves the adhesion between PVAc and the substrate. This leads to a decrease in leakage currents and reduces the polarity at the dielectric/semiconductor interface. The TFTs fabricated using tri-layer dielectrics led to air-stable n-type devices with higher overall performance when compared against the PVAc/TPCL bilayer devices.
agricultural applications which makes them ideal environmentally friendly dielectric materials. [24,28,29] This tri-layer dielectric was used with semiconducting enriched (sc)-SWCNTs in a top gate bottom contact (TGBC) architecture to fabricate n-type TFTs that functioned under ambient conditions. Depositing PLA on top of the semiconducting enriched (sc)-SWCNTs encapsulates them reducing leakage currents and forming a better surface for the deposition of PVAc. The top layer is a low-k TPCL layer that prevents moisture from impacting the performance of the PVAc layer and helps enable air-stable operation.

Preparation of Dielectric and sc-SWCNTs
PLA was dissolved in chloroform at a concentration of 2 mg/ ml. Once fully dissolved the PLA was filtered into another vial using a 0.45 µm PTFE filter. PVA was dissolved in water, filtered with a 0.45 µm cellulose filter, and mixed with a 2 wt.% suspension of cellulose nanocrystals (CNCs) to form a PVA/CNC suspension (PVAc). The PVAc suspensions were fabricated based on previously reported procedures producing a suspension at a concentration of 80 mg ml −1 with 0.75 wt.% CNCs. [30] TPCL was synthesized following previously reported procedures. [18] The TPCL was dissolved in anhydrous toluene at 2 mg ml −1 and heated to 60 °C for 1 h before being filtered through a 0.45 µm PTFE filter into a new vial. The filtered TPCL solution was stored in a nitrogen environment and small volumes of the stock solution were removed for spin coating under ambient conditions. SWCNTs were purchased from Raymor Nanointegris (D = 1.5 nm). The SWCNTs were selectively wrapped with a polyco-alt-carbazole (PCPF) polymer and dispersed in toluene following a previously reported procedure to create semiconducting enriched single-walled carbon nanotube dispersion (sc-SWCNTs). [31] The concentration of the sc-SWCNTs was adjusted so that the 957 nm peak had an absorbance of 2.0 a.u via UV-Vis spectroscopy.

Thin Film Characterization
Both the dispersive (γ d ) and the polar component (γ p ) of the surface energies were calculated using a system of two equations where a curve fitting was used to measure contact angles from images of the drops. These equations have the same form as shown in Equation 1 and are solved simultaneously with the contact angles of diidomethane and distilled water. [32] 1 cos 2 2  [32][33][34] A Bruker dimension Icon was used to perform atomic force microscopy images with ScanAsyst tips while using the ScanAsyst mode. The images were flattened and cleaned up using the Bruker Nanoscope software.

Metal-Insulator-Metal Capacitor Fabrication and Characterization
Metal-insulator-metal (MIM) capacitors were fabricated using 1 in 2 glass substrates that were purchased from University Wafers. The glass substrates were cleaned using a 4-step cleaning procedure where the substrates were sonicated for 5 minutes while immersed in detergent, distilled water, acetone, and methanol sequentially. Next, the substrates were dried using a stream of nitrogen. Both a 5 nm layer of chromium (0.5 Å s −1 ) and a 50 nm layer of gold (1 A s −1 ) were then deposited onto the substrates using a shadow mask and physical vapor deposition (PVD). The PVD system was built by Angstrom Engineering. The PLA for the tri-layer capacitors and PVA for the bilayer devices was then deposited onto the patterned substrates through spin coating. The PLA solution was statically dispensed onto the substrate and spun at 2000 RPM for 90s under ambient conditions. Next, the PVAc dispersion was dynamically spun on top of the PLA layer at 2000 RPM for 90s under ambient conditions. For the bilayer dielectrics the PVAc suspension was spun dynamically onto the patterned substrate at 2000 RPM for 90s. Both the substrate/PLA/PVAc and substrate/PVAc films were then annealed under vacuum at 150 °C for 1 h to remove any excess moisture within the PVAc. Next, the TPCL layer was statically dispensed on top of the PVAc layer for both the bi and tri-layer devices. The TPCL layer was spun at 2000 RPM for 90s and annealed under vacuum at 200 °C for 15 minutes to crosslink the TPCL with the PVAc film. The top electrode (Au, 50 nm, 1 Å s −1 ) was then deposited above the TPCL films using a shadow mask and PVD. This yielded 10 individual MIM capacitors per substrates with areas from 0.35 to 2.88 mm 2 .
The dielectric properties of the fabricated MIM capacitors were then characterized using impedance spectroscopy. A Methrohm PGSTAT204 was used to perform potentiostatic impedance measurements with a 10 mV amplitude within the range of 10 −1 -10 5 Hz. The dielectric constant (κ) as well as www.advmatinterfaces.de the capacitance densities (c i ) in relation to frequency was then calculated using the potentiostatic measurements and the following equations.
In the above equations, t represents the dielectric thickness, ω the angular frequency, A is the surface area, ε 0 is the permittivity of vacuum, Z″ is the imaginary portion of the impedance, and Z′ is the real portion of the impedance.

TFT Fabrication and Characterization
Thin film transistors (TFTs) were fabricated on 15 × 20 mm quartz-coated glass substrates purchased from Ossila. The substrates were cleaned using a 4-step cleaning procedure where the substrates were immersed in detergent, distilled water, acetone, and methanol. For each step, the substrates are sonicated for 5 min and then dried under a stream of nitrogen. Next, the bottom source-drain electrodes (Cr 5 nm 0.5 Å s −1 , Au 50 nm, 1 Å s −1 ) were deposited onto the substrates through a shadow mask by PVD. The patterned substrates were rinsed with distilled water and isopropyl alcohol, dried under nitrogen, and plasma treated for 15 min. The substrates were then submerged in a 1% solution of toluene and OTS at 70 °C overnight. Once the OTS reaction was completed the substrates were rinsed with toluene, dried with nitrogen, and annealed under vacuum at 100 °C for 1 h. With the OTS surface treatment complete the sc-SWCNTs were deposited onto the surface using a Musashi SHOT mini 200Sx (dispenser: Nano Master SMP-III) drop-casting machine. 0.2 µL drops were deposited between the source-drain electrodes. The substrates were then rinsed at a 45° angle 4 times with 1 ml of toluene and dried under nitrogen to remove any excess unbound polymer. Following the sc-SWCNT deposition the bi and tri-layer dielectrics were deposited through spin coating techniques using the same procedure as the MIM fabrication section. Finally, the gate electrode (Au, 50 nm, 1 Å s −1 ) was deposited on top of the TPCL dielectric through a shadow mask using PVD. This yielded 20 TFTs per substrates (W = 1000 µm and L = 30 µm).
The fabricated TFTs were then tested on a custom testing station built by Element Instrumentation inc. and Kreus Design (oesProbe A10000-P290) using a Keithley 2614B and a custom Labview software. All the output and transfer characteristics of the fabricated TFTs were tested under ambient conditions and their transfer characteristics were measured in the linear regime. The following equations were used for the calculation of threshold voltage (V T ) and transconductance (g m ) V GS and V SD are the gate-source and the source-drain voltages, C i is the capacitance density, L is the channel length, and W is the channel width.

Statistical Analysis
The capacitance density is averaged over 20 functioning capacitors per conditions and the standard deviation is shown as a semi-transparent line around the average for both bi and tri-layer devices. The TFT properties are characterized over 30-40 functioning TFTs per condition. The TFTs are measured 3 times and each time the mobility, transconductance, threshold voltage, and on/off current ratios are collected or calculated for each run. The average values are shown with their standard deviation. The transfer and output curves are representative curves of a thin film transistor with performance close to the average for both the bi and tri-layer devices.

Thin Film Characterization
PVA is a promising dielectric due to its polar hydroxyl groups and low environmental impact, [1] however, it does suffer from moisture sensitivity. [35,36] [19,20] Our group reported the use of TPCL ( Figure 1A) as a low-k top encapsulating layer, which was crosslinked at the PVA interface, providing resistance to moisture, reducing the gate leakage while also enabling a thin hydrophobic layer which was impervious to dissolution from

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sequential solution deposition of the semiconductor. [18] We have also reported that the use of cellulose nanocrystals can increase the viscosity of the PVA layer during deposition, reducing the chance of fingering and providing a more uniform film and less short-circuited devices. [37] However, the leakage current of these bilayer devices can be further reduced through a tri-layer architecture. Therefore, we designed a tri-layer dielectric with the structure PLA/PVAc/TPCL. Furthermore, our initial studies suffered from relatively low TFT performance due to the low sc-SWCNT density on the TPCL. [18,38] Therefore we are targeting a TGBC architecture allowing for the substrates to be treated with OTS prior to sc-SWCNT deposition, leading to higher sc-SWCNTs network densities. [39,40] TPCL does not form uniform films on glass or OTS-treated substrates due to its tendency to aggregate. [18] Therefore, PLA was implemented as an alternative, environmentally friendly low-k layer that could be deposited above the sc-SWCNT and below the PVAc, acting as an intermediate layer between OTS and PVAc. Because PLA is insoluble in water it can be deposited without the risk of being rinsed away during the PVAc deposition. Some examples of trilayer dielectric structures similar to Figure 1B have also been reported. Subbarao et al used a poly(methyl methacrylate)/PVA/ Al 2 O 3 dielectric to further reduce leakage currents and encapsulate the PVA protecting it from moisture. [26,27] To the best of our knowledge, this is the first report of completely green tri-layer dielectrics being used in sc-SWCNT TFTs. In our previous work involving sc-SWCNTs and our PVAc/ TPCL bilayer dielectrics the devices were fabricated in a bottom gate top contact (BGTC) architecture. However, this architecture has certain limitations. For example, in a BGTC architecture, the sc-SWCNTs are exposed to the ambient environment which causes oxygen doping and supresses any n-type performance. [41,42] Further the TPCL surface does not allow for dense networks of sc-SWCNTs due to a mismatch in both water contact angle and surface energies. Sc-SWCNTs are commonly dispersed in toluene and have been demonstrated to form dense randomized networks when deposited on OTS surfaces. [12,31,40,43] Figure 2 shows atomic force microscopy (AFM) images of drop casted sc-SWCNTs and their varying network densities and alignments when deposited on quartz-coated glass (Figure 2A), OTS treated quartz-coated glass ( Figure 2B) and TPCL ( Figure 2C). Both AFM images of Figure 2A and Figure 2B demonstrate a much higher network density when compared to the TPCL network in Figure 2C. When fabricating sc-SWCNT transistors both network density and alignment are important. [12,44] The use of OTS improves the tail-to-tail alignment creating a webbed network, unlike the SWCNTs on quartz-coated glass. This leads to better overall TFT performance for the OTS-treated surfaces. By switching from a BGTC architecture to a TGBC architecture it is possible to use an OTS surface treatment to improve the deposition of the sc-SWCNTs while encapsulating the nanotubes enabling them to operate as n-type TFTs.
The properties of each layer were further analyzed through contact angle and surface energy measurements as seen in Table 1. The use of surface energy measurements allows for a better understanding of why sc-SWCNTs form denser networks on OTS-treated surfaces and can be used to help determine how to improve the sequential deposition of layers on top of an OTS-treated surface. Low surface energy materials are usually used as anti-adhesive layers. [45] This property is favorable for drop casting sc-SWCNTs from toluene because it allows the drops to bead and forms dense sc-SWCNT networks. However, it poses a challenge for orthogonal processing. There are two main factors contributing toward the adhesion between two materials one of which is the total surface energy of the material, and the other is the ratio between the polar and dispersive components of the material. [46] First, when orthogonally processing materials it's important to try and match their surface energies. The closer the surface energies of the materials the better the two layers will adhere to each other. [47] The total surface energies can be seen in Table 1 and Figure 3. The large difference between PVAc and OTS demonstrates that both these materials are incompatible for sequential deposition. However, the addition of a PLA interlayer with a lower total surface energy of 41.5 mJ m −2 makes it a better material for deposition on top of the OTS-treated substrates. Next, both the dispersive and polar components of the total surface energy can be seen in Table 1 and Figure 3. This metric is also important when determining the adhesion between materials. At the interface between both materials the polar portion of one material will only interact with the polar portion of the other material and it is the same for the dispersive portion. [46] This can be seen in   Figure 3 where 55% of the total surface energy is dispersive for PVAc whereas OTS is 99% dispersive. This can be improved by using PLA where 82% of the total surface energy is dispersive increasing its adhesion to OTS when compared to PVAc. Further, we also analyzed the deposition of PVA on top of PLA and silver using blade coating techniques and found that depositing PVA on top of PLA leads to lower variations in film thickness ( Figures S1 and S2, Supporting Information). When comparing the surface energies, we see that the low surface energy of OTS allows the toluene drops to bead and increase the density of the sc-SWCNTs networks. The increase in network density is vital for improving TFT performance however it complicated the sequential deposition of PVAc. Therefore, the addition of a thin PLA layer can act as an intermediate between the OTS and the PVAc increasing the adhesion between each layer.

Capacitor Characterization
Metal-insulator-metal capacitors were fabricated for both the PVAc/TPCL and PLA/PVAc/TPCL bi and tri-layers. The dielectric properties were characterized under ambient conditions, between 10 −1 and 10 5 Hz. The capacitance density of the PVAc/ TPCL dielectric stack is slightly higher at 85.5 nF cm −2 compared to 36.3 nF cm −2 for the PLA/PVAc/TPCL tri-layer dielectric as seen in Table 1. This is to be expected as the decrease in capacitance density is caused by the introduction of an additional low-k dielectric layer. [12] The capacitance is calculated as: where c tot is the total capacitance of the tri-layer dielectric and c 1 to c 3 is the capacitance of each material in the tri-layer dielectric. For standard dielectric materials increasing the thickness will reduce the capacitance. [15] Therefore, the addition of PLA as a low-capacitance material reduces the overall capacitance density. This highlights the importance of keeping the PLA layer thin to limit its impact on the capacitance of the tri-layer dielec-tric. The PLA layer is deposited at a concentration of 2 mg ml −1 allowing for films of ≈30 nm measured using profilometry. By keeping the PLA layer thin we can limit the impact it has on the capacitance density of the fabricated dielectrics. The change in capacitance density with frequency is also demonstrated in Figure 4. This highlights the frequency dependence caused by the polarization of the hydroxy groups in the PVAc dielectric. Figure 4 also demonstrates that the introduction of the PLA layer helps reduce variability in both the dielectric and capacitance density measurements.

Thin Film Transistor Characterization
TGBC sc-SWCNT TFTs were assembled using PVAc/TPCL bilayer and PLA/PVAc/TPCL tri-layer dielectrics. The transfer and output behavior of devices with both bilayer and tri-layer dielectrics were characterized under n-type operation. The devices were operated in their linear regime and the transfer curves were used to calculate the threshold voltage (V T ), on/off current ratios (I on/off ) and transconductance (g m ) values summarized in Table 2. The OTS-modified substrate led to the desired increase in sc-SWCNT network density as seen in Figure 2. Although a hydrophobic substrate improves the sc-SWCNT deposition, it introduced a challenge for coating a uniform film of hydrophilic PVAc using an aqueous solution. The poor adhesion between the OTS surface and PVAc dielectric led to a   reduction in functioning TFTs. This was improved using a PLA layer which formed a more uniform film on the OTS-treated substrate increasing the total surface area of the substrates that was covered by the tri-layer dielectric. The use of a tri-layer dielectric in TGBC devices led to an order of magnitude increase in I on/off for the fabricated devices as seen in Table 3. The increase in the I on/off ratio is caused by the introduction of a second low-k barrier between the semiconductor and the PVAc dielectric, further reducing the leakage currents. [26] This is consistent with previous reports showing significant improvements in I on/off by adding low-k interlayers. [17,18,20] The transconductance of sc-SWCNT TFTs have been recorded between 0.001 and 5 µS µm −1 with many studies between 0.1 and 1 µS µm −1 . [48] In this study, the bi and tri-layer TFTs have transconductances of 0.204 and 0.159 µS µm −1 as seen in Table 3. These values for the bi and tri-layer TFTs are within the average range for SWCNT TFTs. Further, within Table 3 the bilayer dielectrics have a higher transconductance which matches literature. [49] For example, Kim et al. [50] demonstrate that hydroxyl groups can be used to enhance n-type performance. The mobility of the fabricated TFTs were also estimated and shown in Table S2, Supporting Information. The use of a TGBC architecture along with the bi and tri-layer dielectrics also enables stable n-type TFTs under ambient conditions. This is due to the dielectric encapsulating the sc-SWCNTs and protecting them from degradation by oxygen and moisture. [51][52][53] The characteristic output and transfer curves of the bilayers and tri-layers are presented in Figure 5A,B,C, and D. The output curves for the tri-layers have a more stable saturation plateau compared to the bilayers, in which PVAc is directly in contact with the sc-SWCNT layer. The instability and nonideal TFT behavior is caused by charge trapping between the sc-SWCNTs and PVAc and can be seen for the bilayer devices at all source gate voltages while the increased leakage currents can also be perceived at the 0 V source-gate measurement. The transfer curve measurements also demonstrate similar performance between both the bi and tri-layer devices. The major difference in the transfer curves is the difference in off-state and source-gate leakage currents. The low-k PLA layer helps reduce leakage currents between the source and the gate while the TPCL layer prevents charge injection through the gate into the PVAc dielectric. The use of two low-k dielectric layers sandwiching the high-k layer compared to a single layer helps further reduce the off-state current of the fabricated TFTs while still providing similar device performance. Large gate leakage is a known issue with polymer dielectrics. Some of the ways to mitigate leakage currents are by increasing the thickness of the low-k layer or by increasing the band gap by selecting a polymer with a lower dielectric constant. [54,55] However, both these techniques can also reduce TFT performance. Overall, for TGBC architecture both bilayer

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and tri-layer dielectrics have a high n-type performance under ambient conditions with the tri-layer reducing leakage currents and allowing for better I on/off current ratios.

Conclusion
We demonstrated the use of a high-performance green trilayer dielectric with sc-SWCNT TFTs. The use of a TGBC architecture allowed for the substrates to be treated with OTS increasing sc-SWCNT network density which led to increased TFT performance. The TGBC architecture also allowed for n-type operation under ambient conditions. Furthermore, we demonstrated that the addition of a PLA layer can act as an intermediate layer between the OTS surface treatment and PVAc, improving the layer adhesion for orthogonal processing. The PLA layer also supressed the charge trapping and polar effects caused by PVAc at the dielectric/semiconductor interface and reduced the leakage current of the fabricated TFTs. In this work we managed to use a change in architecture along with an environmentally friendly tri-layer dielectric system to improve n-type sc-SWCNT TFT performance.

Supporting Information
Supporting Information is available from the Wiley Online Library or from the author.