Reliability Engineering of High‐Mobility IGZO Transistors via Gate Insulator Heterostructures Grown by Atomic Layer Deposition

The reliability of oxide‐semiconductor (OS) thin‐film transistors (TFTs) is significantly influenced by the gate insulator (GI). During electrical bias stress, the defect sites near the semiconductor/GI interface and/or within the GI may trap electrons, which makes the threshold voltage (Vth) shift toward positive values. On the other hand, carbon (C) or hydrogen (H) atoms may diffuse from the GI into the active layer, and act as shallow donors, which induce negative Vth shifts (ΔVth). In this paper, an in situ atomic layer deposition (ALD)‐based GI heterostructure is introduced, which consists of a stack of two complementary materials, namely Al2O3 and SiO2. Here, a competition occurs between electron trapping in Al2O3 (positive ΔVth) and carrier generation from H atoms in SiO2 (negative ΔVth) which allows the achievement of nearly zero ΔVth under positive bias temperature stress (PBTS). This strategy is successfully applied to a high‐mobility (>50 cm2 Vs−1) ALD‐based indium‐gallium‐zinc oxide (IGZO) device, resulting in a net ∆Vth of −0.02 V under PBTS and drain current variation (∆ID) of +0.49% under constant current stress (CCS). The application of an in situ ALD process thus offers valuable insights to resolve the mobility versus reliability trade‐off in high‐performance oxide TFTs.


Introduction
Thin-film transistors (TFTs) incorporating oxide semiconductors (OS) such as indium-gallium-zinc oxide (IGZO) were initially DOI: 10.1002/admi.202301097introduced by the Hosono group in 2004. [1]Such devices have received a lot of attention in the display industry owing to the possibility of obtaining uniform electrical properties over large area substrates, at relatively low costs.Their high field effect mobility (10-30 cm 2 Vs −1 ) and remarkably low off-current levels compared to hydrogenated amorphous silicon (a-Si:H) TFTs enabled the commercialization of active matrix organic light emitting diode (AMOLED) products operating at low frequencies over the last decade. [2]Currently, the mass production of IGZO TFT backplanes for displays involves the synthesis of oxide semiconductor layers by physical vapor deposition (PVD). [3]Due to the hyper-scaling requirements in microelectronics, new challenges occur for OS devices regarding nanoscale thickness control, thin film growth onto 3D structures, and further enhancement in field effect mobility (>50 cm 2 Vs −1 ), while preserving good reliability. [7]he atomic layer deposition (ALD) technique, which is based on self-limited chemical reactions, holds distinct advantages regarding the above requirements.For instance, OS films may be deposited onto intricate 3D structures with excellent step coverage, with precise control over the layer thickness and chemical composition.10] Ye et al.Recently reported the feasibility of atomic-level scaling of BEOL-compatible In 2 O 3 transistors based on ALD, which allowed accurate thickness control of the OS film to obtain an amorphous structure and optimize the free carrier density. [11,12]Additionally, our group disclosed the fabrication of high-mobility IGZO films by modulating the ALD cycles, to emulate a single-crystal-like structure. [13]Their uniform growth onto 3D structures was also demonstrated.
High-mobility OS TFTs are relatively sensitive to the incorporation of external impurities such as hydrogen or carbon, which act as shallow donors that generate free electrons. [14]he H atoms generally passivate the electron traps created by interstitial oxygen near the semiconductor/gate insulator (GI) interface, which in turn reduces the device degradation under positive bias temperature stress (PBTS).However, the excessive free carriers originating from the H donors induce largely negative initial threshold voltage (V th ) values.In order to obtain high mobility TFTs with relatively positive initial V th , the free carrier density must be reduced, for example by decreasing the amount of H atoms being incorporated, yet at the expense of PBTS stability.Therefore, a mobility versus stability trade-off exists in general.
The gate insulator that forms direct contact with the OS influences the device's reliability to a great extent.The GI may contain defects that act as electron traps, which determine the quality of the GI/OS interface.[17] On the other hand, the GI layer may also contain donor species such as hydrogen or carbon, which diffuse into the OS active layer during device fabrication and/or PBTS evaluation.][20][21] If both phenomena are present, competition occurs between charge trapping and free carrier generation in a device under PBTS.
The ALD technique emerges as a potential solution for the synthesis of GI films, which allows precise control of the defect and hydrogen contents.In previous work, the reliability of IGZO TFTs was improved by reducing the charge traps and donors in the GI grown by plasma-enhanced ALD (PEALD), where the plasma exposure time was a critical factor. [18]n the present study, a heterogeneous GI bilayer structure is conceived using an in situ ALD process to achieve high-stability devices under PBTS.Two different insulators, for instance alu-minum oxide (Al 2 O 3 ) and silicon oxide (SiO 2 ), are first synthesized separately.It is found that electron traps are dominant in Al 2 O 3 while donor species (H) abound as dominant, and so the two insulators contribute opposite V th shifts in their respective TFTs.When the two materials are stacked to form a SiO 2 /Al 2 O 3 heterostructure, the resulting IGZO device under PBTS exhibits a net ΔV th close to zero, which is interpreted to result from a nearly perfect balance between the above driving forces.The mechanism of this favorable effect is elucidated through thin-film analyses, device evaluation, and Technology Computer-Aided Design (TCAD) simulation.Consequently, an engineering solution is proposed to surmount the reliability limits in high-mobility IGZO transistors.

Results and Discussion
To evaluate the film properties, Al 2 O 3 and SiO 2 layers were independently grown by PEALD, each with a thickness of 20 nm.Here, identical plasma energy parameters (100 W, 1s) were used to exclude the plasma exposure effects on the underlying active layer during the fabrication of TFTs. [16]A heterogeneous stack was also prepared by the successive deposition of SiO 2 and Al 2 O 3 by an in situ PEALD process, where the optimum thickness of each material was 10 nm, thus forming a total thickness of 20 nm. Figure 1a-c illustrates the top gate (TG) TFT structures with Al 2 O 3 , SiO 2 , and SiO 2 /Al 2 O 3 GI, and each device will be respectively referred to as A20, S20, and SA hereafter.The electrical properties obtained from the transfer curve parameters are indicated in Figure 1d and Table 1.All devices exhibit similarly high field-effect mobility values exceeding 50 cm 2 Vs −1 and reasonably low subthreshold swing (SS) values of ≈70 mV per decade, regardless of the type of GI used.The device performance may thus be attributed to the indium-rich IGZO active layer, also grown by ALD.The representative transfer and output curves are shown in Figures S1 and S2 (Supporting Information).However, as anticipated, the devices under PBTS exhibit different behaviors with respect to the type of gate insulator.Figure 1e-g shows the time evolution of the transfer curves under PBTS, where each device is subjected to a gate stress of 2 MV cm −1 at 60 °C for 1 h.The V th shifts in the positive direction (∆V th = +1.21V) in the A20 device, and negative V th shifts (∆V th = −0.94V) are observed in the S20 device, without apparent degradation of the SS.Therefore it may be deduced that electron trapping near the IGZO/Al 2 O 3 interface is the major degradation mechanism in the A20 TFT, and free carrier generation (most likely from H atoms diffusing from the SiO 2 GI) is the dominant factor that governs the behavior of the S20 device.A considerably small V th shift (∆V th = −0.02V) is observed in the SA TFT, which leads us to suspect that equilibrium is achieved between the two driving forces originating from the Al 2 O 3 and SiO 2 dielectrics.In other words, charge trapping is compensated by the generation of free carriers, so that the net ∆V th is minimized.The behavior of the devices under PBTS was further assessed as a function of temperature and field strength, in order to substantiate this complementary effect.Figure 2a-c shows the ∆V th values under PBTS at different temperatures, while the gate field strength is fixed at 2 MV cm −1 .The A20 device does not appear to be affected by the stress temperatures between 30 and 120 °C, exhibiting a relatively constant ∆V th of ≈1 V in each case.This suggests that at a fixed gate field, the trap sites near the IGZO/Al 2 O 3 interface fully capture the free electrons during PBTS, regardless of the substrate temperature.Conversely, a negative ∆V th of ≈−1 V is observed in the S20 device at room temperature.As the substrate temperature is increased, the V th shifts further in the negative direction during stress.It may be inferred from the temperature dependence of ∆V th , that donor species such as H atoms diffuse from SiO 2 to IGZO, to generate free carriers in the active layer.In the SA TFT, the comparable magnitude of the opposite V th shifts in A20 and S20 devices effectively counter each other, so that ∆V th values near zero are obtained at all temperatures.The slight negative shift above 90 °C is likely to occur from the thermal diffusion of hydrogen atoms from the GI heterostructure into the underlying IGZO.
Figure 2d-f shows the ∆V th evolution as a function of the gate electric field applied during PBTS.In the A20 devices, the V th shift is negligible below 1 MV cm −1 but starts to increase at 2 MV cm −1 and above.This suggests that electron trap states near the IGZO/Al 2 O 3 interface and/or in the GI bulk appear to be located relatively deep in the Al 2 O 3 bandgap since electrons are trapped only when a gate field of 2 MV cm −1 or greater is applied.Further increase in the stress voltage accelerates the charge trapping phenomenon and results in larger V th shifts.On the other hand, the S20 devices undergo larger negative shifts in V th with increasing PBTS gate field.Here, it is highly probable that the diffusion of H atoms from the SiO 2 GI into IGZO has both temperature and gate field dependence.The diffusing donor species are most likely to consist of neutral and positively charged hydrogen (H 0 and H + ). [20]The SA TFTs exhibit nearly perfect stability with regard to PBTS, even at electric fields as high as 3 MV cm −1 .
Figure 3a shows the C-V characteristics of the Al 2 O 3 , SiO 2 , and SiO 2 /Al 2 O 3 dielectrics, which were measured in order to quantify the trap density in each GI system.The capacitance density of the accumulation region is highest in the A20 film and lowest in the S20 film, which is consistent with the average dielectric constant of each GI structure: Al 2 O 3 (6.83),SA (5.13), and SiO 2 (4.06).The flat band voltages of A20 and S20 are positive and negative, respectively.[24] The quantitative density of electron traps (N t ) in each GI was extracted from the anti-clockwise hysteresis (∆V) of the C-V curves; N t = C i × ∆V/q, where C i represents the GI capacitance in F cm −2 and q denotes the electron charge in C. [25][26] As depicted in Figure 3b, the trap density in Al 2 O 3 (3.24× 10 12 cm −2 ) is greater than that of SiO 2 (1.68 × 10 11 cm −2 ) by approximately an order of magnitude, corroborating the larger degradation of A20 TFTs under PBTS by charge trapping.
Note that the SA GI exhibits a trap density of 1.1 × 10 12 cm −2 , which is less than half the sum of the Al 2 O 3 and SiO 2 trap densities.In the SiO 2 /Al 2 O 3 stack, the donor species from the SiO 2 layer may have passivated a portion of the trap sites in Al 2 O 3 .Although the improvement in PBTS reliability of the SA devices is mostly due to the mutual compensation between charge trapping and carrier generation, such a reduction in the GI trap density may have partially taken effect as well.
The donor species diffusing from the GI, such as C and H atoms, readily form shallow donor-like states to contribute free electrons in oxide semiconductors.This effect is pronounced especially in high-mobility indium-rich oxide semiconductors due to the small activation energy (E a ) of n-type dopants. [14]In Figure S3  ).Assuming that the diffusion of H atoms is driven by the concentration difference between the insulator and the IGZO layers, SiO 2 is obviously expected to act as an abundant hydrogen reservoir, compared with Al 2 O 3 .In ALD films, the presence of hydrogen originates from the precursor ligands that are not completely eliminated.Figure 4a,b illustrates a schematic of the precursor structures and their adsorption onto the substrates.In Al 2 O 3 films, the hydrogen (H) atoms in trimethylaluminum (TMA) bond with carbon (C) to subsequently form volatile by-products.29] Additionally, secondary ion mass spectroscopy (SIMS) analyses were carried out on Al 2 O 3 /IGZO and SiO 2 /IGZO stacks to study the concentration profiles of hydrogen.Figure 4c shows no apparent H diffusion from Al 2 O 3 into IGZO after annealing at 350 °C in dry air for 3 h (heat treatment identical to that applied to the actual devices).Conversely, Figure 4d indicates clear H diffusion from SiO 2 into IGZO, to a depth of ≈10 nm.Prior reports indicate that the H permeability of Al 2 O 3 is fivefold smaller than that of SiO 2 , which makes it a rather good hydrogen diffusion barrier. [30]The above results suggest that it is reasonable to conclude that during PBTS, the diffusion of H atoms from SiO 2 into IGZO stimulates the formation of free electrons, thereby inducing negative shifts in V th .
The Technology Computer-Aided Design (TCAD) simulations were done to verify the likelihood of the compensation effect between carrier generation and charge trapping in the SA devices.The density of states (DOS) distribution of the IGZO active layer was standardized for the A20, S20, and SA TFTs to simulate solely the influence of the H content and electron traps within the GI on the PBTS behavior.The simulation parameters are listed in detail in Table S1 (Supporting Information).We configured the hydrogen-related charge generation reaction in the TCAD simulation as follows: The fitting of the simulated data with the actual measurement results was done by modulating the activation energy for electron trapping in the GI, the H content within the GI, and the activation energy for the above charge generation reaction.Based on the thin-film analyses, it was postulated that the A20 TFTs contain relatively small amounts of internal H atoms and large electron trap densities, whereas S20 devices consist of high H contents and fewer charge traps.For the SA-TFTs, we utilized the simulation parameters of the A20 and S20 TFTs and examined the device behavior under stress conditions.Figure 5a-c shows the simulated data of the A20, S20, and SA TFTs under PBTS.It may be verified that electron trapping in the GI and H diffusion from the GI markedly influence the positive and negative V th shifts during stress, respectively.As observed in the SA devices, a competition between the two mechanisms may take place in a GI heterostructure, with virtually no ∆V th under PBTS.Figure 5d,e delineates potential phenomena occurring in the A20, S20, and SA TFTs during stress.In the A20 devices, upon applying a bias stress of 2 MV/cm or higher, electrons in the active layer are trapped in the deep states of Al 2 O 3 , leading to positive V th shifts.Conversely, in the S20 TFTs, the creation of free carriers by the H atoms diffusing from SiO 2 into IGZO leads to negative V th shifts.In the SA devices, which incorporate SiO 2 /Al 2 O 3 GI stacks, the H atoms from SiO 2 diffuse into both IGZO and Al 2 O 3 layers.While the creation of free carriers counters the charge trapping during PBTS, the H atoms may also passivate some of the electron traps in the upper Al 2 O 3 .Because the defective sites in Al 2 O 3 are located at a physical distance from the IGZO/SiO 2 interface, their passivation by the injection of hydrogen may have had relatively little influence regarding the suppression of positive V th shifts under PBTS.However, there is no substantial evidence that one may completely neglect this effect.
Constant current stress (CCS) is an important consideration in display backplanes.For example, the driving TFTs in organic light-emitting diode (OLED) panels provide constant current levels to the emissive layer in order to maintain stable brightness.Figures 6a-c show the CCS evaluation of the A20, S20, and SA devices under identical conditions (V GS = 4 V and V DS = 1 V for 1 h at 25 °C), where the drain current variations (∆I D ) are monitored.In a fashion similar to the V th shift under PBTS, the drain current of the A20 TFTs decreases (∆I D = 77.59-100= −22.41%)due to electron trapping in the GI.On the other hand, the drain current increases in the case of the S20 devices (∆I D = 126.96-100= 26.96%)owing to the generation of free carriers, as was observed in the PBTS results.Finally, the SA TFTs sustain the drain current with a variation of only ∆I D = 100.5-100= +0.50%,as depicted in Figure 6c (inset).It may thus be deduced that the mutual compensation between charge trapping and electron generation indeed takes effect.The SA devices retain the drain current levels with a variation of only 0.49% even under a prolonged CCS time of 3 h, as shown in Figure S5 (Supporting Information).Figure 6d elucidates the concept of the above compensation effect, illustrating how the device degradation may be suppressed by the use of a GI heterostructure, which would otherwise be very difficult to achieve with a conventional single GI layer.The authors believe that the in situ ALD process presented in this work is an adequate method to fabricate stable gate insulator stacks that allow the realization of high mobility devices with extremely high stability.

Conclusion
Gate insulator heterostructures were developed based on in situ ALD in order to fabricate top-gate IGZO transistors with remarkable PBTS reliability while preserving high field effect mobility  (>50 cm 2 Vs −1 ).Single Al 2 O 3 gate insulators induced positive V th shifts under PBTS, predominantly due to the trapping of electrons near the IGZO/Al 2 O 3 interface.On the other hand, the use of single SiO 2 gate dielectrics resulted in the generation of free electrons owing to the high content in H atoms, thus making the V th shift toward negative values.In this regard, SiO 2 /Al 2 O 3 heterostructures were conceived to minimize ∆V th to values close to zero, by properly engineering the competition between the above mechanisms.The mutual compensation between electron trapping and free carrier generation was substantiated by a quantitative analysis of thin films and TCAD device simulations.The design of GI heterostructures via in situ ALD thus emerges as a cornerstone to the development of high mobility oxide TFTs with nearly perfect stability.

Experimental Section
Thin-Film Deposition: The Al 2 O 3 and SiO 2 films were deposited by PEALD with trimethylaluminum (TMA) and di-isopropylamino silane (DI-PAS) as the Al and Si precursors, respectively.All process parameters of PEALD (plasma power/time, working pressure, gas, and temperature) were kept identical, except for the precursors.Argon was used as the car-rier and purge gas at a constant flow rate of 200 sccm.The reaction gas consists of a mixture of oxygen and argon.The deposition temperature and process pressure were 200 °C and 1.2 mTorr, respectively.The same Ar/O 2 plasma was used with a power of 100 W for 1 s in both processes to exclude the plasma effects on the active layer.The growth per cycle of Al 2 O 3 and SiO 2 were 1.35 Å per cycle and 1.08 Å per cycle, respectively.The heterogeneous SiO 2 /Al 2 O 3 stack (SA) was grown sequentially in situ using the above PEALD processes.
Thin-Film Evaluation: The quantitative density of electron traps (N t ) and capacitance of each gate insulator structure (Al 2 O 3 , SiO 2 , SA) were calculated from the capacitance-voltage characteristics of the transistors using an LCR meter (HP 4284A).The N t in each GI was extracted from the anti-clockwise hysteresis (∆V) of the C-V curve; N t = C i × ∆V/q, where C i is the GI capacitance in F cm −2 , and q is electron charge in C.  The devices were evaluated using a Keithley 4200 semiconductor analyzer.For the output curve measurements, the drain-to-source voltage (V DS ) was swept from −5 to 5 V while the gate-to-source voltage (V GS ) was swept from 0 to 5 V, each with 1 V increments.The transfer curves were measured by sweeping V GS in both forward and reverse directions between −5 and 5 V, with V DS fixed at 0.1 and 1 V.The electrical parameters were extracted from 10 devices using each GI structure using the following equations: field effective mobility,  FE = L WC i V DS g m max where L, W, and g m max are the length of the device, the width of the device, and the maximum transconductance, respectively.The C i values in the TFTs were calculated from C-V measurements.The devices were subjected to PBTS with gate field strengths from 0 to 3 MV cm −1 and temperatures of 30, 60, 90, and 120 °C, for 1 h each.The CCS was conducted under V GS = 4 V and V DS = 1 V for 3 h.The drain current variation (∆I D ) before and after CCS was monitored.
Device Simulation: TCAD analyses were done to verify the proposed device degradation mechanisms.Using the Victory Process, Victory Device, and Tony Plot tools from the TCAD simulation suite (Silvaco, Inc.), the electrical properties of the TFTs under different stress conditions were evaluated.The density of states (DOS) model of the IGZO active layer was standardized, in order to simulate the effect of the GI structures only.The transfer curves were fitted with experimental data by adjusting the activation energy of electron trapping in the GI, the H content within the GI, and the activation energy of the charge generation reaction.The simulation parameters of the A20 and S20 TFTs were employed to simulate the SA devices, and their behavior under stress was analyzed.The simulation parameters are listed in detail in Table S1 (Supporting Information).

Figure 2 .
Figure 2. Variations of ΔV th under PBTS for the A20, S20, and SA TFTs with respect to a-c) temperature and d-f) gate field magnitude.

Figure 3 .
Figure 3. a) Capacitance voltage characteristics and b) quantitative trap density in each GI structure; A20, S20, and SA.
(Supporting Information), the carbon signals measured by Xray photoelectron spectroscopy (XPS) after removing the surface contamination are similar to the background noise levels in both Al 2 O 3 and SiO 2 .The negligible carbon contents indicate that the metal cation precursors used in the PEALD process have decom-posed adequately.However, hydrogen atoms are present in both Al 2 O 3 and SiO 2 films.As shown in Figure S4 (Supporting Information), elastic recoil detection (ERD) was performed to estimate the hydrogen concentrations in Al 2 O 3 (3.27× 10 16 cm −2 ), SiO 2 (3.74 × 10 16 cm −2 ), and IGZO (9.75 × 10 15 cm −2

Figure 4 .
Figure 4. Schematic of precursor and adsorption of a) trimethylaluminum (TMA) and b) di-isopropylamino silane (DIPAS).c,d) Dynamic-SIMS depth profiles of H atoms across the GI/active interface.The intensities are converted to quantitative H concentration based on Rutherford backscattering spectroscopy (RBS) and ERD data.

Figure 5 .
Figure 5. a-c) TCAD simulation of the device behaviors under PBTS.The dotted lines represent experimental TFT characteristics, and the solid lines consist of the TCAD fitting results using density of states (DOS) modeling.d-f) Possible degradation mechanisms in the A20, S20, and SA TFTs.
The dielectric constants of the Al 2 O 3 , SiO 2 , and SA films were calculated from the measured GI capacitance values.The carbon impurity contents within the films were examined by XPS, K-alpha, at the Hanyang Center for Research Facilities (Seoul)).The H contents in the Al 2 O 3 , SiO 2 , and IGZO thin films were measured by Rutherford Backscattering Spectrometry -Elastic Recoil Detection (RBS-ERD, KIST Advanced Analysis Center, NFC).The depth profiles of H atoms from the GI to the active layer before and after annealing were quantified based on dynamic secondary ion mass spectrometry (D-SIMS, KIST Advanced Analysis Center, CAMECA) by converting the H signals from D-SIMS analysis to H concentration based on RBS-ERD data.D-SIMS was performed with a Cs+ ion gun at 14.5 keV impact energy.

Figure 6 .
Figure 6.a-c) Constant current stability (CCS) of A20-, S20, and SA-TFTs under V GS = 4 V and V DS = 1 V for 1 h.d) Illustration of the net zero concept based on the quantitative comparison between electron trapping sites in GI and donor-induced species in A20-, S20-, and SA-TFTs.