Capacitance-Voltage (C-V) Characterization of Graphene-Silicon Heterojunction Photodiodes

Heterostructures of two-dimensional (2D) and three-dimensional (3D) materials form efficient devices for utilizing the properties of both classes of materials. Graphene/silicon (G/Si) Schottky diodes have been studied extensively with respect to their optoelectronic properties. Here, we introduce a method to analyze measured capacitance-voltage data of G/Si Schottky diodes connected in parallel with G/silicon dioxide/Si (GIS) capacitors. We also demonstrate the accurate extraction of the built-in potential ($\Phi$$_{bi}$) and the Schottky barrier height from the measurement data independent of the Richardson constant.

In this work, we introduce a method for accurate C-V characterization of G/Si heterojunctions with a parallel GIS capacitor. To evaluate the effect of the GIS capacitor, we performed C-V measurements at small AC signal on G/n-Si Schottky diodes with varying dimensions of the GIS region and on a reference capacitor without Schottky junctions. From these measurements, we propose a methodology to extract the built-in potential (Фbi) and the SBH. Fig. 1a shows schematics of two G/n-Si diodes, D1 and D2, with varying GIS areas. Current density-voltage (J-V) characteristics of both diodes under dark condition are displayed in Fig.   1b in a semi-logarithmic scale. In order to calculate the current density, the measured current is normalized to the G/Si Schottky area, which is marked with a dashed red line in Fig. 1c. Both diodes exhibit rectifying characteristics in the dark with rectification ratios up to 3.8 × 10 4 and 2.94 × 10 4 for D1 and D2, respectively. The basic parameters of the diodes such as n, SBH and Rs are obtained from the forward J-V characteristics in dark condition using the Cheung method [31] . For D1 and D2, n of 2.08 and 2.3, SBH of 0.76 and 0.79 eV and S of 24 and 14 kΩ have been extracted, respectively. Details of the calculation of the diode parameters are described in our previous work [27] (see Fig. S2 in supporting information therein). It should be noted that the extracted values of SBH slightly differ from the true SBH of the devices. This is because the theoretical value of the Richardson constant (A * * ) for n-Si (112 Acm −2 K −2 ) was considered in order to obtain the SBHs. [27] For standard Schottky junctions, where a threedimensional (3D) metal is in contact with Si, the Richardson constant is typically estimated by considering the velocity vector component of electrons normal to the barrier plane and with a kinetic energy greater than the barrier height. For 2D-graphene on silicon, the electron is lockedup between a potential wall, on one side constituted by electron affinity of the graphene layer and, on the other side, by the silicon energy barrier. Trushin suggested that the current across the G/Si barrier can be estimated by considering the tails of electron wave functions pointing into the n-type silicon conduction band. [32] This motivates a much lower effective Richardson constant than that of 3D-metal/Si junctions. It is then clear from the expression for the reverse saturation current of the thermionic emission model [33] , that a lower Richardson constant results in a slightly lower value of SBH. Thus, in order to obtain a value for SHB with high precision, the Richardson constant must be appointed with care. We have therefore performed C-V measurements to obtain SBH values of devices independent of the Richardson constant.  Small-signal C−V characteristics of the devices under study (D1 and D2) in comparison with the test device are shown in Fig. 3a. Both D1 and D2 display similar C-V characteristics and can be modelled with an equivalent circuit model, containing a Schottky junction diode in parallel with the GIS and MIS capacitors (see inset of Fig. 3a). The capacitance due to the metal-Si contact (bulk contact) is neglected as the contact is believed to be ohmic. For forward bias voltages (Vbias) above Фbi (calculated below), both diodes are in on-state and the depletion width in the Schottky junction is strongly reduced. Therefore, the Schottky junction capacitance is boosted, resulting in a strong increase in the measured capacitance. The decreasing capacitance in the range of -0.6 V to qФbi (compared to Fig. 3a) due to the growing depletion layer capacitance (Cdepletion) of the G/Si junction that overcomes the MIS+GIS capacitance. For Vbias < −0.6 V, the bias-independent capacitance shows that the MIS+GIS junction, which is now in deep inversion, dominates the Schottky diode. Therefore, Vth for both devices (D1 and D2) is around -0.6 V.

Results and discussions
Фbi, SBH and ND of the devices can be determined from the measured C-V data.
Generally, the extracted SBH is expected to be equal to the SBH estimated from J-V measurements. The estimated value for ND should be in the same range as the doping density of the Si substrate used to fabricate the devices. The relation between C and Vbias can be expressed by Eq. 1 for a non-ideal Schottky diode with an ideality factor n and an interfacial oxide layer between the metal and the semiconductor [34] : where , , and kB are the elementary charge, the absolute temperature and the Boltzmann constant, respectively. Hence, a linear graph is expected when plotting 1/C 2 versus Vbias for a Schottky junction with a constant ND within the depletion layer. In addition, the SBH can be obtained using Eq. 2 [34] : where Ф is the effect of SBH lowering and Ф * is the potential difference between the conduction band and Fermi level of Si. Ф * can be estimated using Eq. 3 [33] : where NC is the effective density of the states in the conduction band of Si, which is equal to 2.8 × 10 19 cm −3 . Devices D1 and D2 feature combined G/Si, GIS and MIS structures. Thus, the contribution of the GIS and MIS capacitors must be deducted from the measured total capacitance in order to obtain the capacitance of the Schottky junction (G/Si). Afterwards, Фbi and ND can be extracted from the intercept on the Vbias -axis and the slope, respectively, of the "1/C 2 vs. Vbias" plot. Then, the SBH can be calculated using Eq. 2. To obtain the C-V characteristics of the Schottky junction, we assumed that the MIS and GIS capacitors of the present devices behave similar to that of the test structure. Therefore, the Schottky junction capacitance for D1 and D2 can be estimated with Eqs. 4 and 5: where fg% ( fg) ) is the Schottky junction capacitance of D1 (D2), % ( ) ) is the area of GIS+MIS area in device D1 (D2), o lm8l is the total area of the test device, which is equal to the graphene area plus area of the metal electrode connected to graphene, and o lm8l is the measured capacitance of the test structure. As pointed out earlier, the A** for G/Si junctions are expected to be smaller than the theoretical value considered and that will result in a smaller SBH. We therefore believe that this small difference between the SBHs extracted from I-V and C-V measurements would vanish when using the correct value of A**, which is not known at the moment.

Conclusions
C-V measurements were performed on G/Si Schottky diodes with inherent parallel GIS and MIS capacitors. We introduced a method for precisely evaluating the C-V characteristics of these structures. The method provides an alternative way of determining the Schottky barrier height and can be used to crosscheck the consistency of values obtained from analyses of measured I-V data, which may be prone to errors because of an unclear exact value of the Richardson constant.

Methods
Device Fabrication: A phosphorus-doped Si wafer with a resistivity of 1 to 20 Ω.cm was used as the initial substrate. Then, 20 nm SiO2 has been grown on the Si surface using a thermal oxidation process and the wafer has been diced into 20×20 mm 2 chips. The n-Si substrate has then been partially exposed by etching the SiO2 layer using buffered oxide etchant (BOE) after a first UV-photolithography step. This step has not been performed for the fabrication of the test structures. Afterwards, metal electrodes have been formed through a second photolithography step, followed by the deposition of (15/85 nm) chromium (Cr)/nickel (Ni) and a liftoff process. Large-area graphene has been grown on a copper (Cu) foil in a Moorfield NanoCVD rapid thermal processing tool using the chemical vapor deposition (CVD) method. [35] A polymer-supported wet chemical etching transfer technique has been used to transfer graphene films onto the pre-patterned substrates immediately after native oxide etching in BOE to ensure a pure G/Si Schottky junction for the diodes. [36] During transfer, the graphene on Cu foil has been spin-coated with Poly methyl methacrylate (PMMA) and baked for 5 minutes at 85°C. After cutting it into ~ 7 mm 2 pieces, Iron (III) chloride (FeCl3) has been used to etch the Cu foil and the polymer-supported graphene films have been rinsed in HCL followed by DI-water. Then, the chips have been baked on a hotplate for 35 min at 180°C, followed by removal of the PMMA layer in hot acetone (55°C) for one hour. Afterwards, they have been cleaned with isopropanol and dried with nitrogen. Finally, graphene has been patterned through a last photolithography step, followed by etching of graphene in oxygen plasma.
Electrical Characterization: I-V measurements have been performed on the diodes using a Karl Süss probe station connected to a Keithley semiconductor analyzer (SCS4200) under ambient condition. The voltage has been swept from 0 to +2 V for forward (VF) and from 0 to -2V for reverse (VR) biasing, for all the diodes. C-V measurements have been carried out using the same probe station connected to an HP Impedance Analyzer (HP 4294A). The measurements have been performed using a small AC signal amplitude of 25 mV at 10 kHz frequency superimposed to a DC bias voltage, which was swept from −4 V to 4 V. The parallel circuit model (conductance in parallel with capacitance) has been used for the measurements.