Maximizing absorption in photon trapping ultra-fast silicon photodetectors

Silicon photodetectors operating at near-infrared wavelengths with high-speed and high sensitivity are becoming critical for emerging applications, such as Light Detection and Ranging Systems (LIDAR), quantum communications, and medical imaging. However, such photodetectors present a bandwidth-absorption trade-off at those wavelengths that have limited their implementation. Photon trapping structures address this trade-off by enhancing the light-matter interactions, but maximizing their performance remains a challenge due to a multitude of factors influencing their design and fabrication. In this paper, strategies to improve the photon trapping effect while enhancing the speed of operation are investigated. By optimizing the design of photon trapping structures and experimentally integrated them in high-speed photodetectors, a simultaneous broadband absorption efficiency enhancement up to 1000% and a capacitance reduction of more than 50% has been achieved. Such work also allows to present empirical equations to correlate the quantum efficiency of photodetectors with the physical properties of the photon-trapping structures, material characteristics, and limitations of the fabrication technologies. The results obtained, open routes towards designing cost-effective CMOS integrated.

This extensive exercise along with the uncertainties in the fabrication processes contribute to significant challenges in optimizing the device performance.
We conducted extensive simulation and designed vertical pin photodetectors with more than 150 unique integrated PT structures by varying size, shape, period, and orientations, and established a crucial correlation between these parameters to enhance the device performances. Our rigorous simulations and extensive experimental investigations enabled a combination of optimum parameters to help to overcome the trade-off between bandwidth and efficiency in the PDs. Besides, it allows high sensitivity for low levels of photon detection with 500% higher external quantum efficiency (EQE) as compared with the conventional PDs at 850 nm wavelength, and up to 1000% enhancement at other NIR wavelengths around 1000 nm. Additionally, our fabricated devices exhibit more than 50% reduction in junction capacitance due to the introduction of PT structures, and this, in turn, improves the device bandwidth. The extensive design variations make it the most comprehensive study aimed at understanding the PT phenomenon in high-performance PDs. To enable performance projections, it is of interest to develop simple, closed-form expressions for the EQE of a highspeed PT photodetectors that intuitively connect the physical parameters of the PT structures, material characteristics, and quality of fabrication. This work elucidates such crucial expressions to enable the implementation of the PT structures for absorption efficiency enhancement, capacitance reduction, and faster time response.

Device design and Fabrication
The cross-sectional designs of mesa type Si pin PDs with and without integrated PT structures are schematically shown in Figure 1a-b, respectively. The PDs consist of heavily doped p (p++) and n (n++) type Si layer and a 2 μm of thin intrinsic layer, epitaxially grown on the top of Silicon on Insulator (SOI) or bulk Si substrates. The PDs are fabricated with a different diameter (D) ranging from 30 to 500 µm. An SEM image of fabricated PD is depicted in Figure 1c. An array of micro/nanoholes is patterned with a funnel shape or inverted pyramid etching profiles on the surface of the PDs, which serves as potential PT structures. These nanoholes are distributed in hexagonal or square lattices, designed with different diameters (d) and periods (p) ranging from 630 to 1500 nm and 900 to 3000 nm, respectively. Figure 1d represents the top and cross-sectional SEM images of PT holes with a tapered funnel and inverted pyramid shapes. The dimensions of the PT structures are selected to be close to the wavelengths of interest. The periodic distance between structures is reduced in each set of devices by keeping the d fixed, allowing to increase the number of nanoholes that can be accommodated on the surface of PD. The depth of the nanoholes was etched to be around 2 μm for funnel shape, while it varies between 450 to 1000 nm for inverted pyramids. Also, an unpatterned device is fabricated as a reference which we call a control device to compare with the PT PDs (See Figure S1 and Table S1 in Supporting Information for more details on the investigated devices with the variation of different parameters, such as substrate, the diameter of PT holes, and periods).

External Quantum Efficiency
EQE is one of the key parameters that describes the sensitivity of PDs. Herein, several PT PDs with integrated nanoholes are designed, optically simulated, and fabricated, while the period, diameter, and number of nanoholes (N) are systematically varied. Employing the following design guidelines, one can easily fabricate an optimized device by performing simulations beforehand. Firstly, the influence of the N on the measured EQE is studied, where a set of devices with a constant device D of 50 µm is characterized. SEM images of such devices with different N are illustrated in the inset of Figure 1e and Figure S2. The measured EQE is presented in Figure 1e for PT PDs with a fixed period and diameter of 1000 and 700 nm, respectively for hexagonal lattice and inverted pyramid profile on SOI, where the N is varied from 0 (control) to 820. Compared to the control device with an EQE of ~12%, the EQE of the PT devices gradually increases with increasing N, exhibiting a maximum of >38% for an N value exceeding 820. It is important to note that the test devices above were not among the designs with optimum parameters. This experiment mainly demonstrates a correlation between the EQE of a photodetector and N. Other periods and diameters that were optimized contributed to considerably higher peak efficiencies. The EQE enhancement observed in the device is due to the improved coupling of vertically incident light into laterally propagating modes with increasing N within the same area of the devices. Besides, a reduction of planar area in a device leads to decreased surface reflection and improved transmission of the incident light, resulting in relatively higher absorption in the photoactive layer. Consequently, the overall EQE of the PT devices is distinctly increased in comparison to the control device.
Next, EQEs of 500 μm devices with higher N values and maximum up to 145000 nanoholes with the same design as 50 μm diameter devices are added to establish a relationship as shown in Figure 1e (top inset). It shows that, for this design with d/p=700/1000, the EQE value can saturate at ~56% for approx. 5000 nanoholes. The maximum N presented in Figure   1e is 820 with a filling fraction (Areaholes / Areadevice) of only 16% for the 50 µm device (see Supporting Information Figure S3 for other filling fraction values), while a maximum of about 5000 nanoholes can be accommodated in the same device contributing to a very high filling fraction. Advanced foundry processes can accommodate almost 100% filling fraction by reducing the size of the features (such as contact electrodes, the separation between the region covered by the holes, and interconnect) using tighter fabrication tolerances.
Based on the fitting curve, an empirical equation can correlate the EQE of the devices with the photon-trapping structural and device parameters, where ηPT is the EQE of a PT PD for a specific N, ηmax is the maximum possible EQE (simulated value) for the device, a and b are design constants which were calculated to be 41 and 0.00147, respectively, for this design, and Δ is the ideality factor of the device. Δ represents the degrees of perfection in the fabrication process and material quality. When the value of Δ is 1, ηPT value gets closer to ηmax. Imperfection in device fabrication and the impurity of materials could lead to Δ smaller than unity, whereas in our devices, it varied  Table S3, Supporting Information with an inverted pyramid exhibit relatively higher EQE than the devices with a funnel shape.
For instance, the inverted pyramid PDs with d/p of 0.81 exhibit an EQE over 60%, whereas the EQEs exhibited by funnel shape are lower than 50% (see Figure S4, Supporting Information). This discernible enhancement obtained in the inverted pyramid can be attributed to the effective refractive index gradient in the interface of air and Si, resulting in a superior antireflection effect and efficient coupling of light over a wide wavelength and angular ranges. [36] This is an added advantage of PT structures over traditional quarter-wavelength thin-film antireflection coatings. [37] The experimental results can lead to an empirical equation to capture the correlation between ηPT and the d/p in a very generalized fashion, where ηflat is the EQE of the control devices and β is the PT factor. β can be determined from the slope of a linear curve connecting multiple EQEs as a function of d/p. Equation 2 is valid for PD with both hexagonal and square lattices with varying β values, provided that a sufficient number of PT nanoholes are integrated on the surface of the PDs to reach saturation level in photon absorption (see Table S2  FDTD simulated EQE of a PD with funnel shape structure is also included (hollow red circle).
Devices exhibit EQE from 15% to more than 60%. b) Broadband EQE enhancement in the fabricated PDs for wavelengths ranging from 800 to 1000 nm with a diameter of 1000 nm and decreasing periodicity. Inset: A 10x enhancement in EQE is observed at some wavelengths.

Bandwidth enhancement External
In junction PDs, the 3dB bandwidth is dependent on two parameters: the carrier transit time (tr) and the RC constant-time. [38] A reduction in the junction capacitance due to the presence of the PT nanoholes can be taken into consideration to write the following modified expression of f3dB.
Where tr is the transit time required for the carriers to reach the electrode at saturation velocity, R is assumed as 50 Ω, and ff is the filling fraction of the nanohole array (see Figure   S8, Supporting Information). By considering the pin PD as a parallel plate, the capacitance can be written as C=εoεrA/w, where εo and εr are the permittivity of vacuum and silicon, respectively; w is the depletion layer width, typically the i-layer, and A is the junction area. Supporting Information and other references. [39] Furthermore, the same investigation is also conducted for devices with 40 and 50 µm diameter and included in Figure S7. Higher 13 capacitance reduction is observed as the diameter of the PDs increases since, in our current design, a larger diameter of PD allows to accommodate a higher number of nanoholes. Both devices can reach >50% (see Figure S9, Supporting Information) of capacitance reduction by decreasing the area occupied by the ohmic contacts on the surface of the PDs using CMOS foundries where the width of metal contacts can be less than 150 nm. [40]

Conclusion
Through

Experimental Section
Fabrication of photon trapping photodetectors: Mesa type Si pin PDs are fabricated with a total thickness of 2.5 µm. Heavily doped regions of p and n exhibit reduced electron and hole lifetime of carriers, respectively, facilitating relatively lower diffusion of photogenerated carriers into the high-field i-layer region. Additionally, it reduces the series resistance. The fabrication processes were done in class 100 cleanroom. The PIN wafers on bulk Si or SOI were cleaned in a piranha solution (10:1) to remove organic residues. For inverted pyramids nanoholes, 200 nm of silicon nitride was deposited by PECVD at 250 °C and serves as a masking layer for KOH etching. Next, DUV lithography was used to pattern the nanoholes on the wafer followed by DRIE etching to pattern the silicon nitride. KOH etching was performed with a solution at 33% for 2:30 minutes at 65 °C. Next, DRIE was used to reach the n-mesa and p-mesa of the device, allowing to deposit by evaporation 100 nm of Al and 200nm of Pt that serves as the n-ohmic and p-ohmic contacts. Finally, the wafers were treatment with HF for 10 s to minimize the leakage current. For the fabrication of funnel shape nanoholes [41] and other passivation methods [42] can be found in other references.