Organic Electronics Picks Up the Pace: Mask-Less, Solution Processed Organic Transistors Operating at 160 MHz

Organic printed electronics has proven its potential as an essential enabler for applications related to healthcare, entertainment, energy and distributed intelligent objects. The possibility of exploiting solution-based and direct-writing production schemes further boosts the benefits offered by such technology, facilitating the implementation of cheap, conformable, bio-compatible electronic applications. The result shown in this work challenges the widespread assumption that such class of electronic devices is relegated to low-frequency operation, owing to the limited charge mobility of the materials and to the low spatial resolution achievable with conventional printing techniques. Here, it is shown that solution-processed and direct-written organic field-effect transistors can be carefully designed and fabricated so to achieve a maximum transition frequency of 160 MHz, unlocking an operational range that was not available before for organics. Such range was believed to be only accessible with more performing classes of semiconductor materials and/or more expensive fabrication schemes. The present achievement opens a route for cost- and energy-efficient manufacturability of flexible and conformable electronics with wireless-communication capabilities.


Introduction
The development of new applications in the fields of healthcare, energy, distributed sensing and entertainment will require the integration of electronic functionalities into everyday objects. Organic electronics has gained its place among the promising technologies to this purpose, owing to a set of distinctive features: [1] first, it is compatible with flexible substrates, which allows its integration with objects characterized by non-conventional form factors; second, it enables the use of deposition techniques derived from the graphic arts and gives access to cost-efficient manufacturing; third, selected organic materials are biocompatible, allowing for a high degree of integration between electronics and biology. The impressive progress in this field has been driven by: (i) the enhancement of a set of figures of merit, primarily the charge mobility of the semiconductors, now well exceeding amorphous silicon and rivalling low temperature deposited metal oxides; [2] (ii) the strengthening of cost-and energy-efficient fabrication strategies, with the notable examples of printing [3,4] and laser processing, [5][6][7] which are now suitable for the micron-scale patterning of functional materials on large area; (iii) the demonstration of a set of proof-of-concept applications, including green/biodegradable electronic devices, [8] electronic skins and conformable patches for personal healthcare [9][10][11][12] or flexible organic microprocessors. [13] However, in order to widen the set of applications that can be envisioned, a set of functionalities is still lacking. Among these, wireless communication between distributed electronic sensors/actuators and data-processing devices, or fast addressing capabilities for large-area arrays of sensors or light-emitting devices. The implementation of these functionalities would enable flexible large-area displays or sensor arrays and the creation of distributed wireless networks of electronic devices within the Internet of Things (IoT) framework. [14] So far, this set of applications has been considered out of reach for organic electronics.
A fundamental requirement to this goal is the realization of organic transistors, the basic building block of electronic circuits, operating at frequencies well above several tens of MHz and above. Such performance should also be obtained with the sole use of mask-less and scalable fabrication processes, in order to retain the manufacturability edge of organic devices. [15] One of the most widely adopted figures of merit to quantify the maximum operation frequency of single transistors and allow comparison among different technologies is the transition frequency f t , namely the frequency for which the ratio between the small-signal drain and gate currents is unity. [16] To date, the highest f t obtained for a an Organic Field-Effect Transistor (OFET) is 27.7 MHz . [17] Since f t is proportional to the bias voltage, some authors have used the voltage-normalized transition frequency f t /V as a more convenient figure of merit to assess the relative performance of transistor technologies. [5,18,19] In this case, the highest f t /V value achieved for OFETs is 2.23 MHz/V, [20] achieved by virtue of a metaloxide/self-assembled monolayer dielectric layer with high areal capacitance (700 nF/cm 2 ), a sub-micron channel length defined via high-resolution silicon stencil masks and extremely low contact resistance (29 Ωcm) between gold electrodes and a small-molecule organic semiconductor. These results however, together with the wide majority of the works on highfrequency OFETs, included masks and/or evaporation steps in the process flow. [21][22][23][24] Such an approach, while allowing the access to improved performances by virtue of an enhanced control over the deposition of the functional layers, poses a number of difficulties in terms of the future scalability to cost-efficient mass production. The sole use of mask-less directwriting or solution-based techniques largely complicates the achievement of high-frequency operation, an issue also testified by the very limited number of attempts in the past. [5,[25][26][27][28] As of now, despite the technologies and materials exhibiting the performances required for high-frequency operation in excess of several MHz and approaching the 100-MHz range (i.e. charge mobility approaching 1 cm 2 /Vs and patterning resolutions below 1 µm) are in principle available, further progress has been hampered by a set of critical aspects that have been often 3 overlooked. Primarily, the achievement of high effective charge mobility in downscaled transistors requires to obtain normalized contact resistances (R c W) below 1 kΩcm (or less, depending on the other physical parameters and bias point of the transistor), which have been rarely demonstrated. [19] This aspect is intertwined with the need for reduction of the capacitive parasitism related to the gate-to-source and gate-to-drain geometrical overlap, which, in the frame of the current-crowding injection model, also affects charge-injection in a non-trivial way. [15] Finally, the design of efficient strategies for the dissipation of the generated heat becomes of paramount importance in order to prevent the destructive breakdown of the device and to allow for continuous-mode operation: downscaled OFETs with channel lengths in the order of the µm, sustaining a current per unit width in excess of 1 mA/mm and voltages in the range of few tens of volts, need to dissipate efficiently a power density in the range 10 to 100 Wmm -2 , which can easily lead to thermal breakdown of the device. The latter is not surprising, considering that the constituting materials, in particular plastic substrates, are characterized by a very low thermal conductivity, making heat dissipation highly inefficient.
Recently, it was proposed that, for some applications (e.g. switching power converters, pulsed-mode data transfer), this can be circumvented by operating the transistor in pulsed mode, which allowed to reach a record f t of 40 MHz at a bias of 8.6 V in such operation regime. [29] However, fully exploiting the possibilities offered by a high-frequency organic technology requires continuous-mode operation, which in turn requires the adoption of efficient dissipation strategies.
Here we show that a route for the realization of high-frequency OFETs operating at a recordhigh f t of 160 MHz and f t /V of 4 MHz V -1 can be implemented with a combination of scalable laser-based direct-writing techniques and solution-based deposition of organic polymers. We carefully selected a set of solutions to the problems illustrated above that complies with the requirement of a fully mask-less and solution-based process flow: these include laser-based patterning of metallic inks with a micron-scale resolution, the modification of the electrodes with a self-assembled monolayer for the achievement of low contact resistance and the 4 adoption of a substrate with high thermal conductivity. With this result, we prove that operational frequencies in excess of 100 MHz can be achieved with organic transistors.
Moreover, we do not only show a working organic transistor with the highest f t to date and the highest f t /V for continuous operation, but we also demonstrate that a route for the achievement of this performance with scalable, mask-less, solution-based techniques is available, and that the future implementation of cost-and energy-efficient mass manufacturing of highperformance organic electronic applications is credible.

Results
We realized high-frequency OFETs in a bottom-contact, top-gate architecture with the layout schematized in Figure 1a, carefully selecting the architecture, materials and processes in order to overcome a variety of limitations to high-frequency operation.
Our fabrication process relies on the flow illustrated in Figure 1b. We selected femtosecondlaser sintering as a direct-writing patterning technique for the realization of micron-scale conductive electrodes for OFETs. Such an approach was successfully adopted in the past for the realization of metallic grids [30] and OFETs, [7,31,32] including high-frequency, direct-written and printed OFETs, [27,33] also on plastic substrate. [5] The choice of the proposed fabrication scheme is advantageous for a variety of future implementations into a wide set of applications, by virtue of its digital nature and compatibility with different substrate materials.
However, devices of the kind we realize in this work, when fabricated on plastic, are prone to suffer of thermal runaway or breakdown (described later in the text), due to the significant amount of power density in the channel region of the device and to the limited thermal dissipation properties of plastics (commonly exhibiting thermal conductivity in the range 0.1 -0.5 Wm -1 K -1 ). To comply with the need for efficient thermal dissipation of such generated heat, we adopted here a highly thermally-conductive substrate of aluminum nitride (AlN), exhibiting a thermal conductivity in the order of 170 Wm -1 K -1 .

5
To fabricate our OFETs we first coat our substrate with an Ag-nanoparticle ink, then we locally induce the agglomeration of the metal nanoparticles into conductive structures via laser sintering. [5] Then, the unprocessed part of the ink is washed out with an organic solvent, leaving high-resolution conductive patterns with a thickness of 70 nm on the substrate. These structures will constitute the source and drain electrodes of the realized OFETs, yielding a channel length L = 1.2 µm, a channel width W = 800 µm, an electrode width L c = 1.7 µm. To promote an efficient charge injection from such electrodes into the semiconductor, we then induce the self-assembly of a monolayer of dimethylamino(benzenethiol) (DABT) on the surface of the metallic patterns. [34] Then, we adopt the widely-studied and good electron which in turn yields the formation of a layer of aligned polymer nanofibrils. [35,36] We then adopted a bilayer dielectric: we first deposit a 40-nm-thick layer of polystyrene blended with an azide-based crosslinker (1,11-Diazido-3,6,9-trioxaundecane) and we cross-link such layer via UV-light exposure at a wavelength of 256 nm. On top of the polystyrene interlayer, we spin-coat a 300-nm-thick layer of poly(vinyl cinnamate), which is then analogously photocrosslinked. The complete dielectric bilayer exhibits an areal capacitance C diel = 8.54 nF cm -2 , calculated using the literature value of 3.4 for the dielectric constant of poly(vinyl cinnamate) and a value of 2.6 for cross-linked polystyrene (determined from our measurements on capacitor devices). The top gate electrode is then realized via laser sintering in correspondence of the transistor channel, keeping the overlap with source and drain electrodes low, to comply with the need of reducing the overlap capacitive parasitism. This is the first time laser sintering [31] is used for the fabrication of gate electrodes on polymer dielectrics in top-gate structures. Encapsulation of the device to prevent degradation induced by the exposure to the ambient environment concludes the fabrication; further details are reported in the Supporting Information.
A top-view representation of the final device is shown in Figure 1c alongside with a magnified micrograph of the active region of the transistor, which highlights the fine alignment between the top gate electrode and the channel area. We confirmed such alignment, associated with a low capacitive parasitism, with cross-sectional SEM imaging of the device (Figure 1c), which allows to estimate the size of the geometrical overlap between electrodes in the range ∼ 0-250 nm ( Figure S1).
We measured the DC transfer (Figure 2a) and output characteristics ( Figure S3) of our transistors, verifying a correct operation up to a bias voltage of 40 V, with a maximum gate leakage current in the order of the nA, with respect to a channel current in the order of few mA. This proves that laser processing on top of a multilayer stack of organic materials, including a semiconductor and a dielectric, is compatible with the fine patterning of highresolution conductive electrodes without damage to the underlying materials.
We then highlight how the integration of a substrate with a high thermal conductivity in our process allows ideal DC operation of the device and prevents the thermal breakdown. In particular, in the case of OFETs with the same architecture and comparable fabrication process, realized on a glass substrate (which exhibits a lower thermal conductivity in the order of 1 Wm -1 K -1 ), when the generated power per unit area approaches the range 20-30 W mm -2 , the devices start to suffer from thermal degradation, the current driven by the device saturates/ drops with respect to the increase of the gate voltage and severe hysteresis appears in the transfer curve ( Figure S4). Contrarily, for the devices of this work, even at the bias point corresponding to the maximum generated power per unit area P th (I d = 2.18 mA, V d = 40 V and P th = 90 W mm -2 ), correct operation of the device is preserved and no signs of thermal degradation are visible.
We calculated the apparent charge mobility of our devices in the linear (µ lin ) and saturation regimes (µ sat ) versus gate voltage (Figure 2b). The ideality of the DC operation of the transistors is confirmed by the flatness of the curves in the fully accumulated regime above 10 V, with a slight roll-off that can be attributed to some residual impact of the contact resistance. The maximum values for the apparent charge mobility are µ lin = 0.22 cm 2 V -1 s -1 and µ sat = 0.62 cm 2 V -1 s -1 . We extracted the width-normalized contact resistance R c W and the intrinsic charge mobility µ i of our devices, which we estimate to be R c W = 300 Ωcm and µ i = 1 cm 2 V -1 s -1 in the saturation regime at a bias point of V g = V d = 40 V (see Supplementary Information for details). Such a value of R c is not only a key requirement in order to access frequency regimes in excess of 100 MHz, [15,19] but is among the best reported values for OFETs in general and is extremely low when considering the case of transistors realized via direct-writing, solution-based methods and optimized for low geometrical overlap of electrodes and high frequency operation. [37][38][39] We then measured the AC characteristics of our device by means of S-parameters, using a setup already described in our previous work, [27] calibrated with a SOLT procedure and corrected with a 12-term error model. From the measured S-parameters, the parasitic contributions of the pads and interconnections are de-embedded from the measurement with a one-step procedure [40] and the hybrid parameter h 21 is extracted (Figure 2c As a crosscheck of the consistency of the AC performance, we extracted the values for the gate/drain and gate/source capacitances C gd and C gs for V g = V d = 40 V, alongside with the 8 total gate capacitance C g = C gd + C gs ( Figure S5). The total gate capacitance, at a first order, can be estimated as follows: where L ov is the geometrical overlap between gate and source (or drain) electrode and 2d, for low-overlap structures of the kind presented here, accounts for the contribution of the fringing field in the form of an "equivalent overlap length", equal to the thickness of the dielectric d. [15] According to this formula, and with L ov in the range 0-250 nm, the total gate capacitance C g can be estimated to be in the range 101 -135 fF, which is in good agreement with the value extracted from our measurement (140 -150 fF above 30 MHz, Figure S5). The transconductance and output resistance can be estimated from the DC curves respectively as  Figure S6). In addition, we verified that g m is not altered by the de-embedding procedure, confirming the consistency of the obtained results ( Figure S6).
The measured f t can be compared to the theoretical value estimated from the transistor DC electrical parameters and geometrical dimensions, according to: With the range of values for C g calculated above and with the range of values for g m extracted from DC, the theoretical f t is calculated to be in the range ~ 140 -180 MHz, which is consistent with our measured value. By including our additional analysis on the contact resistance (see Supplementary Information), the measured f t can also be related to the value predicted by more refined theoretical models in recent reports, [15,19] which include not only the effects of the fringing electric field for low-overlap structures (already accounted for by Equation (1)) but also the effects associated with charge injection physics in staggered OFETs with small electrode overlap. The application of such model consistently returns, for the parameters of the transistors of this work, a predicted f t in the range 138-146 MHz (see Supplementary Information), which is not dissimilar to our measured result.
Overall, high-frequency operation at 160 MHz of solution-processed OFETs is demonstrated via an S-parameter measurement and further validated by the agreement of the extracted transistor small-signal AC parameters with the ones calculated through physical and geometrical considerations. This experimental demonstration agrees with and complements the theoretical roadmaps described in recent works. [15,19]

Discussion
Contrarily to the widespread assumption that organic electronics is relegated to very low- The OFET AC performance demonstrated in this work was achieved both by devising a set of strategies to overcome the bottlenecks to high-frequency operation and by combining them into a fabrication scheme solely using scalable techniques. First, the high patterning resolution necessary both to downscale the transistor dimensions and to contain the capacitive parasitism has been achieved by using laser sintering, which allowed the fine alignment of micron-sized electrodes via direct writing. Second, the charge injection from the contacts, which must be very efficient for downscaled architectures with low overlap between gate and bottom electrodes, has been promoted by inducing the self-assembly of an amine-based monolayer.
This approach allowed to achieve width-normalized contact resistance R c W = 300 Ωcm, which is among the best reported values for solution-processed, direct-written OFETs in general. This achievement is further reinforced by the fact that it is associated with an architecture optimized for high-frequency operation, whose low electrode overlap is wellknown to be detrimental for charge injection. Third, thermal breakdown/degradation has been avoided by using an appropriate thermally-conductive substrate. The latter result highlights an unprecedented need for substrate materials for OFETs, combining flexibility and sufficient thermal conductivity, thus indicating a clear path to be further pursued in future. [41][42][43][44] In conclusion, we have demonstrated that high-frequency operation in excess of 100 MHz is accessible to organic-based electronics. The result we show here represents a suitable complement and a validation to a set of recent reports that theoretically detailed a feasible roadmap towards high-frequency operation or organic transistors. [15,19] Within the roadmap detailed in such works, our achievement of a R c W of 300 Ωcm in high-frequency devices based on printed polymers constitutes one of the key enablers.
These achievements challenge the conventional, well-known tradeoff between the higher electrical performances of inorganic materials (e.g. silicon, metal-oxides, carbon nanotubes) with the advantageous mechanical properties and the cost-and energy-efficient processability of organics. Our findings, overall, outline a credible route towards the adoption of organics in an expanded set of applications, including remote healthcare, distributed sensing, design and entertainment, requiring the availability of a technology integrating large-area electronics with wireless-communication capabilities, realized via cost-and energy-efficient production schemes.

Experimental Section
For the experimental section, please refer to the Supporting Information.  al. [1] Then, we coated the Ag-nanoparticle ink onto these substrates via spin-coating at 7000 rpm for 5 min. Then, we patterned the source and drain bottom electrodes through laser sintering using the setup and following the procedures illustrated in our previous work. [2] In this case, the incident laser power was 17.2 mW at a scanning speed of 0.05 mm s -1 . The unprocessed part of the ink was removed by thorough rinsing with o-xylene. Then, Ar-plasma is applied for 4 minutes at a power of 100 W, and the self-assembly of DABT on the silver electrodes is induced by dipping the samples in a solution of 17 µl DABT in 12 ml of isopropanol for 15 minutes. The samples are then rinsed with isopropanol. The semiconductor layer is then deposited via off-centered spin-coating [3] (in nitrogen atmosphere) of a 7 g/l solution of P(NDI2OD-T2) in toluene, at a speed of 1000 rpm for 30 s. The samples are then annealed at 100 °C for 15 minutes. After cooling, a 40-nm-thick layer of polystyrene, mixed 1 with 1,11-Diazido-3,6,9-trioxaundecane at a weight ratio of 10:1, is deposited via spin-coating at a speed of 1500 rpm for 5 minutes from a solution in n-butyl acetate at a concentration of 7.5 g/l. Then, we spin-coated a solution of 50 g/l poly(vinyl cinnamate) in cyclopentanone at a speed of 1500 rpm for 2 minutes, so to yield a 300-nm-thick layer, which is then cross-linked analogously to the underlying layer. We then patterned the gate electrodes via laser sintering with the same procedure as illustrated above, using an incident power in the range 4. Analyzer. The AC measurement was performed in ambient atmosphere using a setup and calibration method already described previously. [1] The parasitism attributed to the measurement pads and interconnections has been removed by measuring an open structure with a geometry identical to the interconnections used for the transistor measurement. [1] Supporting

Extraction of the contact resistance
In the saturation regime, which is the case of interest here, only the contact resistance at source side matters (provided that voltage drop on the contact resistance at drain side is low enough to maintain the transistor in saturation [10] ).
In the framework of the current crowding model, suitable for staggered transistors, contact resistances can be expressed as: Where: L ov is the gate-contact overlap; R y is the resistance per unit area taking into account injection and transport across the bulk; L 0 = √ R y /R sh is the injection length, viz. the characteristic length over which injection would take place for very large L ov , R sh being the channel sheet resistance. Modelling the carrier mobility as a power law, For the case of very small L ov , which is the case of interest here (actually for L ov < L 0 , to be verified a posteriori), Equation (1) can be simplified as the sum of a constant term and of a V G -dependent term, as it follows [11] : where the first term accounts for injection and transport across the film, whereas the second term accounts for transport along the film at the semiconductor/insulator interface.
The challenge in the saturation regime is due to the fact that the current voltage relationship incorporating the effects of contact resistance is actually an implicit function, without the possibility of writing current as an explicit function of V G in the general case: where V T is the threshold voltage. There are 5 unknowns in Equation (3):  0 , , V T , R c, const , L ov , (R c, var can be expressed as a function of  0 , , V T , L ov ). To extract them from experimental data, we devise an iterative fitting algorithm. In addition, to ease the procedure and reduce the number of fitting parameters, we select reasonable ranges for µ 0 and V T , and for each (µ 0 , V T ) couple we run the following algorithm.
The parameter γ is initialized at 0.01.
1. Since  0 and V T are fixed and  is initialized (or fitted, vide infra), we can calculate V G , the base which is raised to (γ + 2) in Equation (3): 2. Now we take advantage of the fact that: V G and I are experimentally measured;  0 and V T are fixed. We plot V G −V T − R C I versus V G and, exploiting Equation (2), we fit R c,const , L ov and γ, with the constraint γ > 0. The fitting is done in the range 23 V < V G < 40 V.
3. With the value for γ estimated at step 2, we jump to step 1 and reiterate for 100 cycles.
We sometimes experienced oscillations in the fitted value for  between 0 and a certain γ .
Indeed, for consistent and realistic fitted parameters, γ is very close to 0 (actually smaller than 0.043), therefore the impact of such oscillation is negligible. In these cases, to proceed with the analysis, we arbitrarily chose γ=γ 2 and we run a final direct fit of R c , determining R c,const and L OV . Later, we verified that different choices for γ (i.e. γ=γ 4 or γ= 3 4γ ) did not appreciably change the results of the fitting.
The parameters γ, R c,const and L ov extracted with µ 0 in the range 0.94 -1.1 cm 2 /Vs and V T in the range 5.9-6.2 V are shown below in Table S2. From the independent measurement of the geometrical overlap between electrodes and of the dielectric thickness, within the framework 8 of the gate capacitance model illustrated in the main text, [12] we identify the acceptable values for L ov (i.e. 0.34 µm < L ov < 0.61 µm) and we highlight the corresponding combinations in red in Table S2. In order to evaluate the goodness of the fitting resulting from the algorithm outlined above, we define as a figure of merit the quantity err, with the aim of weighting the goodness of fitting for both the current and the contact resistance:

1.
We calculate the quantity er r I = ∑ We calculate the quantity er r R c = ∑

3.
We define er r =er r R c + er r I 9 The set of calculated quantities err for each combination of parameters  0 and V t is presented In Table S3, where the acceptable values are highlighted in red with the same criterion as Table S2 above. The best fittings of the experimental data curves when combined with the constraints on the acceptable range of L ov are identified for V T = 6.1 V and 1.02 cm 2 /Vs < μ 0 < 1.08 cm 2 /Vs ( Figure S7): indeed, the range for μ 0 ~ 1 cm 2 /Vs is consistent with independent reports for the adopted semiconducting polymer P(NDI2OD-T2) [10] and the range for V T is reasonable and consistent with the measured transfer curves for our devices. In addition we verified that the injection length L 0 is larger than L ov , as needed for equation (2) to hold (indeed Equation (2) is a very good approximation of Equation (1) already starting from L ov = L 0 , where the relative error is as low as 1.54%). [11] Figure S7: Experimental data and fitted curves as a result of our algorithm, for the combinations corresponding to V T = 6.1 V and a) μ 0 = 1.02 cm 2 /Vs, b) μ 0 = 1.04 cm 2 /Vs, c) μ 0 = 1.06 cm 2 /Vs, d) μ 0 = 1.08 cm 2 /Vs.

Consistence of R c W with the theoretical predictions for f t
The experimental values reported here for f t can be analyzed in the frame of a recently reported theoretical roadmap for high-frequency operation of organics. [12] With the model of that work, we express: where the parameters are defined analogously to the definitions in the main text, and The contact resistance is described in accordance with the current-crowding model as in Equation (2), and considered as fully insisting on the source electrode.
When plugging in the parameters of the transistors of this work, as determined by the method described in the previous section, we obtain f t ~ 138 -146 MHz, which is consistent with the experimental measurement. We remark that, in the adopted model, the voltage dependence of the mobility on the gate voltage is not accounted for. However, such contribution is effective only at a second order, since γ < 0.043.