Atomic Layer Deposition of Metal Oxides and Chalcogenides for High Performance Transistors

Abstract Atomic layer deposition (ALD) is a deposition technique well‐suited to produce high‐quality thin film materials at the nanoscale for applications in transistors. This review comprehensively describes the latest developments in ALD of metal oxides (MOs) and chalcogenides with tunable bandgaps, compositions, and nanostructures for the fabrication of high‐performance field‐effect transistors. By ALD various n‐type and p‐type MOs, including binary and multinary semiconductors, can be deposited and applied as channel materials, transparent electrodes, or electrode interlayers for improving charge‐transport and switching properties of transistors. On the other hand, MO insulators by ALD are applied as dielectrics or protecting/encapsulating layers for enhancing device performance and stability. Metal chalcogenide semiconductors and their heterostructures made by ALD have shown great promise as novel building blocks to fabricate single channel or heterojunction materials in transistors. By correlating the device performance to the structural and chemical properties of the ALD materials, clear structure–property relations can be proposed, which can help to design better‐performing transistors. Finally, a brief concluding remark on these ALD materials and devices is presented, with insights into upcoming opportunities and challenges for future electronics and integrated applications.


Introduction
Since the first working transistor was demonstrated in the 1940s, transistors have become a fundamental component of modern electronics. Networks of semiconductor transistors form logic gates essential for the function of microprocessors. Apart from this prominent application, transistors are also widely used in electronic/optoelectronic devices and integrated systems such as flat panel displays, electronic skins, artificial synapses, photodetectors, physical or chemical sensors, and biomedical equipment. [1][2][3][4][5][6][7][8][9][10][11] Thus, the application of transistors is ubiquitous within modern digital products.
The basic design of a transistor is composed of three terminals that consist of source (S), drain (D), and gate (G) electrodes. A semiconductor material, also referred to as a channel, contacts the S and D electrodes. A dielectric serves as an insulation layer between the G electrode and the semiconductor layer to electrically isolate the channel. Variation in channel and electrode placement design affords both bottom-gate and top-gate structures, which are two commonly used types of transistors (Figure 1a,b). The channel length (L) of a transistor is defined as the distance between the S and D regions, and the channel width (W) is the total distance across the channel area parallel to the S and D electrodes. Current manufacturing techniques extensively utilize a silicon substrate for transistors in device fabrication of electronic/optoelectronic systems such as processors, communication chips, and image sensors. [12] However, flexible substrates such as polyethylene terephthalate (PET), polyimide (PI), polydimethylsiloxane (PDMS), and biodegradable polymers, show good potential for use within the nextgeneration flexible devices as a part of wearable/stretchable electronics, and future technologies. [9,[13][14][15] Most transistors operate using a model based on electro-magnetic field manipulation. Hence, they are termed field-effect transistors (FETs). [16,17] Application of a voltage between the source and gate of a FET device forms an electric field. This field stimulates the accumulation of charge carriers at the semiconductor/dielectric interface, a process termed capacitive carrier injection. As a result, current flow between S and D electrodes may be modulated according to a gate voltage (V G , or recorded as V GS ). When V G exceeds a threshold voltage (V T ), a conducting channel is established and a source-drain current (I DS ) can be adjusted by controlling a bias across the S and D electrodes (V DS ). Therefore, transistors can facilitate the adjustment of on-/off-state currents by tuning the applied bias voltages, achieving a higher output power than input power. These attributes afford excellent signal conduction, amplification, and switching functions for various applications such as oscillators, photodetectors, and tactile sensors.
The performance of transistors is generally evaluated through charge-transfer and output characteristics measured for calculating important metrics such as the carrier mobility ( ), V T , on/off current ratio (I ON /I OFF ), and subthreshold swing (SS). Output curves are obtained by plotting I DS as a function of V DS whilst a sweeping V G is applied (Figure 1c), while transfer curves are illustrated by plotting I DS as a function of V G at a constant V DS ( Figure 1d). As the V DS applied increases, I DS will continue to increase until the channel current saturates. If V DS is much lower than the applied V G (V DS << V G − V T ), the transistor operates in a linear regime. At this bias condition, I DS increases linearly with V DS and charge accumulation across the channel is considered to be evenly distributed. Thus, the current-voltage relationship can be determined by Equation (1), [18] where C i is the capacitance per unit area of the dielectric, and lin is the field-effect mobility in the linear regime. When V DS is higher than V G − V T , the conducting channel is pinched off, since the free charge density around the drain contact reduces to nearly (but not quite) zero. [19] Under this condition, I DS becomes V DS independent, and the device operates through a saturation regime. Thus, the carrier mobility of the transistor can be calculated by Equation (2), [20] where sat is the mobility in the saturated regime. Transfer curves reflect the conditions of a saturated regime via a plot of I DS 1/2 against V G (Figure 1d). This relationship yields a straight line, where the square of its slope is proportional to the charge carrier mobility. Meanwhile, V T can be obtained by extrapolation to an intercept of the linear part of the I DS 1/2 -V G plot. Considering that the determination of V T is sometimes ambiguous, one can employ V ON as a parameter for describing the V G needed to turn the device on, that is, the potential at which I DS starts to flow because of field-induced charge accumulation at the semiconductor/dielectric interface. [21] The on-state and off-state currents of FETs can be obtained from the transfer characteristics to afford I ON /I OFF , which directly reflects the control of an applied gate bias over the conductive channel. The SS is defined as the inverse of the maximum slope of the logarithmic I DS plot (expressed as V/decade) and can be extracted from a transfer curve based on the relationship from Equation (3). [16] Note that lower SS values lead to higher switching speeds and lower power consumption. Thus, low values of SS (<< 1) are desirable for improving the ratio between on-and off-currents and making the FET more energy efficient. [16,19] Beyond these key parameters, the operating voltages and device stability are also important for practical applications of transistors. FETs based on SiO 2 dielectrics suffer from highoperating voltages with tens or hundreds of volts. This limits application in wearable devices, where safety and low power consumption are important factors for adoption. For example, low voltage (<5 V), flexible FETs have been demonstrated through the incorporation of high-capacitance polyelectrolytes as gate dielectrics. [22][23][24] Semiconductor materials and processing methods largely determine the performance of FETs. Elemental semiconductors such as amorphous silicon (a-Si) and polycrystalline silicon (poly-Si) were commonly employed for FETs in the electronic industry. [1] The development of novel semiconductor materials using inorganic compounds, organic conjugated molecules, quantum dots, and 2D nanomaterials for highperformance FETs such as metal-oxide-semiconductor FETs (MOSFETs), organic FETs (OFETs), quantum dot FETs (QFETs), show promising results for integration within next-generation devices. [19,[25][26][27] Inorganic group-VI (O, S, Se, and Te) materials are recognized as excellent semiconductor candidates for FETs within dedicated applications such as transparent electronics, large-area thin film electronics, active matrix displays, inverters, ring oscillators, and integrated circuits. [16,21,28] Several examples of metal oxides (MOs) and metal chalcogenides (MCs) have attracted remarkable attention in the development of thin-film transistors (TFTs) and emerging applications, [10,[29][30][31] indicating good potential for the development of high performance electronic/optoelectronic devices as well as integrated systems with state-of-the-art silicon electronic and photonic devices.
Beyond innovation of semiconductor materials, research and development of transistors have also been driven by the fast-developing application of fabrication technologies such as solution-processing, thermal evaporation, sputtering, chemical vapor deposition (CVD), atomic layer deposition (ALD), and many others. [42,[48][49][50][51] Table 1 briefly compares the advantages and disadvantages of these different film growth techniques. In particular, ALD is recognized for producing thin-films with good conformality and reproducibility. These attractive features are beneficial for the fabrication of high-quality semiconductor films and dielectric layers in FETs at the nanoscale. [52] An ALD protocol is comprised of a series of self-limiting surface reactions between gaseous precursors at the interface of a solid substrate. [53,54] Alternating pulse and purge sequences of different precursor reactants supplied using an inert carrier gas ensure that only selective self-limiting reactions occur ( Figure  2a). The sequential nature isolates reactants, which greatly enhances control over the chemisorption reaction at surface-active growth sites. In this manner, the film thickness may be tuned according to the number of ALD cycles, affording angstrom level precision. [55] In addition, low growth temperatures and the conformal coating capabilities of ALD make it compatible with a greater variety of flat and curved substrates. [56][57][58][59] The demonstration of ALD in fabricating numerous types of thin-film materials including pure elements, oxides, chalcogenides, carbides, nitrides, and phosphates on various rigid or flexible supports, highlights its adaptability. [60][61][62][63] A variety of bandgap-tunable MO materials have been fabricated using ALD techniques for applications as semiconductor channels, electrodes, and electrode interlayers in TFTs. [64][65][66][67] Further adaptations of ALD have yielded MO insulators integrated as gate dielectrics and encapsulating layers in FETs. [68][69][70] An increased focus on 2D materials for applications within FETs has stimulated further interest in layered materials such as transition metal chalcogenides (TMCs). [28,31,71,72] Furthermore, ALD-fabricated TMC semiconductors have been combined with conventional silicon-based devices to produce hybrid devices, enabling the integration of flexible designs. [73,74] The large variety of semiconductor materials (Figure 2b) fabricated by ALD, indicates its potential as a transistor component manufacturing method. Thus, the integration of Figure 2. a) Schematic illustration of a typical ALD cycle for growing inorganic films. b) Schematic positions of the valence band (VB) and conduction band (CB) relative to the Fermi level (E f ) for MO semiconductors and insulators, and MC semiconductors made by ALD techniques in previous reports. [32][33][34][35][36][37][38][39][40][41][42][43][44][45][46][47] The red dash line indicates the E f . ALD-MOs and MCs within FETs may serve to improve the performance of existing designs, as well as provide complementary and novel properties for next-generation electronic/optoelectronic devices.
In this article, we aim to present recent advances in the transistor-based applications of ALD MOs and MCs. Emphasis is placed on the tunability of materials using ALD, the influence of ALD on the performance optimization of FETs as well as device applications. The review will first explore the application of ALD for various MO materials used as channel, dielectric and encapsulating materials within FETs, as well as electrode and electrode interlayers. The latter section will discuss MC materials as high-performance semiconductors, with a focus on their electrical performance within FETs and possible heterostructure devices. Last, we will conclude with a brief remark on the merits and limits of ALD-MOs/MCs for transistors as well as their opportunities and challenges in future electronics.

ALD of Metal Oxides for FETs
Over the past decades, MOs have gained attention for electronic applications due to their tunable structures, unique properties, and facile processing methods. [14,75] MOs are generally grouped as semiconductors or insulators, according to the differences in band position and bandgaps. [66,76,77] Recently, uniform MO films with precisely controlled thicknesses and adjustable properties were deposited by ALD, [78] which performed promisingly upon integration within FET devices. [79]

Metal Oxide Semiconductors
MO semiconductors, with tunable bandgap values from 1 to 3 eV, are promising transparent channel materials that have attracted great interest in the microelectronics industry. [64,65,80] Binary MO semiconductors deposited by ALD, such as ZnO, [64,81] In 2 O 3 , [65] SnO, [80] and TiO 2 , [82] have exhibited transport and switching properties meeting the prerequisites for applications in FETs. Besides, multinary MO semiconductors such as indium zinc oxide (IZO), [83] and indium gallium zinc oxide (IGZO), [84] can be effectively fabricated by facile modification of existing ALD processes. Compared with binary MOs used for FETs, multinary MO semiconductors have been demonstrated to deliver more attractive device performance, such as higher mobility, better stability, lower leakage current, and smaller SS. [83][84][85] In addition to the success of n-type MO semiconductors, p-type MO materials such as SnO, CuO, and Cu 2 O as well as emerging alternatives, are also involved in this review due to their significant roles in new-generation electronics. Table 2 summarizes key electrical performance Reproduced with permission. [115] Copyright 2020, Elsevier.
parameters of some representative FETs based on various MO semiconductors fabricated using ALD under different conditions.

Zinc Oxide
Due to a wide-bandgap of 3.37 eV, zinc oxide (ZnO) is a promising transparent oxide semiconductor and attracts great attention for applications in solar cells and TFTs. [103,104] ZnO-based TFTs exhibit notable performance characteristics such as a high I ON /I OFF ratio of 10 8 and a mobility of 80 cm 2 V −1 s −1 . [86,[105][106][107] Synthesis of ZnO by ALD commonly uses diethyl zinc (DEZ) as a precursor. [87,108] ALD-fabricated ZnO films deposited at a low reaction temperature (80 to 250°C), exhibit excellent I ON /I OFF (10 9 ) and mobility (50 cm 2 V −1 s −1 ) metrics. [86,109] However, deposition temperature greatly influences the electrical properties of ALD-ZnO films. [110] Mobility decreases at low deposition temperatures, in contrast, the I ON /I OFF increases. [109] High deposition temperatures can generate greater numbers of defects such as oxygen vacancies, resulting in increased carrier mobility of ALD-ZnO. [111] Correspondingly, oxide film defects resulting from low temperatures can be passivated by O-H species, which will reduce the mobility, but increase the I ON /I OFF . [112] Generally, ALD-ZnO films fabricated using higher deposition temperatures exhibit higher carrier concentrations (≥10 19 ), much higher than the appropriate carrier concentration of ≈10 14 -10 17 for the traditional MO channel layer. [111] It was reported that post-annealing in an oxygen atmosphere could efficiently reduce the carrier concentration, thus obtaining high-quality ZnO films with appropriate semiconductorrelated properties. [113,114] For instance, the electrical performance of ALD-ZnO films deposited at a relatively high temperature (≈200-250°C), is improved by a post-annealing at 300°C in O 2 . [110] The annealed ZnO films exhibit similar transfer characteristics as films fabricated at lower temperatures. Besides the high-temperature-deposited films, Bang et al. also improved the electrical performance of low-temperature-deposited ZnO films via higher temperature post-annealing treatment. [114] The ALD-ZnO film deposited at 100°C using DEZ, showed good device performance with a mobility of 1.2 cm 2 V −1 s −1 and an I ON /I OFF of 3.1 × 10 6 , which can be further improved to 1.8 cm 2 V −1 s −1 and 1.7 × 10 7 , respectively, after post-annealing the ALD-ZnO film at 250°C in ambient air. As a consequence, the SS decreased from 0.53 to 0.34 V dec −1 . The enhanced electrical performance of ZnO transistors can be attributed to the formation of a Znrich phase between the semiconductor layer and the metal electrode during the post-annealing treatment, which may increase the carrier concentration at the metal/semiconductor interface and decrease the contact resistance. Higher annealing temperatures cause faster diffusion of metal atoms, resulting in a rougher interface. Thus, the highly conducting Zn-rich phase may alter the length of the semiconducting channel.
In addition to the deposition temperature, oxygen source is another critical factor that affects the quality of ALD-ZnO films. Strong oxidants such as O 3 yield smaller average grain sizes in comparison to H 2 O in application with DEZ (Figure 3a,b). [115] X-ray diffraction (XRD) analysis shows additional changes in the preferred grain orientation of ZnO film, indicating the tunability of growth direction according to oxidant selection (Figure 3c). The two ALD-ZnO films and their bilayer structure can be employed as n-type channels in TFTs (Figure 3d). Analysis of their individual transfer curves clearly indicates that the O 3derived ZnO film shows better electrical performance than the H 2 O-derived ZnO film ( Figure 3e). Moreover, by using the H 2 Oderived ZnO interlayer to decrease the interfacial trap density, the resulting bilayer ALD-ZnO channel shows improved electrical performance relative to the single layer channel (Figure 3e-h).  [88]. The inset is a photograph of the ZnO TFTs on a 3.5 μm PI substrate folded with a bending radius of ≤ 500 μm. b) Transfer curves of the corresponding device before (black) and after (red) folding. c) Output waveform of the flexible TFT oscillator based on ALD-ZnO on the PI substrate. Reproduced with permission. [88] Copyright 2016, Wiley VCH. d) Optical image of printed inverter with a schematic logic circuit. e) Device structure of the printed TFTs. f) Output waveform of the fabricated five-stage ring oscillator with an input voltage of 20 V (the inset shows a layout of the fabricated devices). Reproduced with permission. [81] Copyright 2015, American Chemistry Society.
Upon increase to the interlayer thickness, the SS of the TFTs decreases while the mobility increases significantly. However, when its thickness exceeds 7 nm, the electrical performance starts to degrade again (Figure 3g-h). As result, the optimized bilayer ALD-ZnO TFTs deliver a highly improved mobility of 31.1 cm 2 V −1 s −1 with a low V T of 0.14 V, a large I ON /I OFF of 10 8 , a small SS of 0.21 V dec −1 , and a good positive bias stress stability.
Assisted by the generation of oxygen vacancies, ALD-ZnO films are considered intrinsic n-type semiconductors. However, Guziewicz et al. has demonstrated successfully the deposition of p-type ZnO semiconductors through in situ nitrogen doping. [86] During the ALD process, an ammonia water solution was used as an oxygen source instead of pure water or oxygen, and the film was annealed briefly in a nitrogen atmosphere after deposition. As a result, the N-doped ZnO exhibited a p-type characteristic with a Hall carrier concentration of ≈10 18 cm −3 . Moreover, a pn homojunction was demonstrated by depositing an n-type ZnO layer onto the p-type ZnO, showing an I ON /I OFF close to 10 5 .
ALD-ZnO also shows good potential for application within transparent and flexible electronics because of its high transmittance and low-temperature processing requirements. [87,103] For instance, ZnO-based transparent TFTs with good optical transmission in the visible range were successfully fabricated using ALD on transparent glass substrates at a temperature below 100°C. [103] Separated by a dielectric of ALD-Al 2 O 3 /HfO 2 /Al 2 O 3 , the ALD-ZnO film acted as both a channel material and a gate electrode. Flexible TFTs using the ALD-ZnO channel and TiO 2 /Al 2 O 3 passivated layers were also achieved on plastics at low temperatures. [87,88] The flexible ALD-ZnO TFTs showed out-standing electrical performance with electron mobility of ≈17 cm 2 V −1 s −1 , an I ON /I OFF of 10 5 , and a SS of 0.4 V dec −1 . [87] With the use of plasma-enhanced ALD (PEALD), flexible ZnObased TFTs have been fabricated via the deposition of ZnO thinfilms onto PI substrates. [88] The TFTs deposited on a 3.5 μm flexible PI substrate exhibit comparable electron mobility (1.3 ± 1.2 cm 2 V −1 s −1 ) and V T (2.2 ± 0.3 V) values to those of TFTs on a glass substrate (Figure 4a). Investigation of device performance before and after fold-induced mechanical stress (Figure 4b), shows a negligible degradation of mobility and V T . The practical application of ZnO-based TFTs was further demonstrated using a crosscoupled LC oscillator circuit, with the flexible PI substrate outperforming analogous TFTs deposited onto glass. Using a V supply of 9 V, the oscillation frequency (f OSC ) measured 17 MHz (Figure 4c), well above the cutoff frequency (f T ) for operation on glass substrates (12.9 MHz).
Printed inverters using ZnO-based TFTs ( Figure 4d) were prepared using a modified version of ALD, which applies spatial isolation techniques to achieve ALD (SALD). [81] The fabricated TFTs (Figure 4e) exhibited excellent electrical performance with high mobility (15 cm 2 V −1 s −1 ). Furthermore, inverters arranged within a five-stage, enhancement-mode ring oscillator architecture displayed a frequency response of 2.68 kHz at an input voltage of 20 V (Figure 4f). In conclusion, the tunable nature of ALD has afforded ZnO semiconductors with strong electrical performance upon integration within TFTs. Its compatibility with flexible substrates, along with its performance within integrated circuits, reflects its promise for use within more complex device architectures.

Indium Oxide
Investigation into heavier MOs has demonstrated that indium oxide (In 2 O 3 ) possesses excellent properties as a wide bandgap (≈3.6 eV) semiconducting/conducting material. [65,116] Deposition of In 2 O 3 using low-temperature ALD yields highly optically transparent (>85%) films, which perform moderately well according to mobility (15 cm 2 V −1 s −1 ) and V T (≈−0.2 V) metrics. [116] Films grown using PEALD with the precursor diethyl[bis(trimethylsilyl)amido]indium [Et 2 InN(SiMe 3 ) 2 ] and O 2 plasma (100-250°C) resulted in polycrystalline In 2 O 3 , which upon the application within a TFT displayed a significantly better mobility (39.2 cm 2 V −1 s −1 ). [89] The low voltage threshold and high mobility suggest ALD-In 2 O 3 is an extremely promising candidate for transparent TFT-containing devices. [117] However, In 2 O 3 films grown at low temperatures typically form non-stoichiometric amorphous films with carrier concentrations analogous to metal-like materials, likely resulting from excess oxygen vacancy site formation. [79] Simulations applying density functional theory (DFT) suggest increasing the order within In 2 O 3 thin films and consequently, the stoichiometric nature of the film leads to an attenuation in the metal-like conductivity. [118] These findings are also supported experimentally. Transmission electron microscopy (TEM) analysis indicates that as-deposited amorphous In 2 O 3 undergoes transformation upon post-deposition annealing at 300°C within an oxygen atmosphere, resulting in crystalline In 2 O 3 . [65] The annealed In 2 O 3 films exhibited improved electrical performance within TFT devices. The mobility was increased from 20.12 to 41.8 cm 2 V −1 s −1 , the SS was decreased from 400 to 100 mV dec −1 , and the V T was reduced from −6.7 V to −0.8 V.
In another study, amorphous InO x deposited at 150°C was post-treated with N 2 O plasma under different exposure times (600-2400 s) to investigate the effects on device performance ( Figure 5). [79] Prolonged plasma exposure leads to an increase in roughness of the InO x surface and a considerable decrease in O-deficiency ( Figure 5g). The TFTs made by using the plasmatreated InO x films transit from a metal-like conductor to a semiconducting device. The switching performances such as the I ON /I OFF are greatly improved with an increase in the plasma time ( Figure 5d). The low-temperature approach enabled further investigation into flexible ALD-InO x TFTs through deposition on a PI substrate (Figure 5a). Repetitive bending tests were carried out to evaluate the electrical performance of the flexible TFTs with two different bending axes, along the channel length (case I, Figure 5b) and along the channel width (case II, Figure 5c), respectively. For case I, the V T shifts gradually in a negative direction after 3000 bending cycles, whilst the mobility and SS exhibit only slight changes (Figure 5e,h). However, more dramatic changes were measured for case II. After 700 bending cycles, the mobility and V T decrease dramatically, while the SS increases drastically (Figure 5f,i). These results suggest that ALD-fabricated InO x films may be suitable for integration within flexible TFT devices. However, the TFT architecture influences durability significantly. Furthermore, both methods demonstrating stoichiometric enrichment of amorphous InO x utilize oxygen enrichment post-processing techniques at significantly different temperatures, suggesting the barrier of formation for In 2 O 3 is kinetic in nature. Further mechanism investigation may assist in supporting this correlation as well as assisting in the optimization of future ALD protocols.

Tin Oxides
Tin dioxide (SnO 2 ), a wide bandgap (≈3.6 eV) n-type semiconductor, exhibits excellent electrical properties such as large electron mobilities (≤147 cm 2 V −1 s −1 ) and high I ON /I OFF ratios (10 7 ). [75,[119][120][121] Deposition of high-quality SnO 2 films may be achieved using a range of tin precursors such as TDMASn, [66,122] dimethylamino-2-methyl-2-propoxy-tin(II) [Sn(dmamp) 2 ], [92] and tetrakis-(dimethylamino)propyl tin(IV) [Sn(DMP) 4 ]. [75] SnO 2 films deposited using Sn(DMP) 4 and oxygen plasma at low temperatures (60°C) feature small hillocks (a low surface roughness value of 0.22 nm, Figure 6a). [75] Evaluation of transfer characteristics within bottom-gate TFTs indicates that the film thickness greatly influences mobility and V T (Figure 6b,c). In thicker layers, the bulk SnO 2 remains in a non-depleted state, causing parallel conduction. In comparison, thin films suffer from surface roughness scattering. However, at an optimized film thickness (6 nm), the TFTs display typical n-type output and transfer characteristics (Figure 6d,e), yielding an electron mobility of 12 cm 2 V −1 s −1 and an I ON /I OFF of 10 7 . The deposition temperature of ALD-SnO 2 has also been demonstrated to influence electrical performance. [92] Improvements in channel mobility (2.31 to 6.24 cm 2 V −1 s −1 ) and V T (7.47 to 1.88 V) are observed upon increasing deposition temperature (70 to 130°C). Above 130°C, carrier concentration increases in tandem with a decrease in resistivity (Figure 6f), resulting in conductor characteristics. By contrast, room-temperature ALD-SnO 2 using tetramethyltin [Sn(CH 3 ) 4 ] and plasma-excited humidified argon, can also be used as a channel material to display n-type behaviors but with pretty low mobility (8.23 × 10 −5 cm 2 V −1 s −1 ). [91] Differing from SnO 2 , tin monoxide (SnO) behaves as a p-type semiconductor with a wide bandgap (≈3.0 eV) and offers a moderate field-effect mobility (≈6.75 cm 2 V −1 s −1 ). [123,124] Although a variety of studies on tin oxides synthesized by ALD have been reported, it is still a challenge to obtain high-quality p-type SnO films. [80,93] Han et al. demonstrated tunability of Sn/O film composition through the use of different oxygen-containing co-reactants. [123] Reactions using a strong oxidant such as O 3 or O 2 plasma yielded n-type SnO 2 films, whilst H 2 O afforded SnO films. Deposition temperature also influenced morphology with higher temperatures (150-210°C) resulting in greater SnO crystallinity and corresponding improvements to the electrical performance of ALD-SnO TFTs (Figure 7a,b). [93] The increased I ON /I OFF is mainly attributed to effective reduction of extrinsic hole concentrations in the SnO films, while the improved mobility may result from the increased grain size of ALD-SnO films grown at relatively high temperatures. Optimization of TFT channel thickness using ALD demonstrated further improvements in TFT performance ( Figure 7c). The optimized ALD-SnO TFTs exhibited interesting electrical performance with a hole mobility of ≈1 cm 2 V −1 s −1 , an I ON /I OFF of 2 × 10 6 , and a SS of 1.8 V dec −1 . Diffusion of Sn(IV) into the SiO 2 insulator layer forms trap sites during both ALD and post-annealing, leading to poor device Reproduced with permission. [79] Copyright 2016, American Chemistry Society Figure 6. a) Atomic force microscope (AFM) images of an ALD-SnO 2 film deposited at 60°C. b) Transfer characteristics of SnO 2 -TFTs with different thicknesses of the ALD-SnO 2 channel. c) Thickness-dependent mobility (red) and V T (blue) of the ALD-SnO 2 TFTs. d) Output and e) transfer curves of the optimized TFT based on ALD-SnO 2 (6 nm) at different applied voltages. Reproduced with permission. [75] Copyright 2019, American Chemistry Society. f) Change in the carrier concentration (red) and resistivity (blue) of ALD-SnO 2 with deposition temperatures. Reproduced with permission. [92] Copyright 2012, Elsevier.
performance. Adoption of an insulating Al 2 O 3 interfacial layer (IL) between the SiO 2 gate dielectric and ALD-SnO channel layer reduces trap site density (Figure 7d,e). [80] Comparison of Al 2 O 3 IL thickness (Figure 7f-i) highlights the effects of ILs upon hysteresis voltage (V hy ), with significant attenuation of V hy observed at 5 nm. Further optimization of the Al 2 O 3 IL afforded a V hy of 0.2 V, a mobility of 1.6 cm 2 V −1 s −1 , and an I ON /I OFF of 1.2 × 10 5 .
In short, both SnO 2 and SnO films made by ALD show good potential as semiconductor channel materials in FETs for promising applications in transparent and flexible electronics. The adaptability of ALD protocols also highlights its capacity to optimize tin oxide thin films for electronic applications. Finally, combining p-type and n-type tin oxides to construct p-n junctions, inverters or other complex structures by ALD will also be a promising and significant direction toward advanced electronics in the future.

Other Binary Metal Oxides
Semiconducting titanium oxide (TiO 2 ) has also attracted extensive interest in the field of FETs due to its high transparency, good stability, and low-cost growth process. [82,109,125] Excellent electri-cal performance characteristics, such as a high field-effect mobility of ≈10 cm 2 V −1 s −1 , attribute further to the use of TiO 2 as a promising channel material. [126] Early reports revealed that high-quality TiO 2 films fabricated by ALD can be applied as channel materials in FETs. [82,127] Ali et al. demonstrated TFT applications of TiO 2 using thermal ALD in conjunction with post-annealing. [96] The annealed TiO 2 film exhibited efficient electronic performance, with electron mobility of 0.672 cm 2 V −1 s −1 , an I ON /I OFF of 2.5 × 10 6 , and a SS of 350 mV dec −1 . Although TiO 2 is typically considered as an ntype semiconductor material owing to oxygen vacancies, [109] ptype behavior has also been demonstrated. Application of epitaxial growth mechanisms using ALD in combination with a [001] oriented Al 2 O 3 substrate, can afford p-type TiO 2 (anatase) thin films. [127] Furthermore, variation in post-annealing conditions demonstrated that TiO 2 may be natively p-type and hole mobility may be further enhanced through titanium deficiencies. [82] Copper oxide (CuO) and cuprous oxide (Cu 2 O), another family of promising binary oxide channel materials, likewise show p-type behaviors and comparable electrical performance in electronic applications. [94,95] The influence of post-annealing temperatures on the optical, electrical, and chemical properties of ALD-CuO x films deposited at 100°C, were recently investigated by Maeng et al. [94] Spectroscopic ellipsometry and X-Ray photoelectron spectroscopy were used to distinguish the relationship between the optical bandgap and annealing temperature of the deposited films (Figure 8a,b). The band edge position of ALD-CuO x films with controlled energy levels clearly relies on annealing temperatures. The as-deposited ALD-CuO x film has an optical bandgap of ≈2.17 eV which then decreases to 2.08, 1.47, 1.43, and 1.43 eV according to the annealing temperatures of 200, 300, 400, and 500°C, respectively. The electrical properties of the ALD-CuO x films were evaluated via TFT devices, revealing typical ptype transfer characteristics (Figure 8c). The as-deposited CuO x exhibits a low I ON /I OFF in addition to a high SS (Figure 8d), which may be attributed to poor stoichiometry at lower temperatures resulting in greater conducting behavior. The higher temperatures used during the annealing process enhance stoichiometry and thus crystallinity, leading to better semiconductor performance output. As a result, the optimized TFTs using ALD-CuO x film annealed at 300°C showed overall improvement in electrical performance, such as the increased hole mobility and I ON /I OFF of 5.64 cm 2 V −1 s −1 and 10 5 , respectively. However, the formation of grain boundaries at 500°C hinders the carrier transport, suppressing further enhancements in TFT performance achieved using post-deposition annealing. Compared with typical p-type CuO and Cu 2 O, some emerging metal halide semiconductors, such as p-type cuprous halides (i.e., CuBr, CuI, and Zn-doped CuI) and metal halide perovskites, can deliver better device performance of FETs. [128][129][130][131][132][133][134] In particular, a very recent report by Liu and Noh et al. presented p-channel perovskite FETs based on cesium tin triiodide (CsSnI 3 ).The resultant FETs exhibited large field-effect hole mobilities (>50 cm 2 V −1 s −1 ), high I ON /I OFF ratios of 10 8 , and excellent operational stability, demonstrating their promising potential for advanced electronics. [134] Currently, there are several reports on the ALD of metal halides. [135,136] However, these ALD-metal halides are isolated nanoparticles and evaluations of their semiconductor characteristics are not reported. Therefore, the research emphasis on high-quality ALD p-type semiconductors should not be limited to MOs. Metal halides and other inorganic hybrid materials are also promising avenues for exploration. The atomic layer control afforded by ALD is highly advantageous for the further development of conventional and emerging p-type semiconductor channels and may yield new high-performance transistors for electronic/optoelectronic applications.

Multinary Metal Oxides
Multinary MOs such as IZO and amorphous indium gallium zinc oxide (a-IGZO) are emerging as novel semiconductor materials for TFTs due to their flexible compositions and excellent electrical properties in contrast to conventional binary MOs. [83,84] The influence of elemental composition on the electrical properties of multi-metal semiconductors has been well established within literatures. [84,85] For example, minor compositional alteration of a-IGZO from In 0. 45 [85] In this respect, ALD affords facile tunability of metal precursor ratios; it enables the fabrication of multinary MOs in a precise manner. A unique approach accessible only using ALD applies the standard half-reaction protocol, but includes an additional separate half-reaction with a different metal precursor during the growth cycle. [97] For example, alternating bilayers of In 2 O 3 and ZnO were deposited according to a fixed ratio of 0.6 (6:4 half-reactions per cycle, respectively), resulting in a pseudomultinary semiconducting heterostructure. [137] Furthermore, selective deposition of the initial In 2 O 3 layer onto the dielectric interface significantly improves TFT performance in comparison to a reverse ZnO-first architecture. Indeed with field-effect mobility (1.07 to 6.5 cm 2 V −1 s −1 ), and I ON /I OFF (5.2 × 10 6 to 5.0 × 10 7 ) are greatly improved whilst V T (10 to 8.9 V) and SS (1.85 to 0.7 V dec −1 ) are deteriorated. In another study, Illiberi and coworkers deposited IZO using spatial-ALD at atmospheric pressure. [83] The ratio of indium/zinc (In/Zn) in the deposited film was accurately tuned by controlling the ratio of In/Zn precursor pulses. A 2:1 In/Zn ratio exhibits both high mobility (> 30 cm 2 V −1 s −1 ) and good stability. The same team further designed quaternary zinc compounds of indium gallium zinc oxide with tunable electrical properties by adjusting the ALD cycle numbers of each binary MO. [84] The field-effect mobility of indium gallium zinc oxide decreased with an increase in Ga-content, while the corresponding V T rose significantly (Figure 9a,b). The decreased mobility and increased V T of oxide TFTs are attributed to the incorporation of  [84] Copyright 2015, American Chemistry Society. c) Energy levels (left) and optical absorption spectra (right) of Zn 1-x Mg x O films with varied Mg contents. Reproduced with permission. [107] Copyright 2014, Wiley-VCH. d) Change in μ sat , V T , I ON /I OFF and interface trap density (N it ) of the ALD-MZO TFTs depending on the Mg content. Reproduced with permission. [141] Copyright 2014, AIP Publishing.
Ga-atoms in IZO, which suppresses oxygen vacancy formation through strong Ga-O bond enthalpy.
It is worth noting that hetero-element doping in binary MOs represents an effective strategy to produce several multinary MOs. [98] For example, ZnO has been widely doped with aluminum, boron, indium, niobium, and magnesium, to improve its electrical properties and promote its applications in optoelectronic devices. [64,98,[138][139][140] Mg-doped ZnO (MZO) films show gradual bandgap increases from 3.18 eV (binary ZnO) to 3.37 eV (ternary Zn 1-x Mg x O) after suitable Mg doping (Figure 9c). [107] Nbdopants also exhibit analogous bandgap tunability when applied to ZnO films. [98] Adaptation of precursor ratios during deposition cycles affords further compositional tuning possibilities for MZO films. [141] Figure 9d exhibits the influence of Mg content in ALD-MZO films on the TFT performance. [141] With a cycle ratio of MgO/ZnO deposition increases from 1:10 to 1:2, the ALD-MZO TFTs deliver suppressed electrical performance with a mobility decreased from 4.32 to 0.47 cm 2 V −1 s −1 and a V T increased from 6.05 to 9.51 V. In contrast, the I ON /I OFF and N it are almost unchanged.
Among various doped-ZnO materials, Al-doped ZnO (AZO) thin films have received much attention owing to their unprece-dented high mobility up to 136 cm 2 V −1 s −1 , [142] as well as the low-cost, high abundance, and non-toxic nature of elemental Al. [143] Investigation of Al-doping effects on the bias-stress stability of ALD-AZO transistors indicates that 3% Al greatly preserves V T hysteresis fidelity, whilst retaining adequate output curve characteristics. [144] However, beyond 5% Al the formation of insulating Al 2 O 3 greatly inhibits TFT performance. XRD analysis of the 3%-AZO showed greatly improved grain orientation and size, which is postulated to enhance stability through the attenuation of trap site formation. Hf is also widely used as a doping element for achieving stable ZnO TFTs. Integration of novel channel architectures using n-type Hf-doped ZnO (HZO) has demonstrated improved bias stability, whilst retaining comparable mobility (4.2 cm 2 V −1 s −1 ). [102] The HZO/ZnO/HZO sandwich heterostructure affords enhanced surface layer stability under ambient conditions, whilst the additional HZO layer in contact with the dielectric interface reduces V T . Similarly, n-type ZnO/HfO 2 multilayer architecture has been fabricated as a channel in TFTs by ALD (Figure 10a). [145] This multilayer structure (TFT-C) exhibits a comparable field-effect electron mobility of ≈13.1 cm 2 V −1 s −1 , but a particularly high I ON /I OFF of ≈8 × 10 9 which is over 7 times higher than that of TFT-A (pure ZnO) and TFT-B (ZnO/HfO 2 ) (Figure 10b). A multilayer structure analogous to that of TFT-C was further investigated by HRTEM, as shown in Figure 10c. [146] The multilayer heterostructure affords fully transparent devices and circuits, where all oxide components including the ZnO/HfO 2 multilayer channel, AZO electrodes, and HfO 2 dielectric were deposited by ALD and entirely indium-free. The TFTs can be fabricated on polyethylene naphthalate (PEN) to deliver high electrical performance ( sat of 8.5 cm 2 V −1 s −1 , I ON /I OFF over 10 9 , and SS value of 0.201 V dec −1 ). Moreover, the multilayer channel TFTs (ML-TFTs) show a maximum V T shift of only +0.3 V and −0.1 V after 3000 s of positive bias stress (PBS) and negative bias stress (NBS), respectively, demonstrating the excellent device operational stability (Figure 10e,f). Compared with the single-layer TFTs (SL-TFTs), the ML-TFTs show a comparable V T shift under the PBS but a much smaller V T shift under the NBS (Figure 10g), due to efficient passivation of the multilayer ALD-ZnO channel by the ultrathin HfO 2 layer. The ML-TFTs based on ALD-ZnO can be further used for designing logic devices such as a negative channel MO semiconductor (NMOS) inverter (Figure 10d), displaying high-performance static voltage transfer characteristics (Figure 10h). The voltage transfer curves exhibit the typical supply voltage (V DD ) dependent rectangle shape. The output voltage (V output ) remains the same with V DD within the transition voltage (V M ) and then drops immediately to V GND when the input voltage (V input ) exceeds V M .
In the interest of expanding the catalog of suitable materials for complementary logic circuits, research in p-type MO semiconductors has increased in tandem in response to the rapid devel-opment of novel n-type materials. The above examples highlight how sequential deposition using ALD may be used to fabricate high-quality heterostructures. Thus, ALD remains an extremely promising technique for the development of future p-n-type heterojunctions.

Metal Oxide Insulators
Over the past decades, several MO insulators have been extensively utilized in electronic devices as gate dielectrics and/or protecting layers due to their high dielectric constant, large optical transparency, and excellent stability. [87,[147][148][149][150] Combining MO insulators with different semiconductor channel layers can significantly optimize the device performance and stability of FETs. Primarily, MO insulator/channel optimization has been demonstrated to greatly improve mobility, I ON /I OFF , hysteresis suppression, and operation stability. [69,151] It is worth noting that the trap state generated at the surface/interface of semiconductors such as those of group III-V compounds are influenced by atmosphere or impurities, resulting in poor device performance. [152] Thus, attenuation of trap density is necessary for improving the electrical performance of various FETs. Adoption of ALD-processed MO insulators on group III-V semiconductors suppresses interface trap state formation due to the high quality of oxide-dielectric or -passivation layer deposited. [153] For instance, the ALD-Al 2 O 3 /GaAs structure exhibited an upper limit for N it of 5 × 10 11 -10 12 cm −2 eV −1 . [154] In this section, MO insulators fabricated by www.advancedsciencenews.com www.advancedscience.com ALD are discussed. Influences on device performance, contribution as functional dielectrics, and protecting/encapsulating layers in FETs-based electronic devices will be highlighted. Electrical performance parameters and transistor function of representative ALD-MO insulators are summarized in Table 3.

Aluminum Oxide
Aluminum oxide (Al 2 O 3 ) is widely applied as an insulator within electronic devices due to its high dielectric constant (k) and wide bandgap. [164,165] Currently, trimethylaluminum (TMA) is the most commonly used aluminum precursor for depositing Al 2 O 3 by ALD. [68,150,155] Utilizing an ALD-Al 2 O 3 dielectric, MgZnObased TFTs have shown improved electrical performance compared with devices with a SiO 2 dielectric. [166] The corresponding mobility and the I ON /I OFF were improved from 5.65 to 7.73 cm 2 V −1 s −1 , and 4.4 × 10 5 to 1.2 × 10 7 , respectively, while the SS was decreased from 0.80 to 0.29 V dec −1 . ALD-Al 2 O 3 has also been used as a gate dielectric layer in TMCs-based FETs to improve their electrical performance. [68] For instance, WSe 2 -based FETs coupled with an ALD-Al 2 O 3 top-gate dielectric layer exhibited excellent mobility of 70.1 cm 2 V −1 s −1 and a high I ON /I OFF of 10 6 . [155] However, the lack of nucleation sites, which are mainly provided by dangling bonds on the surface of TMCs, hinders the formation of a conformal dielectric layer on the channel surface. [167] Moreover, island-like growth of high-oxide clusters on the pristine MoS 2 layer easily forms some defects such as pinholes, leading to increased gate leakage currents. [70,168] Therefore, thicker MO dielectrics are required for the top-gated TMD transistors. High-temperature requirements commonly observed for processing MO dielectrics may result in oxidation damage to TMC channels. Thus, deposition of highquality ultrathin MO dielectrics onto novel TMC channel materials remains a challenge for developing new TFT technologies.
The interfacial chemistry of ReS 2 was in situ analyzed with XPS during the deposition cycles of Al 2 O 3 . [169] Standard PEALD combined with a UV-Ozone pretreatment promotes the formation of weak S-O bonds, which can facilitate nucleation and hence uniformity of the Al 2 O 3 dielectric layer. Thus, the application of non-thermal ALD techniques may be beneficial for suppressing non-ideal surface growth mechanics among TMCs lacking appropriate nucleation density. The deposition of Al 2 O 3 using TMA and water as co-reactants has been widely adopted due to the well-established robustness of the reaction and detailed mechanistic understanding. [61,68,150] However, the stability of chemical bonds formed during this process, such as Al-Al and Al-O-H, may lead to unwanted defects, which will influence the performance of final electronic devices. [170] Previous literature has demonstrated that defect suppression occurs when using ozone (O 3 ), through the removal of -OH groups, [171] or direct use of O 3 as a co-reactant. [172] The use of O 2 plasma has also demonstrated reduced levels of -OH impurities, resulting in high-quality Al 2 O 3 films. [173] Wang et al. deposited high-quality Al 2 O 3 gate dielectrics by PEALD using both H 2 O and O 2 plasma as oxygen sources within one cycle (Figure 11a down). [149] Compared with a sample without O 2 plasma (Figure 11a above), AlGaN/GaN-based metal-insulator-semiconductor high electron mobility transistors (MIS-HEMTs) with the O 2 plasma-derived Al 2 O 3 dielectric exhibit improved electrical performance with a much smaller hysteresis ( Figure 11b). Moreover, a lower SS of 68 mV dec −1 and a higher I ON /I OFF of ≈10 10 are achieved compared with a SS of 97 mV dec −1 and an I ON /I OFF of ≈10 8 for the sample without O 2 plasma ( Figure 11c).
As discussed above, besides the trap states induced by -OH impurities in the Al 2 O 3 dielectric, surface oxides on the surface of non-oxide semiconductors, particularly for group III-V semiconductors, seriously degrade the electrical performance of final devices. [174,175] Indeed, eliminating surface oxidization of the semiconductor and reducing the interfacial trap state density are effective strategies to improve the electrical performance of group III-V semiconductor-based MOSFETs. [175,176] Native oxide ILs on group III-V semiconductors are diminished during Al 2 O 3 deposition by ALD due to the formation of volatile IL products and conversion of interfacial oxides to Al 2 O 3 . The so-called interfacial oxide self-cleaning, resulted in lower trap densities and better electrical properties. [152,177,178] Moreover, the ALD-Al 2 O 3 dielectric as an encapsulation layer efficiently minimized the moistureabsorption effects on the insulator/semiconductor interface, thus contributing to a more stable interface state and improved electrical performance. [179] High-temperature induced surface oxidization of the semiconductors whilst depositing high-k oxides by ALD is another factor that leads to the degradation of electrical performance for www.advancedsciencenews.com www.advancedscience.com FET-based devices. Therefore, decreasing the ALD temperature for processing MO insulators is an attractive route to improve device performance. [180] Decreased temperature during ALD of an Al 2 O 3 dielectric layer onto p-type GaSb-based FETs has resulted in an increase in the hole mobility. [176] This improvement may be attributed to suppressed oxidization and trap state density at the semiconductor/insulator interface, which is known to easily occur in response to higher ALD temperatures. As a result, compared with the high-temperature derived Al 2 O 3 , GaSb-based MOSFETs with the ALD-Al 2 O 3 dielectric deposited at only 150°C delivered a highly decreased N it of ≈4.5 × 10 13 cm −2 eV −1 . Enhanced TFT performance at lower ALD temperatures was also reflected in the deposition of an Al 2 O 3 dielectric/passivation layer on a polycrystalline diamond. Devices fabricated at 200°C displayed a higher output current, larger V T , and lower onresistance compared with that deposited at 300°C. [180] In addition, ALD-processed Al 2 O 3 has been also employed as an effective passivation layer to reduce the surface trap density, and thus suppress the threshold voltage hysteresis significantly. [80] Si et al. demonstrated enhanced FET performances through the passivation of indium selenide ( -In 2 Se 3 ) by ALD-Al 2 O 3 . [151] Figure 11d  Additionally, the adoption of an ALD-Al 2 O 3 passivation interlayer between the p-type SnO film and the SiO 2 dielectric layer can efficiently improve the mobility of SnO TFTs from 1.8 to 5.4 cm 2 V −1 s −1 , whilst decreasing the V hy from 4 to 0.2 V. [80] The passivated SnO channel showed outstanding electrical performance stability and negligible degradation after long-term storage for over 1 year. Enhanced performance of OFETs was also observed when inserting a thin ALD-Al 2 O 3 interlayer between the organic dielectric and semiconductor layers. [147] Passivated OFETs with the ALD-Al 2 O 3 dielectric interlayer (only 1 nm) showed a significantly reduced leakage current and elevated mobility of 0.65 cm 2 V −1 s −1 , much higher than 0.08 cm 2 V −1 s −1 for the devices without an Al 2 O 3 interlayer.
In short, ALD is a mature technique to grow Al 2 O 3 films for electronic applications that can participate in the improvement of device performance. However, the film quality (i.e., film thickness, surface roughness, and pinhole defects) is still one of the main limits that hinder the progress of ALD-Al 2 O 3 towards high-performance electronic devices. In addition, the corrosion of ALD-Al 2 O 3 films in a humid environment remains a problem requiring a solution. [181]

Hafnium Dioxide
Hafnium dioxide (HfO 2 ) is an insulating MO with a bandgap of 5.3-5.7 eV. [76,182] Since 2007, a hafnium-based oxide was intro-duced to replace conventional SiO 2 in FETs by Intel, since then it has become a widely used high-k gate dielectric due to its suitable band offset with Si and excellent dielectric constant of 25, far higher than that of SiO 2 . [183] In relation to the synthesis of hafnium-based oxides, ALD is one of the most promising techniques to design high-quality HfO 2 films with controllable thickness and high conformality. Various hafnium-based precursors such as halides and amides have been utilized for preparing ALD-HfO 2 films. [70,157,183] As an alternative to the normally used oxygen source (e.g., water, O 2 and O 3 ), carboxylic acids have also been demonstrated for the ALD of high-quality HfO 2 films. [184][185][186] However, a point of concern is the incorporation of inorganic/organic ligands in the deposited films during the ALD process significantly affects their final electrical properties. [183] Therefore, it is particularly important to select suitable metal precursors and oxygen sources for developing high-quality HfO 2 films with excellent properties towards electronic applications.
Among the hafnium-based precursors, hafnium tetrachloride (HfCl 4 ) is commonly used for depositing HfO 2 dielectric films due to its good thermal stability, which ensures the minimized decomposition of metal precursors. [183,187,188] HfO 2 films deposited with HfCl 4 also show greater stoichiometry, crystallinity, and lower leakage currents in Si-based electronic devices compared with those derived from TDMAHf. [183] In addition, HfO 2 films made from HfCl 4 display improved electrical performance in graphene-based FETs due to better nucleation of HfCl 4 on 2D graphene substrates. It should be noted that HCl is the byproduct generated when using HfCl 4 and may cause etching damage and hence hinder device performance.
In addition to metal precursors, oxygen source selection is a key parameter that can affect the electrical performance of electronic devices. Compared with a water-derived HfO 2 film, the ozone-derived HfO 2 layer has given rise to higher threshold voltages and lower gate leakage currents in the metal-oxide semiconductor heterostructure FETs (MOS-HFETs). [189] Post-deposition annealing is another factor that can be tuned to optimize both structural characteristics and electrical properties of the ALD-HfO 2 films. [190] Recently, the incorporation of HfO 2 into 2D semiconductor devices has also emerged as a promising development for enhanced device performance. However, homogenous nucleation of ultrathin dielectric films remains a significant challenge during the ALD process. Price et al. demonstrated the deposition of a sub-5 nm uniform HfO 2 dielectric onto 2D MoS 2 and WSe 2 using PEALD when fabricating top-gate FETs. [191] Compared with thermal ALD, PEALD can yield significantly improved nucleation on 2D crystals, resulting in a uniform and smooth HfO 2 thinfilms. Plasma damage to the surface of TMCs remains an issue when processing 2D materials, which may limit its application for 2D TMCs approaching monolayer thickness. [157] Similar to the utilization of perylene tetracarboxylic acid (PTCA) for depositing uniform Al 2 O 3 on graphene, [192] a monolayer (ML) molecular crystal of 3,4,9,10-perylene-tetracarboxylic dianhydride (PTCDA) was used as a nucleation layer to deposit ultrathin HfO 2 dielectrics by ALD on 2D materials including graphene, MoS 2 , and WSe 2 (Figure 12a). [70] This method affords reduced density of trap states at the interface, suppressed leakage currents, and an improved breakdown field. AFM images (Figure 12b) and Passivation of 2D TMC interfaces is another feature of ALD-HfO 2 , which may be exploited for improving device performance. [69,193] TMC semiconductors are sensitive to surface oxidation reactions from atmospheric moisture and oxygen, leading to degradation and poor device longevity. Therefore, passivation and encapsulation using high-k dielectric materials are required to develop high-performance TMC transistors. [69,77] For example, the hysteresis of HfS 2 transistors reduced significantly after passivation using ALD-HfO 2 and corresponded with enhancement to the source-drain current. [188] FETs using a MoS 2 channel encapsulated by an ALD-HfO 2 layer can also display enhanced electrical performance compared with reference devices without encapsulation. [69,168] Layer thickness of HfO 2 may also reduce charge impurity-induced scattering, in addition to screening from atmospheric interferences. [168] More practical electronic device application of ALD-HfO 2 , was demonstrated by Marega et al. through designing floating-gate FETs (FGFETs) for logic-in-memory devices and circuits (Figure   13a-c). [156] The ALD-HfO 2 dielectric film can work as a blocking and tunnel oxide to efficiently modulate the electric field within the MoS 2 channel. Basic characterization of the devices is performed under a V DS of 50 mV and a V G ranging from −12.5 to 12.5 V, delivering a memory window of 10.6 V (Figure 13d). Moreover, the FGFETs are further designed and integrated into twoinput and three-input logic circuits (Figure 13e). As a representative, a complete three-input NAND logic, is normally operated and its corresponding logic input and output curves are shown in Figure 13f. The stable operation of these reprogrammable logicin-memory devices highlights the practical benefits of adopting ALD for optimizing FET performance in developing areas of the electronics industry.

Other Insulating Metal Oxides
Despite rapid advances in the commonly used Al 2 O 3 and HfO 2 , additional insulating MOs such as ZrO 2 , [194] BeO, [158] La 2 O 3 , [161] and Y 2 O 5 [160] have recently attracted attention in electronics owing to their high dielectric constants and large bandgap values. For example, Anderson et al. deposited a ZrO 2 gate dielectric on AlGaN/GaN MOSFETs by ALD, resulting in a much lower interface trap site at a density of 7.00 × 10 12 cm −2 eV −1 than that of the Schottky-gate reference device (2.03 × 10 13 cm −2 eV −1 ). [195] Moreover, the gate leakage current was reduced by up to four orders of magnitude. Chen and co-workers encapsulated organic light-emitting diodes (OLEDs) with ZrO 2 by PEALD and molecular layer deposition (MLD), leading to the efficiently improved water barrier properties of up to 3.08 × 10 −5 g m −2 day −1 . [196] In addition, multinary ALD-MO insulators such as titanium aluminum oxides (TiAlO), [162] and magnesium calcium oxides (MgCaO), [197] are also promising candidates as gate dielectrics or encapsulating materials.
The potential size reduction obtained from using thinner MO with high dielectric constants, such as ZrO 2 and Ta 2 O 5 , make ALD a promising technique for novel device manufacturing. [198]

Metal Oxide Dielectric Heterostructures
Insulating single MO dielectrics have been successfully applied on various channel layers to improve the electrical performance of the final devices. However, it is still a challenge to deposit ultrathin, continuous, and pinhole-free MO films on the surface of a channel layer due to nucleation site deficiency, especially on 2D channel materials. [68,70] Therefore, several methods have been employed to promote surface nucleation and obtain high-quality dielectric layers. Examples include, pretreatment (activation) of the substrate surface before the ALD reaction, using strong oxidants like O 3 or O 2 plasma during the ALD process, and adopting higher reaction temperatures. [149,171] As discussed in previous sections (ALD-Al 2 O 3 and ALD-HfO 2 ), the oxidization of channel materials is predominantly caused by high deposition temperatures and the use of strong oxidizing agents. This remains a consistent hindrance to the broad adoption of ALD in the fabrication of ultrathin MO dielectric films. [149,163,199] A successful strategy to suppress channel layer degradation during ALD and enhance dielectric properties is the incorporation of an intermediate layer to design MO dielectric heterostructures. [163,199,200] Similar to the use of a PTCDA seeding layer as mentioned above, an ultrathin MO layer is preemptively deposited onto the channel as a seeding layer prior to MO ALD. For example, an Al 2 O 3 /ZrO 2 dielectric heterostructure was deposited onto MoS 2 , yielding significant improvements to device performance. [199] A 5 nm layer of Al 2 O 3 was initially deposited onto the MoS 2 channel by ALD at 150°C using TMA and H 2 O as precursors. The corresponding second ZrO 2 dielectric (45 nm) was then deposited at an increased temperature (300°C) onto the Al 2 O 3 seeding layer. Compared with the MoS 2 -TFTs using a single ZrO 2 dielectric layer, the TFTs decorated with the Al 2 O 3 /ZrO 2 heterostructure dielectric show better electrical performance with improved mobility from 5.1 to 7.1 cm 2 V −1 s −1 .
Besides deposition of high-quality dielectric films onto a channel layer, an intermediate/nucleation layer in heterostructured MO dielectrics can also protect channel materials during the ALD process, and prevent the creation of metal atomic vacancies or interstitial defects. [68,163] For example, the formation of Zn vacancies during the ALD of a ZnO film onto a dielectric Ta 2 O 5 layer leads to inferior properties of ZnO TFTs. [163] To solve this problem, a thin ALD-Al 2 O 3 layer has been adopted between the ZnO channel layer and the Ta 2 O 5 dielectric layer to improve the electrical performance of ZnO-based TFTs (Figure 14a). [163] Compared with a single Ta 2 O 5 dielectric, a series of Al 2 O 3 /Ta 2 O 5 dielectric heterostructures grown by ALD show comparable dielectric constants but dramatically suppressed leakage currents (Figure 14b). Further increasing the Al 2 O 3 film thickness results in the gradual attenuation of leakage current density, which is beneficial for reducing off-currents and improving total device performance. These ALD-MO dielectrics also have good stability in capacitance at frequencies from 1 kHz to 1 MHz (Figure 14c). As a result, the ZnO-TFTs with an optimized Al 2 O 3 /Ta 2 O 5 dielectric show a greatly improved mobility (13.3 cm 2 V −1 s −1 ) than that of the single Ta 2 O 5 dielectric layer (0.1 cm 2 V −1 s −1 ), as well as a suppressed SS value and an improved I ON /I OFF (Figure 14d).
Examples of advanced dielectric heterostructures using sputtering deposition (SD) of Ta 2 O 5 onto an ALD-Al 2 O 3 thin buffer layer have also been demonstrated. [201] In contrast with the SD method, ALD techniques have several additional advantages for depositing MO dielectrics, including low growth temperatures, uniform film deposition, and controllable film thicknesses. Moreover, transfer from ALD to SD chamber may introduce surface-adsorbed air contaminants, which may impact the subsequent purity of SD-deposited films and hence the electronic performance of TFTs. Liu et al. studied the electrical properties of different TiO 2 /Al 2 O 3 dielectrics which were prepared by SD and ALD, respectively. [202] Compared with MOSFETs with the SD-TiO 2 /Al 2 O 3 dielectric, the devices with the ALD-TiO 2 /Al 2 O 3 films exhibit a much lower leakage current density and better capacitance-voltage characteristics due to the better quality of thin-film MO dielectric heterostructures made by ALD.
Apart from utilizations in inorganic semiconductors-based FETs, MO dielectric heterostructures have also been widely used in OFETs for enhancing their electrical performance. [181,200] Composition and thickness are important parameters of MO dielectrics and strongly influence transistor performance. [163,203,204] Thus, MO heterostructures with suitable compositions and optimized thicknesses for TFTs remain a major research focus for ALD.

Metal Oxide Electrodes and Electrode Interlayers
In addition to its application as semiconductor channel materials and insulators, ALD-MOs have been adopted for use as transparent conductive oxide electrodes (TCO) and semiconducting electrode interlayers in transistors. For example, indium-tinoxide (ITO), a well-known heteroatom doped SnO 2 , is widely employed as a kind of TCO electrode. [205] Introduction of heteroatoms into oxides increases the carrier concentration, thus converting MO semiconductors to conductors. For pure SnO 2 made by ALD, it can be transformed from the semiconductor to conductor by adjusting ALD conditions (i.e., temperature) to alter carrier concentrations. [92] For instance, highly conductive SnO 2 serving as a transparent gate electrode has been fabricated by controlling the ALD reaction temperature. [66] The ALD-SnO 2 films deposited at 200°C exhibit a large carrier concentration (>10 20 cm −3 ), a low resistivity (≈0.0031 Ω cm), and a high transparency (≈93%) in most of the visible range (Figure 15a). ZnO-based TFTs with such an ALD-SnO 2 gate electrode (Figure 15b) exhibit excellent electrical performance with a high saturation mobility of 15.3 cm 2 V −1 s −1 , a low SS of 130 mV dec −1 , a very high I ON /I OFF ratio of ≈10 9 , and a low gate leakage current (I G ) of less than 10 −12 A (Figure 15c,d). The ALD-SnO 2 gated-TFTs outperform other devices based on electrodes of conventional ITO ( = 15 cm 2 V −1 s −1 , SS = 160 mV dec −1 , and I on /I off ≈10 9 ) and ALD-AZO ( = 11 cm 2 V −1 s −1 , SS = 180 mV dec −1 , and I on /I off ≈10 9 ). Based on these findings, NMOS inverters were designed to further demonstrate the practical application of ALD-SnO 2 gate electrodes. The NMOS inverter with the ALD-SnO 2 gate (Figure 15e) displays static voltage-transfer curves (Figure 15f), highlighting its excellent room temperature performance under varying V DD values ranging from 2.5 to 25 V. Moreover, the maximum gain values of the inverter gradually increase from 20 to 382 upon raising V DD from 2.5 to 25 V (Figure 15g,h).
Additionally, transition metal oxides (TMOs) such as VO x , [67] and MoO 3 , [206] possess suitable semiconducting properties and high stability, enabling them to serve as electrode interlayers for efficient charge injection in optoelectronic/electronic devices. [207] Large contact resistance at organic/metal interfaces seriously limits the carrier mobility and I ON /I OFF of OFETs. [208] Reduction of interfacial contact resistance has been demonstrated using an ultrathin ALD-VO x film at the electrode/semiconductor interface in OFETs. It functions as a hole injection layer, promoting electrode work function tunability and charge transport. [67] The VO x interlayer with controlled thicknesses was deposited by ALD with tetrakis(dimethylamino) vanadium [V(dma) 4 ] and H 2 O at a low www.advancedsciencenews.com www.advancedscience.com temperature (50°C). After 20 ALD cycles, the resulting OFETs exhibited remarkably improved electrical performance with a reduced contact resistance from 71 to 10 kΩ cm and enhanced mobility from 1.09 to 1.56 cm 2 V −1 s −1 . The ALD-VO x interlayer also performed well as a barrier material against moisture/oxygen transmission in OFETs, delivering a good retention (over 83% after 30 days) in the mobility for devices with a combined ALD-Al 2 O 3 layer for encapsulation.

ALD of Metal Chalcogenides for FETs
Interest in applications of MCs and particularly TMCs within next-generation electronics has risen steeply over the past decade, driven by their intrinsic layered crystal structures and unique properties. [193,209] TMCs typically consist of a metal/chalcogen atomic ratio of 1:2, although exceptions of 1:1, [210,211] and 2:3 [212] are possible. TMCs have three classical polymorphs, which are tetragonal (1T), hexagonal symmetry (2H), and rhombohedral (3R). [213] Their electrical properties strongly depend on the polymorphs and structural phase transition, where the TMCs with 1T and 2H phases show metallic and semiconducting behaviors, respectively. For further details on TMCs, their chemical compositions, electronic structures, and applications have been described in a comprehensive review by Chhowalla and co-workers. [214] Versatile processing methods such as exfoliation, [215] CVD, [216] and magnetron sputtering [217] have been reported for the synthesis of TMCs for applications in electronics. However, intrinsic factors arising from these methods often limit the fabrication of TMC films in a uniform, repeatable, scalable, and tunable manner. Precise film thickness is of particular importance to TMCs due to their layer-dependent bandgap characteristics. Bandgap magnitude and crystal structures are influenced by the thickness of TMCs, resulting in a transition from an indirect to direct bandgap material, in the bilayer to a monolayer transition. [213] The tunability of ALD has established it as an ideal candidate for the fabrication of high-quality MCs as channel materials, particularly with regard to thickness control at the nanoscale. [218,219] Channel length ( ) is affected by the thickness of both channel and dielectric layers according to the following Equation (4), where N is the number of gates, and the ch (d ch ) and ox (d ox ) are the dielectric constants (thickness) of the channel and the oxide, respectively. [220] Thus, ALD is an efficient technique to minimize the size of electronic devices by using ultrathin channel materials, such as few-or mono-layer (<1 nm) TMCs. [198] This section will discuss MCs and their heterostructures fabricated using ALD for applications in transistors, with an emphasis on film structural characteristics and device performances. Representative examples of various MCs synthesized by ALD and their related electrical properties as well as device performance are presented in Table 4.

Molybdenum Dichalcogenides
Molybdenum disulfide (MoS 2 ), which occurs naturally as a mineral (molybdenite), has attracted great attention in high-performance FETs due to its tunable intrinsic bandgap (1.2-1.9 eV) and high carrier mobility (up to 500 cm 2 V −1 s −1 ). [209,239] The first publication of single-layer MoS 2 used within transistors reported excellent semiconductor properties with a mobility of 200 cm 2 V −1 s −1 and an I ON /I OFF of 10 8 at room temperature. [240] Subsequent demonstrations of mono-to-few layer MoS 2 transistors further supported the initial findings. [241][242][243] Numerous MoS 2 precursor combinations have been used in the ALD of TMCs such as MoCl 5 and H 2 S, [218,244] Mo(CO) 6 and H 2 S, [245] Mo(CO) 6 and CH 3 S 2 CH 3 , [246] Mo(NMe 2 ) 4 and H 2 S, [73] as well as Mo(NMe 2 ) 2 (N t Bu) 2 and H 2 S. [63] Benefiting from the layer-controllability and reproducibility, ALD-MoS 2 shows great potential for applications in FETs. [209,219] For example, MoS 2 channel fabricated by ALD from MoCl 5 displays an effective mobility of 1.0 cm 2 V −1 s −1 in back-gate FETs with a 20 μm channel. [221] However, temperature requirements of the MoCl 5based process are beyond the upper limit tolerated by organic polymer substrates and photoresists. [73] Additionally, the generation of chlorine-containing by-products such as HCl results in etching damage to both substrates and deposited films.
Metal amides show promise as metal precursors for lowtemperature ALD due to their high reactivity and generation of volatile byproducts. [63,73] By adopting Mo(NMe 2 ) 4 as a metal precursor and H 2 S as a co-reactant, ALD-MoS 2 films were deposited at a record low reaction temperature of 60°C. [73] Low ALD temperatures enable simple device fabrication using lithographic lift-off patterning (Figure 16a). First, a silicon nitridecoated silicon wafer is covered by a patterned resist using a maskless lithography protocol. The MoS 2 film of the desired thickness is then deposited by ALD at 80°C. Removal of the resist using n-methyl-2-pyrrolidone (NMP) at 75°C yields uniform arrays of patterned MoS 2 (Figure 16b-d). Finally, post-deposition sulfurization is performed under an atmosphere of sulfur vapor for 5 h, yielding highly crystalline MoS 2 . The electrical characteristics of the MoS 2 semiconductor are further evaluated as FET components (Figure 16e,f), delivering a mobility of 0.23 cm 2 V −1 s −1 and an I ON /I OFF of ≈10 2 .
However, the low temperature used to deposit MoS 2 results in amorphous films with numerous defects, leading to poor FET performance observed in the large off-state current and low mobility. [239] Improved crystallinity and better electrical performance of TMC films may be achieved using post-deposition sulfurization of the film at high temperatures. [239,247] The standard sulfur sources such as sulfur powder and H 2 S, [219,248] may also be replaced by carbon disulfide (CS 2 ), a strong sulfurizing reagent with low toxicity and cost. [239,249] Moreover, the relatively low sulfurization temperature used for CS 2 may be more compatible with electronic devices, especially for flexible transistors. Compared with as-deposited ALD-MoS 2 , improved electrical performance was demonstrated by sulfurization using CS 2 to obtain ≈100 times higher I ON /I OFF (5 × 10 2 ) and 36 times higher mobility (0.36 cm 2 V −1 s −1 ). [239] Sulfurizing MoO 3 films pre-deposited by ALD is another possible technique to synthesize high-quality MoS 2 films with controlled thicknesses. [219,250,251] Sulfurization of the ALD-MoO 3 film at 500°C followed by annealing at 900°C with sulfur powder yields a MoS 2 film (Figure 17a,b). [219] The layer thickness of MoS 2 may also be precisely adjusted from monolayer to four layers (Figure 17c). When used to prepare a top-gate FET (Figure 17d), the monolayer MoS 2 film shows a typical n-type FET behavior with a mobility of 0.76 cm 2 V −1 s −1 and an I ON /I OFF of 10 4 (Figure 17e). By contrast, the electron mobility of the tetra-layer-MoS 2 (5.9 cm 2 V −1 s −1 ) is more than 8 times higher than that of the monolayer MoS 2 (Figure 17f). Similar trends are observed for CVD-MoS 2 with mobility values increasing from 3.6 to 15.6 cm 2 V −1 s −1 in the monolayer and trilayer, respectively. [252] The improved performance of MoS 2 may be due to the enhanced screening effect induced by an increase in layer numbers of MoS 2 . [253] Generally, monolayer MoS 2 suffers from fluctuating potential, which is caused by the formation of traps at the interface between the dielectric layer and the semiconductor channel. [252] The additional layers of TMCs can efficiently suppress the negative effects of potential fluctuation, thus resulting in a higher carrier mobility. Although previous reports have presented deposition of TMCs on various substrate materials, it remains challenging to synthesize wafer-scale, uniform 2D TMCs in a scalable manner via direct ALD routes. [209,219] This obstacle hinders the integration of 2D TMCs for practical applications in the semiconductor industry. Thus, advances in ALD protocols to produce large-scale, homogeneous 2D TMC thin films are necessary. Consequently, Jeon et al. have synthesized homogeneous few layers of MoS 2 on a 6inch wafer by ALD with the utilization of diethylsulfide (DES) as an inhibitor layer. [209] The deposited MoS 2 films exhibited a sig-nificant increase in grain size and surface coverage (>620%), as well as excellent room temperature mobility (13.9 cm 2 V −1 s −1 ) and I ON /I OFF (>10 8 ).
Conformal surface coating of TMC films onto nonplanar, large surface-to-volume ratio substrates has been extensively demonstrated using ALD, highlighting the benefits to flexible electronic applications. [224,227,233] Deposition of an ultrathin MoS 2 layer onto a SiO 2 nanowire via ALD (Figure 18a) affords a coreshell nanowire FET architecture (Figure 18b) with an omega (Ω)shaped top gate. [224] Cross-sectional TEM images of the deposited nonplanar MoS 2 (Figure 18c) highlight the formation of uniform and high-crystalline MoS 2 layers. The fabricated Ω-shaped MoS 2 FETs exhibit a mobility of 0.02 cm 2 V −1 s −1 and an I ON /I OFF of ≈10 2 (Figure 18d), which are comparable to those of the planar MoS 2 FETs with a mobility of 0.01 cm 2 V −1 s −1 and an I ON /I OFF of ≈3.5 × 10 2 (Figure 18e).
In comparison with MoS 2 , molybdenum selenide (MoSe 2 ) displays a similar high average room temperature mobility (≈50 cm 2 V −1 s −1 ) and a high I ON /I OFF ratio (10 6 ) in addition to bandgaps ranging from 1.1 to 1.6 eV. [254] MoSe 2 materials are typically prepared by exfoliation and CVD. [254,255] However, ALD techniques may also deposit MoSe 2 using Mo(CO) 6 or MoCl 5 and ((CH 3 ) 3 Si) 2 Se as molybdenum and selenium precursors, respectively. [256] Selenization of ALD-MoO 3 also achieves high-quality MoSe 2 films with the desired thickness. [257,258] Similarities between silicon and MoSe 2 , including bandgap size and electronic properties, make the latter an excellent candidate for application as a semiconductor channel material.

Tungsten Dichalcogenides
Tungsten disulfide (WS 2 ), another representative of TMCs, exhibits an indirect bandgap of 1.4 eV (bulk) and a direct bandgap of 2.1 eV (monolayer). [263] It shows great potential in FET applications due to its high theoretical mobility. [264] WS 2 -based FETs have been predicted with the highest mobility of over 1100 cm 2 V −1 s −1 in a monolayer at room temperature. [265] Up to now, WS 2 has been successfully prepared by ALD with WF 6 and H 2 S, [266][267][268] tungsten chlorides (WCl 5 and WCl 6 ) and H 2 S, [226,269] W(CO) 6 and H 2 S, [270] W(NMe 2 ) 2 (N t Bu) 2 (BTBMW) and H 2 S, [59] as well as sulfurizing thickness-controlled ALD-WO 3 films. [228,229] Earlier reports have demonstrated that ALD-WS 2 can exhibit both n-type and p-type semiconducting characteristics. [227,228] For example, atomically thin WS 2 films prepared by sulfurizing ALD-WO 3 operate as n-type semiconductors with an electron mobility of 4.5 cm 2 V −1 s −1 and an I ON /I OFF of ≈10 5 . [229] The thickness of ALD-WO 3 precisely controls the layer number of WS 2 from monolayer to tetra-layer (Figure 19a). [228] The WS 2 -based top-gate FET displays impressive transfer and output characteristics with a high electron mobility of 3.9 cm 2 V −1 s −1 and a low SS of 0.6 V dec −1 (Figure 19b,c). In general, the impurity content as well as structural defects of deposited films significantly affects the electrical properties and even alter the semiconducting behaviors of 2D materials. [209] For instance, PEALD-WS 2 with a large crystal grain size operates as a p-type semiconductor with an I ON /I OFF of ≈10 5 (Figure 19d). [227] It is speculated that p-type behaviors of ALD-WS 2 FETs may arise from S deficiency in the WS 2 films.
Currently, research into tungsten selenide (WSe 2 ) for electronic applications is limited, although exfoliated single-crystal WSe 2 -based FETs have been demonstrated to exhibit a high hole mobility of 350 cm 2 V −1 s −1 at 300 K and a high I ON /I OFF of 10 6 . [271] Park et al. prepared WSe 2 by self-limited layer synthesis (SLS) using WCl 6 and diethyl selenide at a high temperature above 600°C. [231] Unlike conventional ALD processes, the layer number of target films prepared by this SLS process mainly depends on the reaction temperature rather than the SLS cycles. Control of the SLS temperature from 600 to 800°C affords WSe 2 films with a tunable layer number, from five-layers to a monolayer (Figure 19e). Back-gated FETs were used to evaluate a trilayer-WSe 2 film, exhibiting a hole mobility of 2.2 cm 2 V −1 s −1 and an I ON /I OFF of ≈10 6 ( Figure 19f).

Tin Chalcogenides
Tin disulfide (SnS 2 ) is an intrinsic n-type semiconductor with a bandgap of 2.1 eV, larger than that of monolayer MoS 2 . [272] The high bandgap suppresses source/drain tunneling in FETs, affording a high I ON /I OFF of 10 8 . [273] Furthermore, large electron mobility (230 cm 2 V −1 s −1 ) was demonstrated using adsorbatesuppressing conditions, indicating its potential for applications in FETs. [274] The fabrication of SnS 2 films by ALD has been demonstrated using TDMASn and H 2 S, [122,234,275] bis(1dimethylamino-2-methyl-2-propoxy) tin(II) and H 2 S plasma, [74] Sn(OAc) 4 and H 2 S, [276] as well as sulfurizing ALD-SnO x . [233] Phase engineering of precursor thin films via sulfurization methods has shown promising results. Back-gated FET channels prepared via deposition of an ALD-SnS film followed by a sulfurization step, performed as an n-type semiconductor with small mobility (0.014 cm 2 V −1 s −1 ). [234] Such poor electrical properties of SnS 2 can be improved by enhancing its crystallinity and control crystal orientation, [233] as well as optimizing the gate structures. [277] ALD-SnO as a precursor for SnS 2 was demonstrated using a two-step sulfurization process, consisting of an initial thermal post-deposition sulfurization (350°C), and then an H 2 Splasma treatment (Figure 20a). [233] The SnS 2 film with subsequent H 2 S plasma treatment shows better-suited crystal orientation and improved crystallinity than that with simple sulfurization (Figure 20b). Back-gate TFTs fabricated using these SnS 2 films show typical n-type behaviors (Figure 20c,d), where the I ON /I OFF is greatly increased to 10 5 for the TFTs with two-step sulfurized SnS 2 , compared with 10 3 for that with one-step sulfurized SnS 2 . Similarly, the field-effect mobility is also dramatically improved from 2 × 10 −4 to 0.02 cm 2 V −1 s −1 .
A two-step ALD process was demonstrated for obtaining crystalline and continuous SnS 2 films at a low temperature. [276] An amorphous SnS 2 thin layer deposited at 150°C was sulfurized  [224] Copyright 2020, American Chemistry Society.
at a relatively high temperature (250°C), then the formed crystalline SnS 2 acted as a seed layer for promoting the growth of crystalline SnS 2 films by low-temperature ALD (150°C). Another two-step ALD procedure demonstrated by Pyeon et al., applies low temperature (150°C) deposition of monolayer amorphous SnS 2 followed by a subsequent SnS 2 thin channel layer (240°C) (Figure 20e). [74] The amorphous monolayer selectively promotes basal growth of SnS 2 (001) during the second deposition, thus suppressing non-uniform nuclei orientation. The relationship between surface energy and grain orientation was not explored but may offer an avenue for further research. Analysis of the electrical performance as a bottom-gate TFT revealed that the asdeposited SnS 2 film mobility could be improved using an additional sulfurization step (300°C), from 0. In contrast to SnS 2 , tin monosulfide (SnS) is intrinsically ptype, with a small indirect bandgap (1.0 eV). [122,235] ALD synthesis affords p-type SnS films with a hole mobility of 0.21 cm 2 V −1 s −1 but a relatively small I ON /I OFF of 8.8. [234] Generally, SnS films with high-crystal orientation can be synthesized at a relatively low ALD temperature, [235] which is beneficial for the fabrication of electronic devices. [73,122] For instance, the Hall mobility of SnSbased FETs was improved from 0.82 to 15.3 cm 2 V −1 s −1 by tuning ALD reaction temperatures. [235] The significant improvement in carrier transport is ultimately attributed to the preferred crystal orientation of the ALD-SnS film.
The purity of channel materials is also an essential parameter that cannot be ignored in evaluating the influence on electrical Figure 19. a) Optical (up) and AFM (down) images of the transferred single, bi-and tetra-layer ALD-WS 2 nanosheet on SiO 2 substrates. b) Transfer and c) output curves for the FET based on the single layer ALD-WS 2 film. Reproduced with permission. [228] Copyright 2013, American Chemical Society. d) Transfer curves of FETs based on PEALD-WS 2 with p-type characteristics. Reproduced with permission. [227] Copyright 2018, American Chemical Society. e) Variance in film thickness of ALD-WSe 2 with controlled reaction temperatures of 600 (black), 700 (blue), and 800°C (red) synthesized by a SLS method, respectively. f) Transfer curves of a FET based on three-layer ALD-WSe 2 . Reproduced with permission. [231] Copyright 2016, IOP Publishing Ltd.
performance. [278] In some cases, multiple phases of SnS x may be present, including mixtures of SnS, SnS 2 , and Sn 2 S 3 , which may seriously limit electrical properties. [122,278] However, conversion of the as-deposited SnS x mixtures to a single-phase SnS film may be achieved via post-deposition annealing under H 2 (360°C), contributing to a greatly improved Hall mobility of 15.66 cm 2 V −1 s −1 compared with the as-deposited SnS x film of 2.83 cm 2 V −1 s −1 . [278] An analogous two-step strategy has also been applied for the ALD of SnS semiconductors. [236] A continuous amorphous ALD-SnS film was previously deposited at lower temperatures (90°C), followed by a high-temperature deposition of a crystalline SnS at 240°C. The SnS TFTs exhibit p-type behaviors with a mobility of 0.18 cm 2 V −1 s −1 and an I ON /I OFF ra-tio of 80 (Figure 21a). Correspondingly, the ALD-SnS gas sensors also display high sensitivity for NH 3 detection (Figure 21b). The facile transformation of ALD-SnS 2 to SnS with the assistance of Sn(dmamp) 2 vapors is also feasible (Figure 21c). [279] Sn(dmamp) 2 molecules adsorb onto the SnS 2 surface, triggering a reduction of the Sn(IV) forming SnS and volatile byproducts. The opposing behaviors of bottom-gate TFTs using SnS 2 and SnS in response to NO 2 gas sensing (Figure 21d) support the majority carrier species of the two phases are electrons and holes, respectively.
In addition to SnS 2 and SnS, tin selenide (SnSe) shows promise as a low bandgap (0.9 eV for indirect and 1.3 eV for direct) layered nanomaterial for electronic applications. [237,280] Semiconducting ALD-SnSe films can exhibit good p-type Figure 20. a) Illustration of the two-step sulfurization for 2D SnS 2 . b) HRTEM images of the SnS 2 on Al 2 O 3 without (left) and with (right) further H 2 S plasma treatment. c,d) Transfer curves of the TFTs based on ALD-derived SnS 2 with the one-step sulfurization (c) and the two-step sulfurization (d), respectively. Reproduced with permission. [233] Copyright 2018, Royal Society of Chemistry. e) A schematic two-step ALD process for SnS 2 . f) Schematic of nonplanar SnS 2 TFTs with a diagonal-structure and g) cross-sectional HRTEM images of the ALD-derived SnS 2 film. h) Optical image and i) transfer curves of the flexible SnS 2 TFTs with 20 devices distributed across a PI substrate. j) Trend in mobility and V T of flexible TFTs under different bending cycles. Reproduced with permission. [74] Copyright 2020, American Chemical Society.
behavior with a high hole mobility of 10 cm 2 V −1 s −1 and an I ON /I OFF of ≈10 5 .

Other Metal Chalcogenides
Aside from Mo, W, and Sn-based MCs, the fabrication of alternative MC materials such as lead sulfide (PbS), manganese sulfide (MnS), and rhenium disulfide (ReS 2 ) is possible using ALD, [210,281,282] with their development for electronic applications attracting growing interest. [238,283] MnS, is a p-type semiconductor with a wide bandgap of 3.7 eV, and it has been deposited with crystal phase-control by ALD using bis(ethylcyclopentadienyl)Mn(II) (Mn(EtCp) 2 ) and H 2 S precursors. [281] The remarkable properties include an I ON /I OFF of >10 6 and a field-effect hole mobility of 0.1 cm 2 V −1 s −1 , when applying -MnS in a top-gate FET. [283] Moreover, the MnS FETs without dielectric encapsulation show negligible degeneration of device performance after being exposed to air for 30 days, indicating their excellent air stability. Similarly, ReS 2 films can be synthesized on large-area substrates by ALD using ReCl 5 and H 2 S precursors at a wide deposition temperature range between 120 and 500°C. [282] Their use as channel materials in FETs have displayed attractive electrical performances (i.e., an I ON /I OFF of 10 6 and a SS of 750 mV dec −1 ). [284] Very recently, uniform and crystalline PbS thin-films have been produced by low-temperature ALD using rac-N 2 ,N 3 -di-tertbutylbutane-2,3-diamide lead [Pb(dbda)] and bis(trimethylsilyl)- Figure 21. a) Transfer curves of the ALD-SnS TFT. b) Gas response of the ALD-SnS based sensing device under exposure to 1000 ppm NH 3 at room temperature (the inset is a schematic gas sensor with an SEM image of its interdigitated electrodes). Reproduced with permission. [236] Copyright 2017, American Chemical Society. c) Illustration of the transformation process from ALD-SnS 2 to ALD-SnS with the assistance of Sn(dmamp) 2 . d) Gas response of the bottom-gate TFT gas sensor based on pristine ALD-SnS 2 (black) and transformed ALD-SnS (red) under exposure to 5 ppm NO 2 at room temperature. Reproduced with permission. [279] Copyright 2020, American Chemical Society.
amide lead [Pb(btsa) 2 ] as lead precursors, with H 2 S as a sulfur source. [210] The PbS films exhibited typical p-type behaviors with excellent mobility up to 70 cm 2 V −1 s −1 . Lead chalcogenides are a well-established class of ambipolar semiconductors, with carrier transport determined by an excess of either metal or chalcogen within the crystal structure. Thus, chalcogen-and lead-rich materials possess p-and n-type characteristics, respectively. [238] Post-synthesis colloidal ALD (PS-cALD) applies spin-casting (or other solution-processing techniques) to generate nanocrystals (NCs) with precise size control, followed by NC surface modifications using an adapted ALD protocol. Selective stoichiometric enhancement of the NC thin film using ALD (Figure  22a) was achieved through subsequent modification of the NC surface using chalcogen-or lead-based salts dissolved into an organic solvent (65°C). [238] The electrical properties of the stoichiometry-controlled lead chalcogenides were evaluated in a bottom-gate FET (Figure 22b). The transfer curves of PbSe after post-treatment with PbCl 2 reveal the influence of increasing Pb-surface stoichiometry on carrier transport as a function of time (Figure 22c). The initial PbSe NC FETs treated with Na 2 Se exhibit p-type characteristics with a mobility of 7.5 × 10 −3 cm 2 V −1 s −1 , which is decreased to 2.2 × 10 −3 cm 2 V −1 s −1 after 1h PbCl 2 treatment. By extending the treatment time to 6 h, an ambipolar behavior appears in the FETs. After 12 h, n-type NC FETs can be achieved with electron mobility as high as 4.5 cm 2 V −1 s −1 and an I ON /I OFF of ≈10 2 -10 3 . This transformation is also reflected in the output curves, as after 1 h PbCl 2 post-treatment, clear p-type characteristics are observed (Figure 22d), whilst at 12 h n-type characteristics are dominant (Figure 22e).

2D Heterostructures Based on MCs
In addition to single MC semiconductors, MCs-based 2D heterostructures such as MoS 2 /graphene, [222] MoS 2 /WSe 2 , [225] and MoS 2 /WS 2 , [285] may be constructed by stacking different 2D materials together. [213] These heterostructures have been extensively studied in various applications including vertical tunneling FETs, [286] photodetectors, [222] and inverters. [223] The low contact resistance within MC/graphene heterostructures affords improved performance in electronic devices, [222] whilst TMC/TMC heterostructures can function as current rectifiers due to the formation of p-n junctions. [226,287] The deposition of single-layer MoS 2 directly onto graphene via ALD, combines properties of both materials in MoS 2 /graphene heterostructures to achieve a FET-based photodetector. [222] An I DS -V DS curve evaluates the fluctuation of potential in response to light (Figure 23a), with a 116 nA photocurrent difference Figure 22. a) Schematic of PS-cALD for preparing lead chalcogenide NC films and their corresponding TEM images. The left is an as-synthesized NC thin-film, the middle is a thin-film treated with either Na 2 Se, Na 2 S or KHS solution, the right is a thin-film with further treatment in PbCl 2 solution. b) A schematic FET based on the channel of PbS or PbSe thin-films. c) Transfer curves of Na 2 Se-treated PbSe NCs without (black) and with 1 h (blue), 6 h (green), and 12 h (red) of PbCl 2 treatment at 65°C. d,e) Output curves of Na 2 Se-treated PbSe with followed by further PbCl 2 treatment for 1 h (d) and 12 h (e), respectively. Reproduced with permission. [238] Copyright 2014, American Chemical Society.  [222] Copyright 2019, Elsevier. c) Schematic device and optical image of the MoS 2 /WSe 2 FET-based PN diode, and d) the corresponding I-V curves with various gate biases. Reproduced with permission. [225] Copyright 2016, Nature Publishing group. observed at a V DS of 0.1 V and a responsivity of 241 mA W −1 . The on/off switching behavior (Figure 23b) further demonstrates its optoelectronic applications, highlighting the potential of ALD-derived 2D heterostructures.
Precursor selection is an important factor when fabricating 2D MC heterostructures using ALD, as by-products such as HCl may result in surface etching. Thus, metal halide precursors using chloride ligands are typically avoided when used in conjunction with sensitive substrates, as is the case of MoS 2 /WSe 2 heterostructures. The MoS 2 /WSe 2 heterostructures have also been fabricated using the SLS process at 800°C, where MoS 2 was deposited onto exfoliated WSe 2 flakes. [225] As a result, a top-gated FET device (Figure 23c) performs as a typical p-n diode, showing rectifying characteristics with a forward/reverse current ratio of ≈80 at a V G of −60 V (Figure 23d). Similarly, a p-n diode based on InSe/Sb 2 Se 3 heterostructure was also fabricated by stacking a p-type Sb 2 Se 3 layer on n-type InSe, which were both deposited by ALD. [287] The resulting heterostructure exhibited typical diode characteristics with a maximum leakage current of 10 −7 A at −1 V bias.
The ALD of WS 2 /SnS heterostructures ensues to give an ambipolar thin film with electron mobility of 48 cm 2 V −1 s −1 for ntype FETs and a hole mobility of 20 cm 2 V −1 s −1 for p-type FETs at room temperature. [226] However, the hole mobility of SnS in the heterostructure dropped significantly compared with that of the pure SnS (≈818 cm 2 V −1 s −1 ). This result is attributed to hole transport resistance, which may be caused by the misalignment of the SnS and WS 2 layers. The difference between crystal structures led to the growth of the SnS layer on WS 2 at an orientation of ≈15°, resulting in a remarkable drop in the hole mobility of SnS. Thus, misalignment between different TMCs remains a continuing challenge for the fabrication of ALD heterostructures.
Although ALD is well-suited to depositing MCs, there are still limited studies about the electrical applications of ALD-MCs. Moreover, reports on constructing 2D MC heterostructures by ALD in electronics are also limited. [222,226,287] Considering the attractive features of nanoscale MCs, 2D ALD-MCs and their related heterostructures will play an important role in the development of next-generation electronic devices. Additionally, multinary MCs with tunable properties and improved performance are also worthy of in-depth studies. For example, Mo 1-x W x S 2 exhibits a tunable optical bandgap from 1.87 to 2.00 eV, and displays an improved photocurrent relative to MoS 2 and WS 2 , respectively. [288] Continued research should focus on the broad applications and possibilities provided by ALD-MCs and their derived architectures for advanced electronics and optoelectronics.

Conclusions and Perspective
In summary, this review has outlined recent advances in the fabrication of FET materials using ALD, as well as assessed their corresponding performances as integrated devices. The wellestablished merits of ALD yielded FET materials with atomically precise layer thickness, whilst maintaining conformality to numerous substrate/device architectures. The large variety of key FET materials fabricated using ALD includes semiconductor channels, dielectrics, passivation/encapsulation layers, electrodes, and electrode interlayers, highlighting the benefits of ALD for FET manufacturing. The continuously expanding library of ALD precursors has enabled numerous MOs and MCs to be deposited as ultrathin films, whilst additional ALD factors facilitate control over stoichiometry, structure and bandgap properties. These factors, in conjunction with electronic performance metrics such as the charge carrier mobility, on/off current ratio, switching speed and device stability, enable the rapid and successive optimization of new materials for applications in FETs and their derived devices. Several wide/medium bandgap n-and p-type MO have been fabricated as channel materials as well as transparent electrodes and electrode interlayers, resulting in improved charge transport and signal switching. Large bandgap MOs have also served as effective gate dielectrics or protecting/encapsulating layers for enhancing device performance, particularly the durability and operational stability. The rapid development of 2D materials and devices has also triggered investigation on the design of ALD-MCs as promising channel materials for n-type and p-type transistors. These narrow/mediumbandgap semiconductors are used as single channel layers as well as heterostructures for promoting charge transport, photodetection, gas sensing, and more.
Despite significant progress, ALD application still requires the development of cost-effective precursors and methods, to further promote the integration of FET materials in high-performance devices. Previous reports have focused on n-type MO and MC semiconductors due to the absence of p-type and bipolar counterparts. Impressively, reports of some p-type semiconductors derived from ALD, including SnO, CuO, Cu 2 O, WS 2 and WSe 2 , SnS and SnSe, as well as InSe, highlight the growing progress of p-type ALD materials. Examples such as ZnO, TiO 2 , and lead chalcogenides may also display a transition to p-type characteristics through appropriate doping with heteroatoms, substrate selection, and enrichment with metal elements. However, further research on p-type materials using ALD is required for a more detailed evaluation of their electric, optoelectronic and mechanical properties, as well as their device stability (e.g., operational stability, air stability, photostability, bending stability, and so forth).
The capacity for ALD to tune the composition of MOs and MCs makes it well adapted to explore multinary FET materials. By controlling ALD reaction parameters (e.g., temperature, time, precursor, substrate, and pre-/post-treatment, etc.), thin-film fabrication according to a desired stoichiometric composition affords facile optimization possibilities for the bandgap, mobility, and other physical/chemical properties. Moreover, ALD has the potential to fabricate more complex heterostructures in a manner that is not accessible with other techniques, but currently remains underexplored. For example, simple alternating bilayers of MO insulators have proven an effective adaptation for shielding devices against atmospheric water and oxygen surface adsorption. Design of such heterostructure using ALD is a promising strategy for boosting the electrical performance of FET devices using MO/MO, MC/MC, and hybrid MO/MC architectures. In addition, the uniqueness of ALD may also provoke greater integration of ALD techniques with other established methods (i.e., 3D printing, inject printing, flexographic printing, solutionprocess patterning, and laser processing, etc.) towards advanced FET design and fabrication, which may prove useful for developing future micro-/nano-scale structures and devices.
The successful demonstration of ALD of MOs and MCs in high-performance FETs reflects their promising potential as www.advancedsciencenews.com www.advancedscience.com future components within electronic devices such as inverters, oscillators, and integrated circuits. In addition, other ALDderived materials, such as III-V group semiconductors, metal nitrides, metal halides, perovskites, and hybrids, also show significant potential in advanced electronics and semiconductorintegrated systems. However, current researches on most ALD-materials still mainly focus on individual FET fabrication and is limited to laboratory-scale. Meanwhile, translation of the ALD processes to device arrays based on FETs is an important step for developing the technology for larger-scale manufacturing. This demand may stimulate the adoption of ALD-FETs within newly emerging technologies such as multifunctional sensing, artificial synapses, self-driving systems, smart manufacturing as well as an intelligent medical diagnosis and health monitoring. The emerging ALD processes of MOs and MCs with tunable compositions, structures, and electronic properties can provide the possibility to optimize optoelectronic and mechanical properties and promote widespread applications within electronics, photonics, information, and Internet of Things. Nowadays, the ever-developing uses of artificial intelligence (AI) are accelerating the discovery and deployment of advanced materials as well as functional devices. [289] Thus AI techniques such as machine learning and deep learning may be used to further develop ALD-derived materials and FETs/chips for flexible circuits, actuators, intelligent robotics, integrated networks of quantum devices, wearable applications, and human-machine interactions, etc. Moreover, the electronic information industry continues to gradually favor low-power electronic devices as a strategy to reduce carbon emissions and achieve global carbon neutrality. [290] Therefore, emphasis must be placed on the fabrication of electronic materials and devices by ALD, that match the growing global demands for green and sustainable electronics. The coming decades will continue to witness the rapid development in both improved ALD technologies and the availability of diverse MOs, MCs, and other emerging materials for new-generation devices and realistic applications.